| /third_party/uboot/u-boot-2020.01/include/configs/ |
| D | MPC8349EMDS.h | 81 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 macro
94 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ macro
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| D | MPC8349EMDS_SDRAM.h | 81 #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 macro
94 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ macro
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| D | socrates.h | 84 #define CONFIG_SYS_DDR_TIMING_2 0x14904CC8 macro
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| D | mpc8308_p1m.h | 83 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
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| D | MPC832XEMDS.h | 58 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
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| D | ve8313.h | 71 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
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| D | MPC8308RDB.h | 79 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
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| D | sbc8349.h | 70 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ macro
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| D | MPC8540ADS.h | 87 #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ macro
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| D | ids8313.h | 77 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) |\ macro
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| D | MPC8323ERDB.h | 58 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
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| D | MPC8313ERDB_NOR.h | 94 #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ macro
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| /third_party/uboot/u-boot-2020.01/board/freescale/mpc8349emds/ |
| D | mpc8349emds.c | 105 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
130 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
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| /third_party/uboot/u-boot-2020.01/include/configs/km/ |
| D | km-mpc8360.h | 72 #define CONFIG_SYS_DDR_TIMING_2 (\ macro
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| D | km-mpc832x.h | 75 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ macro
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| D | km-mpc8309.h | 110 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \ macro
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| /third_party/uboot/u-boot-2020.01/board/freescale/p1_twr/ |
| D | ddr.c | 34 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2, in fixed_sdram()
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| /third_party/uboot/u-boot-2020.01/board/socrates/ |
| D | sdram.c | 39 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
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| /third_party/uboot/u-boot-2020.01/board/gdsys/mpc8308/ |
| D | sdram.c | 52 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
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| /third_party/uboot/u-boot-2020.01/board/mpc8308_p1m/ |
| D | sdram.c | 45 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
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| /third_party/uboot/u-boot-2020.01/board/freescale/mpc8308rdb/ |
| D | sdram.c | 49 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); in fixed_sdram()
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| /third_party/uboot/u-boot-2020.01/board/freescale/mpc8315erdb/ |
| D | sdram.c | 66 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
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| /third_party/uboot/u-boot-2020.01/board/freescale/mpc832xemds/ |
| D | mpc832xemds.c | 139 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
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| /third_party/uboot/u-boot-2020.01/board/freescale/mpc8313erdb/ |
| D | sdram.c | 75 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2; in fixed_sdram()
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| /third_party/uboot/u-boot-2020.01/board/Arcturus/ucp1020/ |
| D | ddr.c | 94 .timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2, in fixed_sdram()
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