| /third_party/uboot/u-boot-2020.01/arch/arm/include/asm/arch-hi3660/ |
| D | hi3660.h | 19 #define CRG_REG_BASE 0xfff35000 macro
20 #define CRG_PEREN2 (CRG_REG_BASE + 0x020)
21 #define CRG_PERDIS2 (CRG_REG_BASE + 0x024)
22 #define CRG_PERCLKEN2 (CRG_REG_BASE + 0x028)
23 #define CRG_PERSTAT2 (CRG_REG_BASE + 0x02C)
24 #define CRG_PEREN4 (CRG_REG_BASE + 0x040)
25 #define CRG_PERDIS4 (CRG_REG_BASE + 0x044)
26 #define CRG_PERCLKEN4 (CRG_REG_BASE + 0x048)
27 #define CRG_PERSTAT4 (CRG_REG_BASE + 0x04C)
28 #define CRG_PERRSTEN2 (CRG_REG_BASE + 0x078)
[all …]
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| /third_party/uboot/u-boot-2020.01/drivers/phy/hibvt/ |
| D | phy-usb-hi3516dv300.c | 144 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
146 writel(reg, CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
150 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
152 writel(reg, CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
156 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
158 writel(reg, CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
162 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
164 writel(reg, CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
168 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
170 writel(reg, CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
[all …]
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| D | phy-usb-hi3556v200.c | 145 reg = readl(CRG_REG_BASE + REG_CRG80); in hisi_usb_init_clk()
147 writel(reg, CRG_REG_BASE + REG_CRG80); in hisi_usb_init_clk()
151 reg = readl(CRG_REG_BASE + REG_CRG80); in hisi_usb_init_clk()
153 writel(reg, CRG_REG_BASE + REG_CRG80); in hisi_usb_init_clk()
157 reg = readl(CRG_REG_BASE + REG_CRG80); in hisi_usb_init_clk()
159 writel(reg, CRG_REG_BASE + REG_CRG80); in hisi_usb_init_clk()
163 reg = readl(CRG_REG_BASE + REG_CRG80); in hisi_usb_init_clk()
165 writel(reg, CRG_REG_BASE + REG_CRG80); in hisi_usb_init_clk()
169 reg = readl(CRG_REG_BASE + REG_CRG80); in hisi_usb_init_clk()
171 writel(reg, CRG_REG_BASE + REG_CRG80); in hisi_usb_init_clk()
[all …]
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| D | phy-usb-hi3559v200.c | 145 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
147 writel(reg, CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
151 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
153 writel(reg, CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
157 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
159 writel(reg, CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
163 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
165 writel(reg, CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
169 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
171 writel(reg, CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
[all …]
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| D | phy-usb-hi3516cv500.c | 145 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
147 writel(reg, CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
151 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
153 writel(reg, CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
157 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
159 writel(reg, CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
163 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
165 writel(reg, CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
169 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
171 writel(reg, CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
[all …]
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| D | phy-hi3516dv200-usb.c | 204 writel(reg, CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
208 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
210 writel(reg, CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
213 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
215 writel(reg, CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
218 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
220 writel(reg, CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
223 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
225 writel(reg, CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
228 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
[all …]
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| D | phy-hi3518ev300-usb.c | 204 writel(reg, CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
208 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
210 writel(reg, CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
213 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
215 writel(reg, CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
218 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
220 writel(reg, CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
223 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
225 writel(reg, CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
228 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
[all …]
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| D | phy-hi3516ev300-usb.c | 203 writel(reg, CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
207 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
209 writel(reg, CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
212 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
214 writel(reg, CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
217 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
219 writel(reg, CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
222 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
224 writel(reg, CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
227 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
[all …]
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| D | phy-hi3516ev200-usb.c | 203 writel(reg, CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
207 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
209 writel(reg, CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
212 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
214 writel(reg, CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
217 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
219 writel(reg, CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
222 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
224 writel(reg, CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
227 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
[all …]
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3556av100/ |
| D | ddr_training_custom.c | 22 #define CRG_REG_BASE 0x04510000U macro
40 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
42 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
44 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
46 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
58 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
60 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
62 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
64 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3559av100/ |
| D | ddr_training_custom.c | 22 #define CRG_REG_BASE 0x12010000U macro
40 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
42 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
44 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
46 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
58 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
60 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
62 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
64 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3519av100/ |
| D | ddr_training_custom.c | 22 #define CRG_REG_BASE 0x04510000U macro
40 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
42 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
44 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
46 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
58 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
60 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
62 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
64 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516dv300/ |
| D | ddr_training_custom.c | 22 #define CRG_REG_BASE 0x12010000U macro
40 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
42 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
44 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
46 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
58 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
60 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
62 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
64 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516av300/ |
| D | ddr_training_custom.c | 22 #define CRG_REG_BASE 0x12010000U macro
40 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
42 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
44 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
46 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
58 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
60 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
62 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
64 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516cv500/ |
| D | ddr_training_custom.c | 22 #define CRG_REG_BASE 0x12010000U macro
40 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
42 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
44 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
46 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
58 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
60 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
62 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
64 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516dv200/ |
| D | ddr_training_custom.c | 22 #define CRG_REG_BASE 0x12010000U macro
48 reg->custom.ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
50 ddr_write(reg->custom.ddrt_clk_reg | (1U << 1), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
53 ddr_write(ddr_read(CRG_REG_BASE + PERI_CRG_DDRT) & (~(1U << 0)), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
74 ddr_write(reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
95 ddr_cksel = (ddr_read(CRG_REG_BASE + PERI_CRG_DDRCKSEL) >> 0x3) & 0x7; in ddr_get_cksel()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516ev200/ |
| D | ddr_training_custom.c | 22 #define CRG_REG_BASE 0x12010000U macro
48 reg->custom.ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
50 ddr_write(reg->custom.ddrt_clk_reg | (1U << 1), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
53 ddr_write(ddr_read(CRG_REG_BASE + PERI_CRG_DDRT) & (~(1U << 0)), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
74 ddr_write(reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
95 ddr_cksel = (ddr_read(CRG_REG_BASE + PERI_CRG_DDRCKSEL) >> 0x3) & 0x7; in ddr_get_cksel()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3518ev300/ |
| D | ddr_training_custom.c | 22 #define CRG_REG_BASE 0x12010000U macro
48 reg->custom.ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
50 ddr_write(reg->custom.ddrt_clk_reg | (1U << 1), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
53 ddr_write(ddr_read(CRG_REG_BASE + PERI_CRG_DDRT) & (~(1U << 0)), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
74 ddr_write(reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
95 ddr_cksel = (ddr_read(CRG_REG_BASE + PERI_CRG_DDRCKSEL) >> 0x3) & 0x7; in ddr_get_cksel()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516ev300/ |
| D | ddr_training_custom.c | 22 #define CRG_REG_BASE 0x12010000U macro
48 reg->custom.ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
50 ddr_write(reg->custom.ddrt_clk_reg | (1U << 1), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
53 ddr_write(ddr_read(CRG_REG_BASE + PERI_CRG_DDRT) & (~(1U << 0)), CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_save()
74 ddr_write(reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_cmd_site_restore()
95 ddr_cksel = (ddr_read(CRG_REG_BASE + PERI_CRG_DDRCKSEL) >> 0x3) & 0x7; in ddr_get_cksel()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3535av100/ |
| D | ddr_training_custom.c | 22 #define CRG_REG_BASE 0x11010000U macro
85 relate_reg->custom.ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_cmd_save()
87 …ddr_write(relate_reg->custom.ddrt_clk_reg | (0x1 << DDRTEST0_CKEN_BIT), CRG_REG_BASE + PERI_CRG_DD… in ddr_boot_cmd_save()
90 …ddr_write(ddr_read(CRG_REG_BASE + PERI_CRG_DDRT) & (~(0x1 << DDRTEST0_SRST_REQ_BIT)), CRG_REG_BASE… in ddr_boot_cmd_save()
114 ddr_write(relate_reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_cmd_restore()
132 ddr_cksel = (ddr_read(CRG_REG_BASE + PERI_CRG_DDRCKSEL) >> 0x3) & 0x7; in ddr_get_cksel()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3520dv500/ |
| D | ddr_training_custom.c | 22 #define CRG_REG_BASE 0x11010000U macro
83 relate_reg->custom.ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_cmd_save()
85 …ddr_write(relate_reg->custom.ddrt_clk_reg | (0x1 << DDRTEST0_CKEN_BIT), CRG_REG_BASE + PERI_CRG_DD… in ddr_boot_cmd_save()
88 …ddr_write(ddr_read(CRG_REG_BASE + PERI_CRG_DDRT) & (~(0x1 << DDRTEST0_SRST_REQ_BIT)), CRG_REG_BASE… in ddr_boot_cmd_save()
112 ddr_write(relate_reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_cmd_restore()
130 ddr_cksel = (ddr_read(CRG_REG_BASE + PERI_CRG_DDRCKSEL) >> 0x3) & 0x7; in ddr_get_cksel()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3521dv200/ |
| D | ddr_training_custom.c | 22 #define CRG_REG_BASE 0x11010000U macro
83 relate_reg->custom.ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_cmd_save()
85 …ddr_write(relate_reg->custom.ddrt_clk_reg | (0x1 << DDRTEST0_CKEN_BIT), CRG_REG_BASE + PERI_CRG_DD… in ddr_boot_cmd_save()
88 …ddr_write(ddr_read(CRG_REG_BASE + PERI_CRG_DDRT) & (~(0x1 << DDRTEST0_SRST_REQ_BIT)), CRG_REG_BASE… in ddr_boot_cmd_save()
112 ddr_write(relate_reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_cmd_restore()
130 ddr_cksel = (ddr_read(CRG_REG_BASE + PERI_CRG_DDRCKSEL) >> 0x3) & 0x7; in ddr_get_cksel()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3531dv200/ |
| D | ddr_training_custom.c | 22 #define CRG_REG_BASE 0x11010000U macro
85 relate_reg->custom.ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_cmd_save()
87 …ddr_write(relate_reg->custom.ddrt_clk_reg | (0x1 << DDRTEST0_CKEN_BIT), CRG_REG_BASE + PERI_CRG_DD… in ddr_boot_cmd_save()
90 …ddr_write(ddr_read(CRG_REG_BASE + PERI_CRG_DDRT) & (~(0x1 << DDRTEST0_SRST_REQ_BIT)), CRG_REG_BASE… in ddr_boot_cmd_save()
114 ddr_write(relate_reg->custom.ddrt_clk_reg, CRG_REG_BASE + PERI_CRG_DDRT); in ddr_boot_cmd_restore()
132 ddr_cksel = (ddr_read(CRG_REG_BASE + PERI_CRG_DDRCKSEL) >> 0x3) & 0x7; in ddr_get_cksel()
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| /third_party/uboot/u-boot-2020.01/drivers/mmc/ |
| D | himci_hi3516dv300.c | 128 tmp_reg = himci_readl(CRG_REG_BASE + SDIO0_CRG); in hi_mci_sys_init()
131 himci_writel(tmp_reg, CRG_REG_BASE + SDIO0_CRG); in hi_mci_sys_init()
135 himci_writel(tmp_reg, CRG_REG_BASE + SDIO0_CRG); in hi_mci_sys_init()
139 himci_writel(tmp_reg, CRG_REG_BASE + SDIO0_CRG); in hi_mci_sys_init()
144 tmp_reg = himci_readl(CRG_REG_BASE + EMMC_CRG); in hi_mci_sys_init()
150 himci_writel(tmp_reg, CRG_REG_BASE + EMMC_CRG); in hi_mci_sys_init()
154 himci_writel(tmp_reg, CRG_REG_BASE + EMMC_CRG); in hi_mci_sys_init()
158 himci_writel(tmp_reg, CRG_REG_BASE + EMMC_CRG); in hi_mci_sys_init()
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| D | himci_hi3516cv500.c | 128 tmp_reg = himci_readl(CRG_REG_BASE + SDIO0_CRG); in hi_mci_sys_init()
131 himci_writel(tmp_reg, CRG_REG_BASE + SDIO0_CRG); in hi_mci_sys_init()
135 himci_writel(tmp_reg, CRG_REG_BASE + SDIO0_CRG); in hi_mci_sys_init()
139 himci_writel(tmp_reg, CRG_REG_BASE + SDIO0_CRG); in hi_mci_sys_init()
144 tmp_reg = himci_readl(CRG_REG_BASE + EMMC_CRG); in hi_mci_sys_init()
150 himci_writel(tmp_reg, CRG_REG_BASE + EMMC_CRG); in hi_mci_sys_init()
154 himci_writel(tmp_reg, CRG_REG_BASE + EMMC_CRG); in hi_mci_sys_init()
158 himci_writel(tmp_reg, CRG_REG_BASE + EMMC_CRG); in hi_mci_sys_init()
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