1 /*
2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program. If not, see <http://www.gnu.org/licenses/>.
16 *
17 */
18
19 #include "ddr_interface.h"
20 #include "ddr_training_impl.h"
21
22 #define CRG_REG_BASE 0x12010000U
23 #define PERI_CRG83 0x14CU
24
25 /**
26 * Do some prepare before copy code from DDR to SRAM.
27 * Keep empty when nothing to do.
28 */
ddr_cmd_prepare_copy(void)29 void ddr_cmd_prepare_copy(void) { return; }
30
31 /**
32 * Save site before DDR training command execute .
33 * Keep empty when nothing to do.
34 */
ddr_cmd_site_save(void)35 void ddr_cmd_site_save(void)
36 {
37 unsigned int ddrt_clk_reg;
38
39 /* turn on ddrt clock */
40 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83);
41 ddrt_clk_reg |= (1U << 1); /* enable ddrt0 clock */
42 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83);
43 __asm__ __volatile__("nop");
44 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83);
45 ddrt_clk_reg &= ~(1U << 0); /* disable ddrt0 soft reset */
46 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83);
47 }
48
49 /**
50 * Restore site after DDR training command execute.
51 * Keep empty when nothing to do.
52 */
ddr_cmd_site_restore(void)53 void ddr_cmd_site_restore(void)
54 {
55 unsigned int ddrt_clk_reg;
56
57 /* turn off ddrt clock */
58 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83);
59 ddrt_clk_reg |= (1U << 0); /* eable ddrt0 soft reset */
60 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83);
61 __asm__ __volatile__("nop");
62 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83);
63 ddrt_clk_reg &= ~(1U << 1); /* disable ddrt0 clock */
64 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83);
65 }
66
ddr_training_save_reg_custom(void * reg,unsigned int mask)67 void ddr_training_save_reg_custom(void *reg, unsigned int mask) { return; }
ddr_training_restore_reg_custom(void * reg)68 void ddr_training_restore_reg_custom(void *reg) { return; }