Searched refs:PERI_CRG83 (Results 1 – 3 of 3) sorted by relevance
| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3556av100/ |
| D | ddr_training_custom.c | 23 #define PERI_CRG83 0x14CU macro
40 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
42 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
44 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
46 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
58 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
60 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
62 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
64 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3559av100/ |
| D | ddr_training_custom.c | 23 #define PERI_CRG83 0x14CU macro
40 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
42 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
44 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
46 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
58 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
60 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
62 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
64 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3519av100/ |
| D | ddr_training_custom.c | 23 #define PERI_CRG83 0x14CU macro
40 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
42 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
44 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
46 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_save()
58 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
60 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
62 ddrt_clk_reg = ddr_read(CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
64 ddr_write(ddrt_clk_reg, CRG_REG_BASE + PERI_CRG83); in ddr_cmd_site_restore()
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