Searched refs:ddr_mode (Results 1 – 16 of 16) sorted by relevance
782 MV_DRAM_MODES *ddr_mode; in ddr3_static_training_init() local786 ddr_mode = ddr3_get_static_ddr_mode(); in ddr3_static_training_init()789 while (ddr_mode->vals[j].reg_addr != 0) { in ddr3_static_training_init()791 reg_write(ddr_mode->vals[j].reg_addr, in ddr3_static_training_init()792 ddr_mode->vals[j].reg_value); in ddr3_static_training_init()794 if (ddr_mode->vals[j].reg_addr == in ddr3_static_training_init()882 MV_DRAM_MODES *ddr_mode; in ddr3_static_mc_init() local886 ddr_mode = ddr3_get_static_ddr_mode(); in ddr3_static_mc_init()888 while (ddr_mode->regs[j].reg_addr != 0) { in ddr3_static_mc_init()889 reg_write(ddr_mode->regs[j].reg_addr, in ddr3_static_mc_init()[all …]
42 enum ddr_mode mem_type; /* Type of on-board memory */
431 enum ddr_mode { enum
251 if (host->mmc->ddr_mode) { in xenon_mmc_phy_set()343 if (host->mmc->ddr_mode) in xenon_sdhci_set_ios_post()357 if (host->mmc->ddr_mode) in xenon_sdhci_set_ios_post()
147 if (mmc->ddr_mode) in sdhci_cdns_set_control_reg()152 if (mmc->ddr_mode) in sdhci_cdns_set_control_reg()
553 if (mmc->ddr_mode) in tmio_sd_set_ddr_mode()577 if (mmc->ddr_mode && (divisor == 1)) in tmio_sd_set_clk_rate()666 mmc->clock, mmc->ddr_mode, mmc->bus_width); in tmio_sd_set_ios()
146 if (host->mmc->ddr_mode) in sdhci_iproc_set_ios_post()
127 timeout /= mmc->ddr_mode ? 2 : 1; in dwmci_get_timeout()489 if (mmc->ddr_mode)
192 mmc->ddr_mode = mmc_is_mode_ddr(mode); in mmc_select_mode()280 if (mmc->ddr_mode) in mmc_set_blocklen()2579 if (mmc->ddr_mode) { in mmc_startup()2790 mmc->ddr_mode = 0; in mmc_get_op_cond()
475 | (mmc->ddr_mode ? XFERTYP_DDREN : 0)); in esdhc_send_cmd_common()627 int ddr_pre_div = mmc->ddr_mode ? 2 : 1; in set_sysctl()
40 enum ddr_mode mem_type; /* Memory type */
75 void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode mode) in update_reset_dll()
484 static void clock_get_mem_selection(enum ddr_mode *mem_type, in clock_get_mem_selection()501 enum ddr_mode mem_type; in get_arm_ratios()525 enum ddr_mode mem_type; in clock_get_mem_timings()
945 void update_reset_dll(uint32_t *phycontrol0, enum ddr_mode);
655 int ddr_mode; member
50 mmc->ddr_mode ? " DDR" : ""); in print_mmcinfo()