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1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
4  * Copyright 2019 NXP Semiconductors
5  * Andy Fleming
6  * Yangbo Lu <yangbo.lu@nxp.com>
7  *
8  * Based vaguely on the pxa mmc code:
9  * (C) Copyright 2003
10  * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
11  */
12 
13 #include <config.h>
14 #include <common.h>
15 #include <command.h>
16 #include <clk.h>
17 #include <cpu_func.h>
18 #include <errno.h>
19 #include <hwconfig.h>
20 #include <mmc.h>
21 #include <part.h>
22 #include <power/regulator.h>
23 #include <malloc.h>
24 #include <fsl_esdhc_imx.h>
25 #include <fdt_support.h>
26 #include <asm/io.h>
27 #include <dm.h>
28 #include <asm-generic/gpio.h>
29 #include <dm/pinctrl.h>
30 
31 #if !CONFIG_IS_ENABLED(BLK)
32 #include "mmc_private.h"
33 #endif
34 
35 DECLARE_GLOBAL_DATA_PTR;
36 
37 #define SDHCI_IRQ_EN_BITS		(IRQSTATEN_CC | IRQSTATEN_TC | \
38 				IRQSTATEN_CINT | \
39 				IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
40 				IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
41 				IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
42 				IRQSTATEN_DINT)
43 #define MAX_TUNING_LOOP 40
44 #define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
45 
46 struct fsl_esdhc {
47 	uint    dsaddr;		/* SDMA system address register */
48 	uint    blkattr;	/* Block attributes register */
49 	uint    cmdarg;		/* Command argument register */
50 	uint    xfertyp;	/* Transfer type register */
51 	uint    cmdrsp0;	/* Command response 0 register */
52 	uint    cmdrsp1;	/* Command response 1 register */
53 	uint    cmdrsp2;	/* Command response 2 register */
54 	uint    cmdrsp3;	/* Command response 3 register */
55 	uint    datport;	/* Buffer data port register */
56 	uint    prsstat;	/* Present state register */
57 	uint    proctl;		/* Protocol control register */
58 	uint    sysctl;		/* System Control Register */
59 	uint    irqstat;	/* Interrupt status register */
60 	uint    irqstaten;	/* Interrupt status enable register */
61 	uint    irqsigen;	/* Interrupt signal enable register */
62 	uint    autoc12err;	/* Auto CMD error status register */
63 	uint    hostcapblt;	/* Host controller capabilities register */
64 	uint    wml;		/* Watermark level register */
65 	uint    mixctrl;	/* For USDHC */
66 	char    reserved1[4];	/* reserved */
67 	uint    fevt;		/* Force event register */
68 	uint    admaes;		/* ADMA error status register */
69 	uint    adsaddr;	/* ADMA system address register */
70 	char    reserved2[4];
71 	uint    dllctrl;
72 	uint    dllstat;
73 	uint    clktunectrlstatus;
74 	char    reserved3[4];
75 	uint	strobe_dllctrl;
76 	uint	strobe_dllstat;
77 	char    reserved4[72];
78 	uint    vendorspec;
79 	uint    mmcboot;
80 	uint    vendorspec2;
81 	uint    tuning_ctrl;	/* on i.MX6/7/8 */
82 	char	reserved5[44];
83 	uint    hostver;	/* Host controller version register */
84 	char    reserved6[4];	/* reserved */
85 	uint    dmaerraddr;	/* DMA error address register */
86 	char    reserved7[4];	/* reserved */
87 	uint    dmaerrattr;	/* DMA error attribute register */
88 	char    reserved8[4];	/* reserved */
89 	uint    hostcapblt2;	/* Host controller capabilities register 2 */
90 	char    reserved9[8];	/* reserved */
91 	uint    tcr;		/* Tuning control register */
92 	char    reserved10[28];	/* reserved */
93 	uint    sddirctl;	/* SD direction control register */
94 	char    reserved11[712];/* reserved */
95 	uint    scr;		/* eSDHC control register */
96 };
97 
98 struct fsl_esdhc_plat {
99 	struct mmc_config cfg;
100 	struct mmc mmc;
101 };
102 
103 struct esdhc_soc_data {
104 	u32 flags;
105 };
106 
107 /**
108  * struct fsl_esdhc_priv
109  *
110  * @esdhc_regs: registers of the sdhc controller
111  * @sdhc_clk: Current clk of the sdhc controller
112  * @bus_width: bus width, 1bit, 4bit or 8bit
113  * @cfg: mmc config
114  * @mmc: mmc
115  * Following is used when Driver Model is enabled for MMC
116  * @dev: pointer for the device
117  * @non_removable: 0: removable; 1: non-removable
118  * @wp_enable: 1: enable checking wp; 0: no check
119  * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
120  * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
121  * @caps: controller capabilities
122  * @tuning_step: tuning step setting in tuning_ctrl register
123  * @start_tuning_tap: the start point for tuning in tuning_ctrl register
124  * @strobe_dll_delay_target: settings in strobe_dllctrl
125  * @signal_voltage: indicating the current voltage
126  * @cd_gpio: gpio for card detection
127  * @wp_gpio: gpio for write protection
128  */
129 struct fsl_esdhc_priv {
130 	struct fsl_esdhc *esdhc_regs;
131 	unsigned int sdhc_clk;
132 	struct clk per_clk;
133 	unsigned int clock;
134 	unsigned int mode;
135 	unsigned int bus_width;
136 #if !CONFIG_IS_ENABLED(BLK)
137 	struct mmc *mmc;
138 #endif
139 	struct udevice *dev;
140 	int non_removable;
141 	int wp_enable;
142 	int vs18_enable;
143 	u32 flags;
144 	u32 caps;
145 	u32 tuning_step;
146 	u32 tuning_start_tap;
147 	u32 strobe_dll_delay_target;
148 	u32 signal_voltage;
149 #if CONFIG_IS_ENABLED(DM_REGULATOR)
150 	struct udevice *vqmmc_dev;
151 	struct udevice *vmmc_dev;
152 #endif
153 #ifdef CONFIG_DM_GPIO
154 	struct gpio_desc cd_gpio;
155 	struct gpio_desc wp_gpio;
156 #endif
157 };
158 
159 /* Return the XFERTYP flags for a given command and data packet */
esdhc_xfertyp(struct mmc_cmd * cmd,struct mmc_data * data)160 static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
161 {
162 	uint xfertyp = 0;
163 
164 	if (data) {
165 		xfertyp |= XFERTYP_DPSEL;
166 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
167 		xfertyp |= XFERTYP_DMAEN;
168 #endif
169 		if (data->blocks > 1) {
170 			xfertyp |= XFERTYP_MSBSEL;
171 			xfertyp |= XFERTYP_BCEN;
172 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
173 			xfertyp |= XFERTYP_AC12EN;
174 #endif
175 		}
176 
177 		if (data->flags & MMC_DATA_READ)
178 			xfertyp |= XFERTYP_DTDSEL;
179 	}
180 
181 	if (cmd->resp_type & MMC_RSP_CRC)
182 		xfertyp |= XFERTYP_CCCEN;
183 	if (cmd->resp_type & MMC_RSP_OPCODE)
184 		xfertyp |= XFERTYP_CICEN;
185 	if (cmd->resp_type & MMC_RSP_136)
186 		xfertyp |= XFERTYP_RSPTYP_136;
187 	else if (cmd->resp_type & MMC_RSP_BUSY)
188 		xfertyp |= XFERTYP_RSPTYP_48_BUSY;
189 	else if (cmd->resp_type & MMC_RSP_PRESENT)
190 		xfertyp |= XFERTYP_RSPTYP_48;
191 
192 	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
193 		xfertyp |= XFERTYP_CMDTYP_ABORT;
194 
195 	return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
196 }
197 
198 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
199 /*
200  * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
201  */
esdhc_pio_read_write(struct fsl_esdhc_priv * priv,struct mmc_data * data)202 static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
203 				 struct mmc_data *data)
204 {
205 	struct fsl_esdhc *regs = priv->esdhc_regs;
206 	uint blocks;
207 	char *buffer;
208 	uint databuf;
209 	uint size;
210 	uint irqstat;
211 	ulong start;
212 
213 	if (data->flags & MMC_DATA_READ) {
214 		blocks = data->blocks;
215 		buffer = data->dest;
216 		while (blocks) {
217 			start = get_timer(0);
218 			size = data->blocksize;
219 			irqstat = esdhc_read32(&regs->irqstat);
220 			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
221 				if (get_timer(start) > PIO_TIMEOUT) {
222 					printf("\nData Read Failed in PIO Mode.");
223 					return;
224 				}
225 			}
226 			while (size && (!(irqstat & IRQSTAT_TC))) {
227 				udelay(100); /* Wait before last byte transfer complete */
228 				irqstat = esdhc_read32(&regs->irqstat);
229 				databuf = in_le32(&regs->datport);
230 				*((uint *)buffer) = databuf;
231 				buffer += 4;
232 				size -= 4;
233 			}
234 			blocks--;
235 		}
236 	} else {
237 		blocks = data->blocks;
238 		buffer = (char *)data->src;
239 		while (blocks) {
240 			start = get_timer(0);
241 			size = data->blocksize;
242 			irqstat = esdhc_read32(&regs->irqstat);
243 			while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
244 				if (get_timer(start) > PIO_TIMEOUT) {
245 					printf("\nData Write Failed in PIO Mode.");
246 					return;
247 				}
248 			}
249 			while (size && (!(irqstat & IRQSTAT_TC))) {
250 				udelay(100); /* Wait before last byte transfer complete */
251 				databuf = *((uint *)buffer);
252 				buffer += 4;
253 				size -= 4;
254 				irqstat = esdhc_read32(&regs->irqstat);
255 				out_le32(&regs->datport, databuf);
256 			}
257 			blocks--;
258 		}
259 	}
260 }
261 #endif
262 
esdhc_setup_data(struct fsl_esdhc_priv * priv,struct mmc * mmc,struct mmc_data * data)263 static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
264 			    struct mmc_data *data)
265 {
266 	int timeout;
267 	struct fsl_esdhc *regs = priv->esdhc_regs;
268 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
269 	dma_addr_t addr;
270 #endif
271 	uint wml_value;
272 
273 	wml_value = data->blocksize/4;
274 
275 	if (data->flags & MMC_DATA_READ) {
276 		if (wml_value > WML_RD_WML_MAX)
277 			wml_value = WML_RD_WML_MAX_VAL;
278 
279 		esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
280 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
281 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
282 		addr = virt_to_phys((void *)(data->dest));
283 		if (upper_32_bits(addr))
284 			printf("Error found for upper 32 bits\n");
285 		else
286 			esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
287 #else
288 		esdhc_write32(&regs->dsaddr, (u32)data->dest);
289 #endif
290 #endif
291 	} else {
292 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
293 		flush_dcache_range((ulong)data->src,
294 				   (ulong)data->src+data->blocks
295 					 *data->blocksize);
296 #endif
297 		if (wml_value > WML_WR_WML_MAX)
298 			wml_value = WML_WR_WML_MAX_VAL;
299 		if (priv->wp_enable) {
300 			if ((esdhc_read32(&regs->prsstat) &
301 			    PRSSTAT_WPSPL) == 0) {
302 				printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
303 				return -ETIMEDOUT;
304 			}
305 		} else {
306 #ifdef CONFIG_DM_GPIO
307 			if (dm_gpio_is_valid(&priv->wp_gpio) && dm_gpio_get_value(&priv->wp_gpio)) {
308 				printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
309 				return -ETIMEDOUT;
310 			}
311 #endif
312 		}
313 
314 		esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
315 					wml_value << 16);
316 #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
317 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
318 		addr = virt_to_phys((void *)(data->src));
319 		if (upper_32_bits(addr))
320 			printf("Error found for upper 32 bits\n");
321 		else
322 			esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
323 #else
324 		esdhc_write32(&regs->dsaddr, (u32)data->src);
325 #endif
326 #endif
327 	}
328 
329 	esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
330 
331 	/* Calculate the timeout period for data transactions */
332 	/*
333 	 * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
334 	 * 2)Timeout period should be minimum 0.250sec as per SD Card spec
335 	 *  So, Number of SD Clock cycles for 0.25sec should be minimum
336 	 *		(SD Clock/sec * 0.25 sec) SD Clock cycles
337 	 *		= (mmc->clock * 1/4) SD Clock cycles
338 	 * As 1) >=  2)
339 	 * => (2^(timeout+13)) >= mmc->clock * 1/4
340 	 * Taking log2 both the sides
341 	 * => timeout + 13 >= log2(mmc->clock/4)
342 	 * Rounding up to next power of 2
343 	 * => timeout + 13 = log2(mmc->clock/4) + 1
344 	 * => timeout + 13 = fls(mmc->clock/4)
345 	 *
346 	 * However, the MMC spec "It is strongly recommended for hosts to
347 	 * implement more than 500ms timeout value even if the card
348 	 * indicates the 250ms maximum busy length."  Even the previous
349 	 * value of 300ms is known to be insufficient for some cards.
350 	 * So, we use
351 	 * => timeout + 13 = fls(mmc->clock/2)
352 	 */
353 	timeout = fls(mmc->clock/2);
354 	timeout -= 13;
355 
356 	if (timeout > 14)
357 		timeout = 14;
358 
359 	if (timeout < 0)
360 		timeout = 0;
361 
362 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
363 	if ((timeout == 4) || (timeout == 8) || (timeout == 12))
364 		timeout++;
365 #endif
366 
367 #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
368 	timeout = 0xE;
369 #endif
370 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
371 
372 	return 0;
373 }
374 
check_and_invalidate_dcache_range(struct mmc_cmd * cmd,struct mmc_data * data)375 static void check_and_invalidate_dcache_range
376 	(struct mmc_cmd *cmd,
377 	 struct mmc_data *data) {
378 	unsigned start = 0;
379 	unsigned end = 0;
380 	unsigned size = roundup(ARCH_DMA_MINALIGN,
381 				data->blocks*data->blocksize);
382 #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
383 	dma_addr_t addr;
384 
385 	addr = virt_to_phys((void *)(data->dest));
386 	if (upper_32_bits(addr))
387 		printf("Error found for upper 32 bits\n");
388 	else
389 		start = lower_32_bits(addr);
390 #else
391 	start = (unsigned)data->dest;
392 #endif
393 	end = start + size;
394 	invalidate_dcache_range(start, end);
395 }
396 
397 #ifdef CONFIG_MCF5441x
398 /*
399  * Swaps 32-bit words to little-endian byte order.
400  */
sd_swap_dma_buff(struct mmc_data * data)401 static inline void sd_swap_dma_buff(struct mmc_data *data)
402 {
403 	int i, size = data->blocksize >> 2;
404 	u32 *buffer = (u32 *)data->dest;
405 	u32 sw;
406 
407 	while (data->blocks--) {
408 		for (i = 0; i < size; i++) {
409 			sw = __sw32(*buffer);
410 			*buffer++ = sw;
411 		}
412 	}
413 }
414 #endif
415 
416 /*
417  * Sends a command out on the bus.  Takes the mmc pointer,
418  * a command pointer, and an optional data pointer.
419  */
esdhc_send_cmd_common(struct fsl_esdhc_priv * priv,struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)420 static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
421 				 struct mmc_cmd *cmd, struct mmc_data *data)
422 {
423 	int	err = 0;
424 	uint	xfertyp;
425 	uint	irqstat;
426 	u32	flags = IRQSTAT_CC | IRQSTAT_CTOE;
427 	struct fsl_esdhc *regs = priv->esdhc_regs;
428 	unsigned long start;
429 
430 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
431 	if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
432 		return 0;
433 #endif
434 
435 	esdhc_write32(&regs->irqstat, -1);
436 
437 	sync();
438 
439 	/* Wait for the bus to be idle */
440 	while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
441 			(esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
442 		;
443 
444 	while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
445 		;
446 
447 	/* Wait at least 8 SD clock cycles before the next command */
448 	/*
449 	 * Note: This is way more than 8 cycles, but 1ms seems to
450 	 * resolve timing issues with some cards
451 	 */
452 	udelay(1000);
453 
454 	/* Set up for a data transfer if we have one */
455 	if (data) {
456 		err = esdhc_setup_data(priv, mmc, data);
457 		if(err)
458 			return err;
459 
460 		if (data->flags & MMC_DATA_READ)
461 			check_and_invalidate_dcache_range(cmd, data);
462 	}
463 
464 	/* Figure out the transfer arguments */
465 	xfertyp = esdhc_xfertyp(cmd, data);
466 
467 	/* Mask all irqs */
468 	esdhc_write32(&regs->irqsigen, 0);
469 
470 	/* Send the command */
471 	esdhc_write32(&regs->cmdarg, cmd->cmdarg);
472 #if defined(CONFIG_FSL_USDHC)
473 	esdhc_write32(&regs->mixctrl,
474 	(esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
475 			| (mmc->ddr_mode ? XFERTYP_DDREN : 0));
476 	esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
477 #else
478 	esdhc_write32(&regs->xfertyp, xfertyp);
479 #endif
480 
481 	if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
482 	    (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
483 		flags = IRQSTAT_BRR;
484 
485 	/* Wait for the command to complete */
486 	start = get_timer(0);
487 	while (!(esdhc_read32(&regs->irqstat) & flags)) {
488 		if (get_timer(start) > 1000) {
489 			err = -ETIMEDOUT;
490 			goto out;
491 		}
492 	}
493 
494 	irqstat = esdhc_read32(&regs->irqstat);
495 
496 	if (irqstat & CMD_ERR) {
497 		err = -ECOMM;
498 		goto out;
499 	}
500 
501 	if (irqstat & IRQSTAT_CTOE) {
502 		err = -ETIMEDOUT;
503 		goto out;
504 	}
505 
506 	/* Switch voltage to 1.8V if CMD11 succeeded */
507 	if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
508 		esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
509 
510 		printf("Run CMD11 1.8V switch\n");
511 		/* Sleep for 5 ms - max time for card to switch to 1.8V */
512 		udelay(5000);
513 	}
514 
515 	/* Workaround for ESDHC errata ENGcm03648 */
516 	if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
517 		int timeout = 50000;
518 
519 		/* Poll on DATA0 line for cmd with busy signal for 5000 ms */
520 		while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
521 					PRSSTAT_DAT0)) {
522 			udelay(100);
523 			timeout--;
524 		}
525 
526 		if (timeout <= 0) {
527 			printf("Timeout waiting for DAT0 to go high!\n");
528 			err = -ETIMEDOUT;
529 			goto out;
530 		}
531 	}
532 
533 	/* Copy the response to the response buffer */
534 	if (cmd->resp_type & MMC_RSP_136) {
535 		u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
536 
537 		cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
538 		cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
539 		cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
540 		cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
541 		cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
542 		cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
543 		cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
544 		cmd->response[3] = (cmdrsp0 << 8);
545 	} else
546 		cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
547 
548 	/* Wait until all of the blocks are transferred */
549 	if (data) {
550 #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
551 		esdhc_pio_read_write(priv, data);
552 #else
553 		flags = DATA_COMPLETE;
554 		if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
555 		    (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
556 			flags = IRQSTAT_BRR;
557 		}
558 
559 		do {
560 			irqstat = esdhc_read32(&regs->irqstat);
561 
562 			if (irqstat & IRQSTAT_DTOE) {
563 				err = -ETIMEDOUT;
564 				goto out;
565 			}
566 
567 			if (irqstat & DATA_ERR) {
568 				err = -ECOMM;
569 				goto out;
570 			}
571 		} while ((irqstat & flags) != flags);
572 
573 		/*
574 		 * Need invalidate the dcache here again to avoid any
575 		 * cache-fill during the DMA operations such as the
576 		 * speculative pre-fetching etc.
577 		 */
578 		if (data->flags & MMC_DATA_READ) {
579 			check_and_invalidate_dcache_range(cmd, data);
580 #ifdef CONFIG_MCF5441x
581 			sd_swap_dma_buff(data);
582 #endif
583 		}
584 #endif
585 	}
586 
587 out:
588 	/* Reset CMD and DATA portions on error */
589 	if (err) {
590 		esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
591 			      SYSCTL_RSTC);
592 		while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
593 			;
594 
595 		if (data) {
596 			esdhc_write32(&regs->sysctl,
597 				      esdhc_read32(&regs->sysctl) |
598 				      SYSCTL_RSTD);
599 			while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
600 				;
601 		}
602 
603 		/* If this was CMD11, then notify that power cycle is needed */
604 		if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
605 			printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
606 	}
607 
608 	esdhc_write32(&regs->irqstat, -1);
609 
610 	return err;
611 }
612 
set_sysctl(struct fsl_esdhc_priv * priv,struct mmc * mmc,uint clock)613 static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
614 {
615 	struct fsl_esdhc *regs = priv->esdhc_regs;
616 	int div = 1;
617 #ifdef ARCH_MXC
618 #ifdef CONFIG_MX53
619 	/* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
620 	int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
621 #else
622 	int pre_div = 1;
623 #endif
624 #else
625 	int pre_div = 2;
626 #endif
627 	int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
628 	int sdhc_clk = priv->sdhc_clk;
629 	uint clk;
630 
631 	while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
632 		pre_div *= 2;
633 
634 	while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
635 		div++;
636 
637 	pre_div >>= 1;
638 	div -= 1;
639 
640 	clk = (pre_div << 8) | (div << 4);
641 
642 #ifdef CONFIG_FSL_USDHC
643 	esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
644 #else
645 	esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
646 #endif
647 
648 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
649 
650 	udelay(10000);
651 
652 #ifdef CONFIG_FSL_USDHC
653 	esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
654 #else
655 	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
656 #endif
657 
658 	priv->clock = clock;
659 }
660 
661 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
esdhc_clock_control(struct fsl_esdhc_priv * priv,bool enable)662 static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable)
663 {
664 	struct fsl_esdhc *regs = priv->esdhc_regs;
665 	u32 value;
666 	u32 time_out;
667 
668 	value = esdhc_read32(&regs->sysctl);
669 
670 	if (enable)
671 		value |= SYSCTL_CKEN;
672 	else
673 		value &= ~SYSCTL_CKEN;
674 
675 	esdhc_write32(&regs->sysctl, value);
676 
677 	time_out = 20;
678 	value = PRSSTAT_SDSTB;
679 	while (!(esdhc_read32(&regs->prsstat) & value)) {
680 		if (time_out == 0) {
681 			printf("fsl_esdhc: Internal clock never stabilised.\n");
682 			break;
683 		}
684 		time_out--;
685 		mdelay(1);
686 	}
687 }
688 #endif
689 
690 #ifdef MMC_SUPPORTS_TUNING
esdhc_change_pinstate(struct udevice * dev)691 static int esdhc_change_pinstate(struct udevice *dev)
692 {
693 	struct fsl_esdhc_priv *priv = dev_get_priv(dev);
694 	int ret;
695 
696 	switch (priv->mode) {
697 	case UHS_SDR50:
698 	case UHS_DDR50:
699 		ret = pinctrl_select_state(dev, "state_100mhz");
700 		break;
701 	case UHS_SDR104:
702 	case MMC_HS_200:
703 	case MMC_HS_400:
704 	case MMC_HS_400_ES:
705 		ret = pinctrl_select_state(dev, "state_200mhz");
706 		break;
707 	default:
708 		ret = pinctrl_select_state(dev, "default");
709 		break;
710 	}
711 
712 	if (ret)
713 		printf("%s %d error\n", __func__, priv->mode);
714 
715 	return ret;
716 }
717 
esdhc_reset_tuning(struct mmc * mmc)718 static void esdhc_reset_tuning(struct mmc *mmc)
719 {
720 	struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
721 	struct fsl_esdhc *regs = priv->esdhc_regs;
722 
723 	if (priv->flags & ESDHC_FLAG_USDHC) {
724 		if (priv->flags & ESDHC_FLAG_STD_TUNING) {
725 			esdhc_clrbits32(&regs->autoc12err,
726 					MIX_CTRL_SMPCLK_SEL |
727 					MIX_CTRL_EXE_TUNE);
728 		}
729 	}
730 }
731 
esdhc_set_strobe_dll(struct mmc * mmc)732 static void esdhc_set_strobe_dll(struct mmc *mmc)
733 {
734 	struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
735 	struct fsl_esdhc *regs = priv->esdhc_regs;
736 	u32 val;
737 
738 	if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
739 		writel(ESDHC_STROBE_DLL_CTRL_RESET, &regs->strobe_dllctrl);
740 
741 		/*
742 		 * enable strobe dll ctrl and adjust the delay target
743 		 * for the uSDHC loopback read clock
744 		 */
745 		val = ESDHC_STROBE_DLL_CTRL_ENABLE |
746 			(priv->strobe_dll_delay_target <<
747 			 ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
748 		writel(val, &regs->strobe_dllctrl);
749 		/* wait 1us to make sure strobe dll status register stable */
750 		mdelay(1);
751 		val = readl(&regs->strobe_dllstat);
752 		if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
753 			pr_warn("HS400 strobe DLL status REF not lock!\n");
754 		if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
755 			pr_warn("HS400 strobe DLL status SLV not lock!\n");
756 	}
757 }
758 
esdhc_set_timing(struct mmc * mmc)759 static int esdhc_set_timing(struct mmc *mmc)
760 {
761 	struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
762 	struct fsl_esdhc *regs = priv->esdhc_regs;
763 	u32 mixctrl;
764 
765 	mixctrl = readl(&regs->mixctrl);
766 	mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
767 
768 	switch (mmc->selected_mode) {
769 	case MMC_LEGACY:
770 	case SD_LEGACY:
771 		esdhc_reset_tuning(mmc);
772 		writel(mixctrl, &regs->mixctrl);
773 		break;
774 	case MMC_HS_400:
775 	case MMC_HS_400_ES:
776 		mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
777 		writel(mixctrl, &regs->mixctrl);
778 		esdhc_set_strobe_dll(mmc);
779 		break;
780 	case MMC_HS:
781 	case MMC_HS_52:
782 	case MMC_HS_200:
783 	case SD_HS:
784 	case UHS_SDR12:
785 	case UHS_SDR25:
786 	case UHS_SDR50:
787 	case UHS_SDR104:
788 		writel(mixctrl, &regs->mixctrl);
789 		break;
790 	case UHS_DDR50:
791 	case MMC_DDR_52:
792 		mixctrl |= MIX_CTRL_DDREN;
793 		writel(mixctrl, &regs->mixctrl);
794 		break;
795 	default:
796 		printf("Not supported %d\n", mmc->selected_mode);
797 		return -EINVAL;
798 	}
799 
800 	priv->mode = mmc->selected_mode;
801 
802 	return esdhc_change_pinstate(mmc->dev);
803 }
804 
esdhc_set_voltage(struct mmc * mmc)805 static int esdhc_set_voltage(struct mmc *mmc)
806 {
807 	struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
808 	struct fsl_esdhc *regs = priv->esdhc_regs;
809 	int ret;
810 
811 	priv->signal_voltage = mmc->signal_voltage;
812 	switch (mmc->signal_voltage) {
813 	case MMC_SIGNAL_VOLTAGE_330:
814 		if (priv->vs18_enable)
815 			return -EIO;
816 #if CONFIG_IS_ENABLED(DM_REGULATOR)
817 		if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
818 			ret = regulator_set_value(priv->vqmmc_dev, 3300000);
819 			if (ret) {
820 				printf("Setting to 3.3V error");
821 				return -EIO;
822 			}
823 			/* Wait for 5ms */
824 			mdelay(5);
825 		}
826 #endif
827 
828 		esdhc_clrbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
829 		if (!(esdhc_read32(&regs->vendorspec) &
830 		    ESDHC_VENDORSPEC_VSELECT))
831 			return 0;
832 
833 		return -EAGAIN;
834 	case MMC_SIGNAL_VOLTAGE_180:
835 #if CONFIG_IS_ENABLED(DM_REGULATOR)
836 		if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
837 			ret = regulator_set_value(priv->vqmmc_dev, 1800000);
838 			if (ret) {
839 				printf("Setting to 1.8V error");
840 				return -EIO;
841 			}
842 		}
843 #endif
844 		esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
845 		if (esdhc_read32(&regs->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
846 			return 0;
847 
848 		return -EAGAIN;
849 	case MMC_SIGNAL_VOLTAGE_120:
850 		return -ENOTSUPP;
851 	default:
852 		return 0;
853 	}
854 }
855 
esdhc_stop_tuning(struct mmc * mmc)856 static void esdhc_stop_tuning(struct mmc *mmc)
857 {
858 	struct mmc_cmd cmd;
859 
860 	cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
861 	cmd.cmdarg = 0;
862 	cmd.resp_type = MMC_RSP_R1b;
863 
864 	dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
865 }
866 
fsl_esdhc_execute_tuning(struct udevice * dev,uint32_t opcode)867 static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
868 {
869 	struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
870 	struct fsl_esdhc_priv *priv = dev_get_priv(dev);
871 	struct fsl_esdhc *regs = priv->esdhc_regs;
872 	struct mmc *mmc = &plat->mmc;
873 	u32 irqstaten = readl(&regs->irqstaten);
874 	u32 irqsigen = readl(&regs->irqsigen);
875 	int i, ret = -ETIMEDOUT;
876 	u32 val, mixctrl;
877 
878 	/* clock tuning is not needed for upto 52MHz */
879 	if (mmc->clock <= 52000000)
880 		return 0;
881 
882 	/* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
883 	if (priv->flags & ESDHC_FLAG_STD_TUNING) {
884 		val = readl(&regs->autoc12err);
885 		mixctrl = readl(&regs->mixctrl);
886 		val &= ~MIX_CTRL_SMPCLK_SEL;
887 		mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
888 
889 		val |= MIX_CTRL_EXE_TUNE;
890 		mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
891 
892 		writel(val, &regs->autoc12err);
893 		writel(mixctrl, &regs->mixctrl);
894 	}
895 
896 	/* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
897 	mixctrl = readl(&regs->mixctrl);
898 	mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
899 	writel(mixctrl, &regs->mixctrl);
900 
901 	writel(IRQSTATEN_BRR, &regs->irqstaten);
902 	writel(IRQSTATEN_BRR, &regs->irqsigen);
903 
904 	/*
905 	 * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
906 	 * of loops reaches 40 times.
907 	 */
908 	for (i = 0; i < MAX_TUNING_LOOP; i++) {
909 		u32 ctrl;
910 
911 		if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
912 			if (mmc->bus_width == 8)
913 				writel(0x7080, &regs->blkattr);
914 			else if (mmc->bus_width == 4)
915 				writel(0x7040, &regs->blkattr);
916 		} else {
917 			writel(0x7040, &regs->blkattr);
918 		}
919 
920 		/* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
921 		val = readl(&regs->mixctrl);
922 		val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
923 		writel(val, &regs->mixctrl);
924 
925 		/* We are using STD tuning, no need to check return value */
926 		mmc_send_tuning(mmc, opcode, NULL);
927 
928 		ctrl = readl(&regs->autoc12err);
929 		if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
930 		    (ctrl & MIX_CTRL_SMPCLK_SEL)) {
931 			/*
932 			 * need to wait some time, make sure sd/mmc fininsh
933 			 * send out tuning data, otherwise, the sd/mmc can't
934 			 * response to any command when the card still out
935 			 * put the tuning data.
936 			 */
937 			mdelay(1);
938 			ret = 0;
939 			break;
940 		}
941 
942 		/* Add 1ms delay for SD and eMMC */
943 		mdelay(1);
944 	}
945 
946 	writel(irqstaten, &regs->irqstaten);
947 	writel(irqsigen, &regs->irqsigen);
948 
949 	esdhc_stop_tuning(mmc);
950 
951 	return ret;
952 }
953 #endif
954 
esdhc_set_ios_common(struct fsl_esdhc_priv * priv,struct mmc * mmc)955 static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
956 {
957 	struct fsl_esdhc *regs = priv->esdhc_regs;
958 	int ret __maybe_unused;
959 	u32 clock;
960 
961 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
962 	/* Select to use peripheral clock */
963 	esdhc_clock_control(priv, false);
964 	esdhc_setbits32(&regs->scr, ESDHCCTL_PCS);
965 	esdhc_clock_control(priv, true);
966 #endif
967 	/* Set the clock speed */
968 	clock = mmc->clock;
969 	if (clock < mmc->cfg->f_min)
970 		clock = mmc->cfg->f_min;
971 
972 	if (priv->clock != clock)
973 		set_sysctl(priv, mmc, clock);
974 
975 #ifdef MMC_SUPPORTS_TUNING
976 	if (mmc->clk_disable) {
977 #ifdef CONFIG_FSL_USDHC
978 		esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
979 #else
980 		esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
981 #endif
982 	} else {
983 #ifdef CONFIG_FSL_USDHC
984 		esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
985 				VENDORSPEC_CKEN);
986 #else
987 		esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
988 #endif
989 	}
990 
991 	if (priv->mode != mmc->selected_mode) {
992 		ret = esdhc_set_timing(mmc);
993 		if (ret) {
994 			printf("esdhc_set_timing error %d\n", ret);
995 			return ret;
996 		}
997 	}
998 
999 	if (priv->signal_voltage != mmc->signal_voltage) {
1000 		ret = esdhc_set_voltage(mmc);
1001 		if (ret) {
1002 			printf("esdhc_set_voltage error %d\n", ret);
1003 			return ret;
1004 		}
1005 	}
1006 #endif
1007 
1008 	/* Set the bus width */
1009 	esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
1010 
1011 	if (mmc->bus_width == 4)
1012 		esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
1013 	else if (mmc->bus_width == 8)
1014 		esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
1015 
1016 	return 0;
1017 }
1018 
esdhc_init_common(struct fsl_esdhc_priv * priv,struct mmc * mmc)1019 static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
1020 {
1021 	struct fsl_esdhc *regs = priv->esdhc_regs;
1022 	ulong start;
1023 
1024 	/* Reset the entire host controller */
1025 	esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
1026 
1027 	/* Wait until the controller is available */
1028 	start = get_timer(0);
1029 	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
1030 		if (get_timer(start) > 1000)
1031 			return -ETIMEDOUT;
1032 	}
1033 
1034 #if defined(CONFIG_FSL_USDHC)
1035 	/* RSTA doesn't reset MMC_BOOT register, so manually reset it */
1036 	esdhc_write32(&regs->mmcboot, 0x0);
1037 	/* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
1038 	esdhc_write32(&regs->mixctrl, 0x0);
1039 	esdhc_write32(&regs->clktunectrlstatus, 0x0);
1040 
1041 	/* Put VEND_SPEC to default value */
1042 	if (priv->vs18_enable)
1043 		esdhc_write32(&regs->vendorspec, (VENDORSPEC_INIT |
1044 			      ESDHC_VENDORSPEC_VSELECT));
1045 	else
1046 		esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
1047 
1048 	/* Disable DLL_CTRL delay line */
1049 	esdhc_write32(&regs->dllctrl, 0x0);
1050 #endif
1051 
1052 #ifndef ARCH_MXC
1053 	/* Enable cache snooping */
1054 	esdhc_write32(&regs->scr, 0x00000040);
1055 #endif
1056 
1057 #ifndef CONFIG_FSL_USDHC
1058 	esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
1059 #else
1060 	esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
1061 #endif
1062 
1063 	/* Set the initial clock speed */
1064 	mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
1065 
1066 	/* Disable the BRR and BWR bits in IRQSTAT */
1067 	esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
1068 
1069 #ifdef CONFIG_MCF5441x
1070 	esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
1071 #else
1072 	/* Put the PROCTL reg back to the default */
1073 	esdhc_write32(&regs->proctl, PROCTL_INIT);
1074 #endif
1075 
1076 	/* Set timout to the maximum value */
1077 	esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
1078 
1079 	return 0;
1080 }
1081 
esdhc_getcd_common(struct fsl_esdhc_priv * priv)1082 static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
1083 {
1084 	struct fsl_esdhc *regs = priv->esdhc_regs;
1085 	int timeout = 1000;
1086 
1087 #ifdef CONFIG_ESDHC_DETECT_QUIRK
1088 	if (CONFIG_ESDHC_DETECT_QUIRK)
1089 		return 1;
1090 #endif
1091 
1092 #if CONFIG_IS_ENABLED(DM_MMC)
1093 	if (priv->non_removable)
1094 		return 1;
1095 #ifdef CONFIG_DM_GPIO
1096 	if (dm_gpio_is_valid(&priv->cd_gpio))
1097 		return dm_gpio_get_value(&priv->cd_gpio);
1098 #endif
1099 #endif
1100 
1101 	while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
1102 		udelay(1000);
1103 
1104 	return timeout > 0;
1105 }
1106 
esdhc_reset(struct fsl_esdhc * regs)1107 static int esdhc_reset(struct fsl_esdhc *regs)
1108 {
1109 	ulong start;
1110 
1111 	/* reset the controller */
1112 	esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
1113 
1114 	/* hardware clears the bit when it is done */
1115 	start = get_timer(0);
1116 	while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
1117 		if (get_timer(start) > 100) {
1118 			printf("MMC/SD: Reset never completed.\n");
1119 			return -ETIMEDOUT;
1120 		}
1121 	}
1122 
1123 	return 0;
1124 }
1125 
1126 #if !CONFIG_IS_ENABLED(DM_MMC)
esdhc_getcd(struct mmc * mmc)1127 static int esdhc_getcd(struct mmc *mmc)
1128 {
1129 	struct fsl_esdhc_priv *priv = mmc->priv;
1130 
1131 	return esdhc_getcd_common(priv);
1132 }
1133 
esdhc_init(struct mmc * mmc)1134 static int esdhc_init(struct mmc *mmc)
1135 {
1136 	struct fsl_esdhc_priv *priv = mmc->priv;
1137 
1138 	return esdhc_init_common(priv, mmc);
1139 }
1140 
esdhc_send_cmd(struct mmc * mmc,struct mmc_cmd * cmd,struct mmc_data * data)1141 static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
1142 			  struct mmc_data *data)
1143 {
1144 	struct fsl_esdhc_priv *priv = mmc->priv;
1145 
1146 	return esdhc_send_cmd_common(priv, mmc, cmd, data);
1147 }
1148 
esdhc_set_ios(struct mmc * mmc)1149 static int esdhc_set_ios(struct mmc *mmc)
1150 {
1151 	struct fsl_esdhc_priv *priv = mmc->priv;
1152 
1153 	return esdhc_set_ios_common(priv, mmc);
1154 }
1155 
1156 static const struct mmc_ops esdhc_ops = {
1157 	.getcd		= esdhc_getcd,
1158 	.init		= esdhc_init,
1159 	.send_cmd	= esdhc_send_cmd,
1160 	.set_ios	= esdhc_set_ios,
1161 };
1162 #endif
1163 
fsl_esdhc_init(struct fsl_esdhc_priv * priv,struct fsl_esdhc_plat * plat)1164 static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
1165 			  struct fsl_esdhc_plat *plat)
1166 {
1167 	struct mmc_config *cfg;
1168 	struct fsl_esdhc *regs;
1169 	u32 caps, voltage_caps;
1170 	int ret;
1171 
1172 	if (!priv)
1173 		return -EINVAL;
1174 
1175 	regs = priv->esdhc_regs;
1176 
1177 	/* First reset the eSDHC controller */
1178 	ret = esdhc_reset(regs);
1179 	if (ret)
1180 		return ret;
1181 
1182 #ifdef CONFIG_MCF5441x
1183 	/* ColdFire, using SDHC_DATA[3] for card detection */
1184 	esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
1185 #endif
1186 
1187 #ifndef CONFIG_FSL_USDHC
1188 	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
1189 				| SYSCTL_IPGEN | SYSCTL_CKEN);
1190 	/* Clearing tuning bits in case ROM has set it already */
1191 	esdhc_write32(&regs->mixctrl, 0);
1192 	esdhc_write32(&regs->autoc12err, 0);
1193 	esdhc_write32(&regs->clktunectrlstatus, 0);
1194 #else
1195 	esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
1196 			VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
1197 #endif
1198 
1199 	if (priv->vs18_enable)
1200 		esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
1201 
1202 	writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
1203 	cfg = &plat->cfg;
1204 #ifndef CONFIG_DM_MMC
1205 	memset(cfg, '\0', sizeof(*cfg));
1206 #endif
1207 
1208 	voltage_caps = 0;
1209 	caps = esdhc_read32(&regs->hostcapblt);
1210 
1211 #ifdef CONFIG_MCF5441x
1212 	/*
1213 	 * MCF5441x RM declares in more points that sdhc clock speed must
1214 	 * never exceed 25 Mhz. From this, the HS bit needs to be disabled
1215 	 * from host capabilities.
1216 	 */
1217 	caps &= ~ESDHC_HOSTCAPBLT_HSS;
1218 #endif
1219 
1220 #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
1221 	caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
1222 			ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
1223 #endif
1224 
1225 /* T4240 host controller capabilities register should have VS33 bit */
1226 #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
1227 	caps = caps | ESDHC_HOSTCAPBLT_VS33;
1228 #endif
1229 
1230 	if (caps & ESDHC_HOSTCAPBLT_VS18)
1231 		voltage_caps |= MMC_VDD_165_195;
1232 	if (caps & ESDHC_HOSTCAPBLT_VS30)
1233 		voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
1234 	if (caps & ESDHC_HOSTCAPBLT_VS33)
1235 		voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
1236 
1237 	cfg->name = "FSL_SDHC";
1238 #if !CONFIG_IS_ENABLED(DM_MMC)
1239 	cfg->ops = &esdhc_ops;
1240 #endif
1241 #ifdef CONFIG_SYS_SD_VOLTAGE
1242 	cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
1243 #else
1244 	cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
1245 #endif
1246 	if ((cfg->voltages & voltage_caps) == 0) {
1247 		printf("voltage not supported by controller\n");
1248 		return -1;
1249 	}
1250 
1251 	if (priv->bus_width == 8)
1252 		cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1253 	else if (priv->bus_width == 4)
1254 		cfg->host_caps = MMC_MODE_4BIT;
1255 
1256 	cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
1257 #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
1258 	cfg->host_caps |= MMC_MODE_DDR_52MHz;
1259 #endif
1260 
1261 	if (priv->bus_width > 0) {
1262 		if (priv->bus_width < 8)
1263 			cfg->host_caps &= ~MMC_MODE_8BIT;
1264 		if (priv->bus_width < 4)
1265 			cfg->host_caps &= ~MMC_MODE_4BIT;
1266 	}
1267 
1268 	if (caps & ESDHC_HOSTCAPBLT_HSS)
1269 		cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
1270 
1271 #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
1272 	if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
1273 		cfg->host_caps &= ~MMC_MODE_8BIT;
1274 #endif
1275 
1276 	cfg->host_caps |= priv->caps;
1277 
1278 	cfg->f_min = 400000;
1279 	cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
1280 
1281 	cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
1282 
1283 	writel(0, &regs->dllctrl);
1284 	if (priv->flags & ESDHC_FLAG_USDHC) {
1285 		if (priv->flags & ESDHC_FLAG_STD_TUNING) {
1286 			u32 val = readl(&regs->tuning_ctrl);
1287 
1288 			val |= ESDHC_STD_TUNING_EN;
1289 			val &= ~ESDHC_TUNING_START_TAP_MASK;
1290 			val |= priv->tuning_start_tap;
1291 			val &= ~ESDHC_TUNING_STEP_MASK;
1292 			val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
1293 			writel(val, &regs->tuning_ctrl);
1294 		}
1295 	}
1296 
1297 	return 0;
1298 }
1299 
1300 #if !CONFIG_IS_ENABLED(DM_MMC)
fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg * cfg,struct fsl_esdhc_priv * priv)1301 static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
1302 				 struct fsl_esdhc_priv *priv)
1303 {
1304 	if (!cfg || !priv)
1305 		return -EINVAL;
1306 
1307 	priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
1308 	priv->bus_width = cfg->max_bus_width;
1309 	priv->sdhc_clk = cfg->sdhc_clk;
1310 	priv->wp_enable  = cfg->wp_enable;
1311 	priv->vs18_enable  = cfg->vs18_enable;
1312 
1313 	return 0;
1314 };
1315 
fsl_esdhc_initialize(bd_t * bis,struct fsl_esdhc_cfg * cfg)1316 int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
1317 {
1318 	struct fsl_esdhc_plat *plat;
1319 	struct fsl_esdhc_priv *priv;
1320 	struct mmc *mmc;
1321 	int ret;
1322 
1323 	if (!cfg)
1324 		return -EINVAL;
1325 
1326 	priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
1327 	if (!priv)
1328 		return -ENOMEM;
1329 	plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
1330 	if (!plat) {
1331 		free(priv);
1332 		return -ENOMEM;
1333 	}
1334 
1335 	ret = fsl_esdhc_cfg_to_priv(cfg, priv);
1336 	if (ret) {
1337 		debug("%s xlate failure\n", __func__);
1338 		free(plat);
1339 		free(priv);
1340 		return ret;
1341 	}
1342 
1343 	ret = fsl_esdhc_init(priv, plat);
1344 	if (ret) {
1345 		debug("%s init failure\n", __func__);
1346 		free(plat);
1347 		free(priv);
1348 		return ret;
1349 	}
1350 
1351 	mmc = mmc_create(&plat->cfg, priv);
1352 	if (!mmc)
1353 		return -EIO;
1354 
1355 	priv->mmc = mmc;
1356 
1357 	return 0;
1358 }
1359 
fsl_esdhc_mmc_init(bd_t * bis)1360 int fsl_esdhc_mmc_init(bd_t *bis)
1361 {
1362 	struct fsl_esdhc_cfg *cfg;
1363 
1364 	cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
1365 	cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
1366 	cfg->sdhc_clk = gd->arch.sdhc_clk;
1367 	return fsl_esdhc_initialize(bis, cfg);
1368 }
1369 #endif
1370 
1371 #ifdef CONFIG_OF_LIBFDT
esdhc_status_fixup(void * blob,const char * compat)1372 __weak int esdhc_status_fixup(void *blob, const char *compat)
1373 {
1374 #ifdef CONFIG_FSL_ESDHC_PIN_MUX
1375 	if (!hwconfig("esdhc")) {
1376 		do_fixup_by_compat(blob, compat, "status", "disabled",
1377 				sizeof("disabled"), 1);
1378 		return 1;
1379 	}
1380 #endif
1381 	return 0;
1382 }
1383 
fdt_fixup_esdhc(void * blob,bd_t * bd)1384 void fdt_fixup_esdhc(void *blob, bd_t *bd)
1385 {
1386 	const char *compat = "fsl,esdhc";
1387 
1388 	if (esdhc_status_fixup(blob, compat))
1389 		return;
1390 
1391 #ifdef CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
1392 	do_fixup_by_compat_u32(blob, compat, "peripheral-frequency",
1393 			       gd->arch.sdhc_clk, 1);
1394 #else
1395 	do_fixup_by_compat_u32(blob, compat, "clock-frequency",
1396 			       gd->arch.sdhc_clk, 1);
1397 #endif
1398 }
1399 #endif
1400 
1401 #if CONFIG_IS_ENABLED(DM_MMC)
1402 #include <asm/arch/clock.h>
init_clk_usdhc(u32 index)1403 __weak void init_clk_usdhc(u32 index)
1404 {
1405 }
1406 
fsl_esdhc_probe(struct udevice * dev)1407 static int fsl_esdhc_probe(struct udevice *dev)
1408 {
1409 	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
1410 	struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1411 	struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1412 	const void *fdt = gd->fdt_blob;
1413 	int node = dev_of_offset(dev);
1414 	struct esdhc_soc_data *data =
1415 		(struct esdhc_soc_data *)dev_get_driver_data(dev);
1416 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1417 	struct udevice *vqmmc_dev;
1418 #endif
1419 	fdt_addr_t addr;
1420 	unsigned int val;
1421 	struct mmc *mmc;
1422 #if !CONFIG_IS_ENABLED(BLK)
1423 	struct blk_desc *bdesc;
1424 #endif
1425 	int ret;
1426 
1427 	addr = dev_read_addr(dev);
1428 	if (addr == FDT_ADDR_T_NONE)
1429 		return -EINVAL;
1430 	priv->esdhc_regs = (struct fsl_esdhc *)addr;
1431 	priv->dev = dev;
1432 	priv->mode = -1;
1433 	if (data)
1434 		priv->flags = data->flags;
1435 
1436 	val = dev_read_u32_default(dev, "bus-width", -1);
1437 	if (val == 8)
1438 		priv->bus_width = 8;
1439 	else if (val == 4)
1440 		priv->bus_width = 4;
1441 	else
1442 		priv->bus_width = 1;
1443 
1444 	val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
1445 	priv->tuning_step = val;
1446 	val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
1447 			     ESDHC_TUNING_START_TAP_DEFAULT);
1448 	priv->tuning_start_tap = val;
1449 	val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
1450 			     ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
1451 	priv->strobe_dll_delay_target = val;
1452 
1453 	if (dev_read_bool(dev, "non-removable")) {
1454 		priv->non_removable = 1;
1455 	 } else {
1456 		priv->non_removable = 0;
1457 #ifdef CONFIG_DM_GPIO
1458 		gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
1459 				     GPIOD_IS_IN);
1460 #endif
1461 	}
1462 
1463 	if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
1464 		priv->wp_enable = 1;
1465 	} else {
1466 		priv->wp_enable = 0;
1467 #ifdef CONFIG_DM_GPIO
1468 		gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
1469 				   GPIOD_IS_IN);
1470 #endif
1471 	}
1472 
1473 	priv->vs18_enable = 0;
1474 
1475 #if CONFIG_IS_ENABLED(DM_REGULATOR)
1476 	/*
1477 	 * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
1478 	 * otherwise, emmc will work abnormally.
1479 	 */
1480 	ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
1481 	if (ret) {
1482 		dev_dbg(dev, "no vqmmc-supply\n");
1483 	} else {
1484 		ret = regulator_set_enable(vqmmc_dev, true);
1485 		if (ret) {
1486 			dev_err(dev, "fail to enable vqmmc-supply\n");
1487 			return ret;
1488 		}
1489 
1490 		if (regulator_get_value(vqmmc_dev) == 1800000)
1491 			priv->vs18_enable = 1;
1492 	}
1493 #endif
1494 
1495 	/*
1496 	 * TODO:
1497 	 * Because lack of clk driver, if SDHC clk is not enabled,
1498 	 * need to enable it first before this driver is invoked.
1499 	 *
1500 	 * we use MXC_ESDHC_CLK to get clk freq.
1501 	 * If one would like to make this function work,
1502 	 * the aliases should be provided in dts as this:
1503 	 *
1504 	 *  aliases {
1505 	 *	mmc0 = &usdhc1;
1506 	 *	mmc1 = &usdhc2;
1507 	 *	mmc2 = &usdhc3;
1508 	 *	mmc3 = &usdhc4;
1509 	 *	};
1510 	 * Then if your board only supports mmc2 and mmc3, but we can
1511 	 * correctly get the seq as 2 and 3, then let mxc_get_clock
1512 	 * work as expected.
1513 	 */
1514 
1515 	init_clk_usdhc(dev->seq);
1516 
1517 	if (CONFIG_IS_ENABLED(CLK)) {
1518 		/* Assigned clock already set clock */
1519 		ret = clk_get_by_name(dev, "per", &priv->per_clk);
1520 		if (ret) {
1521 			printf("Failed to get per_clk\n");
1522 			return ret;
1523 		}
1524 		ret = clk_enable(&priv->per_clk);
1525 		if (ret) {
1526 			printf("Failed to enable per_clk\n");
1527 			return ret;
1528 		}
1529 
1530 		priv->sdhc_clk = clk_get_rate(&priv->per_clk);
1531 	} else {
1532 		priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
1533 		if (priv->sdhc_clk <= 0) {
1534 			dev_err(dev, "Unable to get clk for %s\n", dev->name);
1535 			return -EINVAL;
1536 		}
1537 	}
1538 
1539 	ret = fsl_esdhc_init(priv, plat);
1540 	if (ret) {
1541 		dev_err(dev, "fsl_esdhc_init failure\n");
1542 		return ret;
1543 	}
1544 
1545 	ret = mmc_of_parse(dev, &plat->cfg);
1546 	if (ret)
1547 		return ret;
1548 
1549 	mmc = &plat->mmc;
1550 	mmc->cfg = &plat->cfg;
1551 	mmc->dev = dev;
1552 #if !CONFIG_IS_ENABLED(BLK)
1553 	mmc->priv = priv;
1554 
1555 	/* Setup dsr related values */
1556 	mmc->dsr_imp = 0;
1557 	mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
1558 	/* Setup the universal parts of the block interface just once */
1559 	bdesc = mmc_get_blk_desc(mmc);
1560 	bdesc->if_type = IF_TYPE_MMC;
1561 	bdesc->removable = 1;
1562 	bdesc->devnum = mmc_get_next_devnum();
1563 	bdesc->block_read = mmc_bread;
1564 	bdesc->block_write = mmc_bwrite;
1565 	bdesc->block_erase = mmc_berase;
1566 
1567 	/* setup initial part type */
1568 	bdesc->part_type = mmc->cfg->part_type;
1569 	mmc_list_add(mmc);
1570 #endif
1571 
1572 	upriv->mmc = mmc;
1573 
1574 	return esdhc_init_common(priv, mmc);
1575 }
1576 
1577 #if CONFIG_IS_ENABLED(DM_MMC)
fsl_esdhc_get_cd(struct udevice * dev)1578 static int fsl_esdhc_get_cd(struct udevice *dev)
1579 {
1580 	struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1581 
1582 	return esdhc_getcd_common(priv);
1583 }
1584 
fsl_esdhc_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)1585 static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
1586 			      struct mmc_data *data)
1587 {
1588 	struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1589 	struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1590 
1591 	return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
1592 }
1593 
fsl_esdhc_set_ios(struct udevice * dev)1594 static int fsl_esdhc_set_ios(struct udevice *dev)
1595 {
1596 	struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1597 	struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1598 
1599 	return esdhc_set_ios_common(priv, &plat->mmc);
1600 }
1601 
1602 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
fsl_esdhc_set_enhanced_strobe(struct udevice * dev)1603 static int fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
1604 {
1605 	struct fsl_esdhc_priv *priv = dev_get_priv(dev);
1606 	struct fsl_esdhc *regs = priv->esdhc_regs;
1607 	u32 m;
1608 
1609 	m = readl(&regs->mixctrl);
1610 	m |= MIX_CTRL_HS400_ES;
1611 	writel(m, &regs->mixctrl);
1612 
1613 	return 0;
1614 }
1615 #endif
1616 
1617 static const struct dm_mmc_ops fsl_esdhc_ops = {
1618 	.get_cd		= fsl_esdhc_get_cd,
1619 	.send_cmd	= fsl_esdhc_send_cmd,
1620 	.set_ios	= fsl_esdhc_set_ios,
1621 #ifdef MMC_SUPPORTS_TUNING
1622 	.execute_tuning	= fsl_esdhc_execute_tuning,
1623 #endif
1624 #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
1625 	.set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
1626 #endif
1627 };
1628 #endif
1629 
1630 static struct esdhc_soc_data usdhc_imx7d_data = {
1631 	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
1632 			| ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
1633 			| ESDHC_FLAG_HS400,
1634 };
1635 
1636 static struct esdhc_soc_data usdhc_imx8qm_data = {
1637 	.flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
1638 		ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
1639 		ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
1640 };
1641 
1642 static const struct udevice_id fsl_esdhc_ids[] = {
1643 	{ .compatible = "fsl,imx53-esdhc", },
1644 	{ .compatible = "fsl,imx6ul-usdhc", },
1645 	{ .compatible = "fsl,imx6sx-usdhc", },
1646 	{ .compatible = "fsl,imx6sl-usdhc", },
1647 	{ .compatible = "fsl,imx6q-usdhc", },
1648 	{ .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
1649 	{ .compatible = "fsl,imx7ulp-usdhc", },
1650 	{ .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1651 	{ .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1652 	{ .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1653 	{ .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
1654 	{ .compatible = "fsl,esdhc", },
1655 	{ /* sentinel */ }
1656 };
1657 
1658 #if CONFIG_IS_ENABLED(BLK)
fsl_esdhc_bind(struct udevice * dev)1659 static int fsl_esdhc_bind(struct udevice *dev)
1660 {
1661 	struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
1662 
1663 	return mmc_bind(dev, &plat->mmc, &plat->cfg);
1664 }
1665 #endif
1666 
1667 U_BOOT_DRIVER(fsl_esdhc) = {
1668 	.name	= "fsl-esdhc-mmc",
1669 	.id	= UCLASS_MMC,
1670 	.of_match = fsl_esdhc_ids,
1671 	.ops	= &fsl_esdhc_ops,
1672 #if CONFIG_IS_ENABLED(BLK)
1673 	.bind	= fsl_esdhc_bind,
1674 #endif
1675 	.probe	= fsl_esdhc_probe,
1676 	.platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
1677 	.priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
1678 };
1679 #endif
1680