| /third_party/uboot/u-boot-2020.01/arch/arm/mach-sunxi/ |
| D | dram_sun4i.c | 60 struct sunxi_dram_reg *dram = in mctl_ddr3_reset() local
73 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
75 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
79 clrbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
81 setbits_le32(&dram->mcr, DRAM_MCR_RESET); in mctl_ddr3_reset()
100 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; in mctl_set_drive() local
103 clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3) | (0x3 << 28), in mctl_set_drive()
105 clrsetbits_le32(&dram->mcr, DRAM_MCR_MODE_NORM(0x3), in mctl_set_drive()
113 struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; in mctl_itm_disable() local
115 clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF); in mctl_itm_disable()
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| D | Kconfig | 12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
48 Select this dram controller driver for some sun50i platforms,
405 int "sunxi dram type"
409 Set the dram type, 3: DDR3, 7: LPDDR3
412 int "sunxi dram clock speed"
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| /third_party/uboot/u-boot-2020.01/drivers/ram/rockchip/ |
| D | sdram_px30.c | 132 static void rkclk_ddr_reset(struct dram_info *dram, in rkclk_ddr_reset() argument
138 &dram->cru->softrst_con[1]); in rkclk_ddr_reset()
140 &dram->cru->softrst_con[2]); in rkclk_ddr_reset()
143 static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz) in rkclk_set_dpll() argument
171 writel(DPLL_MODE(CLOCK_FROM_XIN_OSC), &dram->cru->mode); in rkclk_set_dpll()
173 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->pll[1].con0); in rkclk_set_dpll()
175 &dram->cru->pll[1].con1); in rkclk_set_dpll()
179 if (LOCK(readl(&dram->cru->pll[1].con1))) in rkclk_set_dpll()
184 writel(DPLL_MODE(CLOCK_FROM_PLL), &dram->cru->mode); in rkclk_set_dpll()
187 static void rkclk_configure_ddr(struct dram_info *dram, in rkclk_configure_ddr() argument
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| D | sdram_rk3328.c | 64 static void rkclk_ddr_reset(struct dram_info *dram, in rkclk_ddr_reset() argument
70 &dram->cru->softrst_con[5]); in rkclk_ddr_reset()
71 writel(ddrctrl_asrstn_req(ctl_srstn), &dram->cru->softrst_con[9]); in rkclk_ddr_reset()
74 static void rkclk_set_dpll(struct dram_info *dram, unsigned int hz) in rkclk_set_dpll() argument
102 writel(((0x1 << 4) << 16) | (0 << 4), &dram->cru->mode_con); in rkclk_set_dpll()
103 writel(POSTDIV1(postdiv1) | FBDIV(fbdiv), &dram->cru->dpll_con[0]); in rkclk_set_dpll()
105 &dram->cru->dpll_con[1]); in rkclk_set_dpll()
109 if (LOCK(readl(&dram->cru->dpll_con[1]))) in rkclk_set_dpll()
114 writel(((0x1 << 4) << 16) | (1 << 4), &dram->cru->mode_con); in rkclk_set_dpll()
117 static void rkclk_configure_ddr(struct dram_info *dram, in rkclk_configure_ddr() argument
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| D | sdram_rk322x.c | 362 static void phy_softreset(struct dram_info *dram) in phy_softreset() argument
364 struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy; in phy_softreset()
365 struct rk322x_grf *grf = dram->grf; in phy_softreset()
377 static void set_bw(struct dram_info *dram, u32 bw) in set_bw() argument
379 struct rk322x_ddr_pctl *pctl = dram->chan[0].pctl; in set_bw()
380 struct rk322x_ddr_phy *ddr_phy = dram->chan[0].phy; in set_bw()
381 struct rk322x_grf *grf = dram->grf; in set_bw()
576 static void dram_all_config(const struct dram_info *dram, in dram_all_config() argument
594 writel(sys_reg, &dram->grf->os_reg[2]); in dram_all_config()
599 static int dram_cap_detect(struct dram_info *dram, in dram_cap_detect() argument
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| D | sdram_rk3399.c | 82 int (*data_training_first)(struct dram_info *dram, u32 channel, u8 rank,
84 int (*set_rate_index)(struct dram_info *dram,
226 static void *get_ddrc0_con(struct dram_info *dram, u8 channel) in get_ddrc0_con() argument
228 return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc1_con0; in get_ddrc0_con()
786 static void pctl_start(struct dram_info *dram, in pctl_start() argument
790 const struct chan_info *chan_0 = &dram->chan[0]; in pctl_start()
791 const struct chan_info *chan_1 = &dram->chan[1]; in pctl_start()
795 u32 *ddrc0_con_0 = get_ddrc0_con(dram, 0); in pctl_start()
798 u32 *ddrc1_con_0 = get_ddrc0_con(dram, 1); in pctl_start()
838 dram->pwrup_srefresh_exit[0]); in pctl_start()
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| D | sdram_rk3188.c | 532 static void dram_all_config(const struct dram_info *dram, in dram_all_config() argument
554 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); in dram_all_config()
557 ddr_rank_2_row15en(dram->grf, 0); in dram_all_config()
559 ddr_rank_2_row15en(dram->grf, 1); in dram_all_config()
561 writel(sys_reg, &dram->pmu->sys_reg[2]); in dram_all_config()
564 static int sdram_rank_bw_detect(struct dram_info *dram, int channel, in sdram_rank_bw_detect() argument
569 const struct chan_info *chan = &dram->chan[channel]; in sdram_rank_bw_detect()
572 ddr_rank_2_row15en(dram->grf, 0); in sdram_rank_bw_detect()
595 dram->grf); in sdram_rank_bw_detect()
605 ddr_phy_ctl_reset(dram->cru, channel, 1); in sdram_rank_bw_detect()
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| D | sdram_rk3288.c | 590 static void dram_all_config(const struct dram_info *dram, in dram_all_config() argument
612 dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); in dram_all_config()
614 writel(sys_reg, &dram->pmu->sys_reg[2]); in dram_all_config()
615 rk_clrsetreg(&dram->sgrf->soc_con2, 0x1f, sdram_params->base.stride); in dram_all_config()
618 static int sdram_rank_bw_detect(struct dram_info *dram, int channel, in sdram_rank_bw_detect() argument
623 const struct chan_info *chan = &dram->chan[channel]; in sdram_rank_bw_detect()
649 dram->grf); in sdram_rank_bw_detect()
659 ddr_phy_ctl_reset(dram->cru, channel, 1); in sdram_rank_bw_detect()
661 ddr_phy_ctl_reset(dram->cru, channel, 0); in sdram_rank_bw_detect()
671 static int sdram_col_row_detect(struct dram_info *dram, int channel, in sdram_col_row_detect() argument
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/arm926ejs/lpc32xx/ |
| D | dram.c | 24 void ddr_init(struct emc_dram_settings *dram) in ddr_init() argument
36 writel(dram->cmddelay, &clk->sdramclk_ctrl); in ddr_init()
37 writel(dram->config0, &emc->config0); in ddr_init()
38 writel(dram->rascas0, &emc->rascas0); in ddr_init()
39 writel(dram->rdconfig, &emc->read_config); in ddr_init()
41 writel((ck / dram->trp) & 0x0000000F, &emc->t_rp); in ddr_init()
42 writel((ck / dram->tras) & 0x0000000F, &emc->t_ras); in ddr_init()
43 writel((ck / dram->tsrex) & 0x0000007F, &emc->t_srex); in ddr_init()
44 writel((ck / dram->twr) & 0x0000000F, &emc->t_wr); in ddr_init()
45 writel((ck / dram->trc) & 0x0000001F, &emc->t_rc); in ddr_init()
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| D | Makefile | 8 obj-$(CONFIG_SPL_BUILD) += dram.o lowlevel_init.o
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| /third_party/uboot/u-boot-2020.01/arch/arm/mach-uniphier/clk/ |
| D | Makefile | 5 obj-$(CONFIG_ARCH_UNIPHIER_LD4) += clk-early-ld4.o clk-dram-ld4.o dpll-ld4.o
6 obj-$(CONFIG_ARCH_UNIPHIER_PRO4) += clk-early-ld4.o clk-dram-ld4.o dpll-pro4.o
7 obj-$(CONFIG_ARCH_UNIPHIER_SLD8) += clk-early-ld4.o clk-dram-ld4.o dpll-sld8.o
8 obj-$(CONFIG_ARCH_UNIPHIER_PRO5) += clk-early-ld4.o clk-dram-pro5.o dpll-pro5.o
9 obj-$(CONFIG_ARCH_UNIPHIER_PXS2) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
10 obj-$(CONFIG_ARCH_UNIPHIER_LD6B) += clk-early-ld4.o clk-dram-pxs2.o dpll-pxs2.o
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| /third_party/uboot/u-boot-2020.01/arch/x86/dts/ |
| D | galileo.dts | 51 dram-width = <DRAM_WIDTH_X8>;
52 dram-speed = <DRAM_FREQ_800>;
53 dram-type = <DRAM_TYPE_DDR3>;
63 dram-density = <DRAM_DENSITY_1G>;
64 dram-cl = <6>;
65 dram-ras = <0x0000927c>;
66 dram-wtr = <0x00002710>;
67 dram-rrd = <0x00002710>;
68 dram-faw = <0x00009c40>;
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| /third_party/uboot/u-boot-2020.01/arch/arm/mach-mvebu/ |
| D | cpu.c | 543 const struct mbus_dram_target_info *dram; in ahci_mvebu_mbus_config() local
550 dram = mvebu_mbus_dram_info(); in ahci_mvebu_mbus_config()
558 for (i = 0; i < dram->num_cs; i++) { in ahci_mvebu_mbus_config()
559 const struct mbus_dram_window *cs = dram->cs + i; in ahci_mvebu_mbus_config()
562 (dram->mbus_dram_target_id << 4) | 1, in ahci_mvebu_mbus_config()
604 const struct mbus_dram_target_info *dram) in xhci_mvebu_mbus_config() argument
613 for (i = 0; i < dram->num_cs; i++) { in xhci_mvebu_mbus_config()
614 const struct mbus_dram_window *cs = dram->cs + i; in xhci_mvebu_mbus_config()
618 (dram->mbus_dram_target_id << 4) | 1, in xhci_mvebu_mbus_config()
628 const struct mbus_dram_target_info *dram; in board_xhci_enable() local
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| D | Makefile | 15 obj-y = dram.o
23 obj-y += dram.o
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| /third_party/uboot/u-boot-2020.01/drivers/ata/ |
| D | mvsata_ide.c | 107 const struct mbus_dram_target_info *dram; in mvsata_ide_conf_mbus_windows() local
110 dram = mvebu_mbus_dram_info(); in mvsata_ide_conf_mbus_windows()
118 for (i = 0; i < dram->num_cs; i++) { in mvsata_ide_conf_mbus_windows()
119 const struct mbus_dram_window *cs = dram->cs + i; in mvsata_ide_conf_mbus_windows()
121 (dram->mbus_dram_target_id << 4) | 1, in mvsata_ide_conf_mbus_windows()
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| /third_party/uboot/u-boot-2020.01/drivers/mmc/ |
| D | mv_sdhci.c | 19 const struct mbus_dram_target_info *dram; in sdhci_mvebu_mbus_config() local
22 dram = mvebu_mbus_dram_info(); in sdhci_mvebu_mbus_config()
29 for (i = 0; i < dram->num_cs; i++) { in sdhci_mvebu_mbus_config()
30 const struct mbus_dram_window *cs = dram->cs + i; in sdhci_mvebu_mbus_config()
34 (dram->mbus_dram_target_id << 4) | 1, in sdhci_mvebu_mbus_config()
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| /third_party/uboot/u-boot-2020.01/drivers/usb/host/ |
| D | ehci-marvell.c | 55 const struct mbus_dram_target_info *dram; in usb_brg_adrdec_setup() local
58 dram = mvebu_mbus_dram_info(); in usb_brg_adrdec_setup()
65 for (i = 0; i < dram->num_cs; i++) { in usb_brg_adrdec_setup()
66 const struct mbus_dram_window *cs = dram->cs + i; in usb_brg_adrdec_setup()
70 (dram->mbus_dram_target_id << 4) | 1, in usb_brg_adrdec_setup()
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/imx/imx8m/ |
| D | Kconfig | 5 bool "imx8m dram"
26 hex "Define the base address for saved dram timing"
28 after DRAM is trained, need to save the dram related timming
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| /third_party/uboot/u-boot-2020.01/drivers/video/ |
| D | mvebu_lcd.c | 100 const struct mbus_dram_target_info *dram; in mvebu_lcd_conf_mbus_registers() local
103 dram = mvebu_mbus_dram_info(); in mvebu_lcd_conf_mbus_registers()
113 for (i = 0; i < dram->num_cs; i++) { in mvebu_lcd_conf_mbus_registers()
114 const struct mbus_dram_window *cs = dram->cs + i; in mvebu_lcd_conf_mbus_registers()
116 (dram->mbus_dram_target_id << 4) | 1, in mvebu_lcd_conf_mbus_registers()
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| /third_party/skia/third_party/externals/icu/source/data/unit/ |
| D | ig.txt | 35 dram{
36 dnam{"mmiri dram"}
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| /third_party/uboot/u-boot-2020.01/doc/device-tree-bindings/misc/ |
| D | intel,baytrail-fsp.txt | 75 - fsp,dram-speed
76 - fsp,dram-type
137 fsp,dram-speed = <DRAM_SPEED_1066MTS>;
138 fsp,dram-type = <DRAM_TYPE_DDR3L>;
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| /third_party/uboot/u-boot-2020.01/drivers/pci/ |
| D | pci_mvebu.c | 227 const struct mbus_dram_target_info *dram = mvebu_mbus_dram_info(); in mvebu_pcie_setup_wins() local
250 for (i = 0; i < dram->num_cs; i++) { in mvebu_pcie_setup_wins()
251 const struct mbus_dram_window *cs = dram->cs + i; in mvebu_pcie_setup_wins()
258 (dram->mbus_dram_target_id << 4) | 1, in mvebu_pcie_setup_wins()
269 writel(dram->cs[0].base | 0xc, pcie->base + PCIE_BAR_LO_OFF(1)); in mvebu_pcie_setup_wins()
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| /third_party/uboot/u-boot-2020.01/arch/mips/mach-bmips/ |
| D | Makefile | 3 obj-y += dram.o
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| /third_party/uboot/u-boot-2020.01/arch/riscv/cpu/generic/ |
| D | Makefile | 5 obj-y += dram.o
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/arm926ejs/armada100/ |
| D | Makefile | 7 obj-y = cpu.o timer.o dram.o
|