1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
2 /*
3 * (C) Copyright 2016-2017 Rockchip Inc.
4 *
5 * Adapted from coreboot.
6 */
7
8 #include <common.h>
9 #include <clk.h>
10 #include <dm.h>
11 #include <dt-structs.h>
12 #include <ram.h>
13 #include <regmap.h>
14 #include <syscon.h>
15 #include <asm/io.h>
16 #include <asm/arch-rockchip/clock.h>
17 #include <asm/arch-rockchip/cru_rk3399.h>
18 #include <asm/arch-rockchip/grf_rk3399.h>
19 #include <asm/arch-rockchip/pmu_rk3399.h>
20 #include <asm/arch-rockchip/hardware.h>
21 #include <asm/arch-rockchip/sdram.h>
22 #include <asm/arch-rockchip/sdram_rk3399.h>
23 #include <linux/err.h>
24 #include <time.h>
25
26 #define PRESET_SGRF_HOLD(n) ((0x1 << (6 + 16)) | ((n) << 6))
27 #define PRESET_GPIO0_HOLD(n) ((0x1 << (7 + 16)) | ((n) << 7))
28 #define PRESET_GPIO1_HOLD(n) ((0x1 << (8 + 16)) | ((n) << 8))
29
30 #define PHY_DRV_ODT_HI_Z 0x0
31 #define PHY_DRV_ODT_240 0x1
32 #define PHY_DRV_ODT_120 0x8
33 #define PHY_DRV_ODT_80 0x9
34 #define PHY_DRV_ODT_60 0xc
35 #define PHY_DRV_ODT_48 0xd
36 #define PHY_DRV_ODT_40 0xe
37 #define PHY_DRV_ODT_34_3 0xf
38
39 #define PHY_BOOSTP_EN 0x1
40 #define PHY_BOOSTN_EN 0x1
41 #define PHY_SLEWP_EN 0x1
42 #define PHY_SLEWN_EN 0x1
43 #define PHY_RX_CM_INPUT 0x1
44 #define CS0_MR22_VAL 0
45 #define CS1_MR22_VAL 3
46
47 /* LPDDR3 DRAM DS */
48 #define LPDDR3_DS_34 0x1
49 #define LPDDR3_DS_40 0x2
50 #define LPDDR3_DS_48 0x3
51
52 #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \
53 ((n) << (8 + (ch) * 4)))
54 #define CRU_SFTRST_DDR_PHY(ch, n) ((0x1 << (9 + 16 + (ch) * 4)) | \
55 ((n) << (9 + (ch) * 4)))
56 struct chan_info {
57 struct rk3399_ddr_pctl_regs *pctl;
58 struct rk3399_ddr_pi_regs *pi;
59 struct rk3399_ddr_publ_regs *publ;
60 struct msch_regs *msch;
61 };
62
63 struct dram_info {
64 #if defined(CONFIG_TPL_BUILD) || \
65 (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
66 u32 pwrup_srefresh_exit[2];
67 struct chan_info chan[2];
68 struct clk ddr_clk;
69 struct rk3399_cru *cru;
70 struct rk3399_grf_regs *grf;
71 struct rk3399_pmu_regs *pmu;
72 struct rk3399_pmucru *pmucru;
73 struct rk3399_pmusgrf_regs *pmusgrf;
74 struct rk3399_ddr_cic_regs *cic;
75 const struct sdram_rk3399_ops *ops;
76 #endif
77 struct ram_info info;
78 struct rk3399_pmugrf_regs *pmugrf;
79 };
80
81 struct sdram_rk3399_ops {
82 int (*data_training_first)(struct dram_info *dram, u32 channel, u8 rank,
83 struct rk3399_sdram_params *sdram);
84 int (*set_rate_index)(struct dram_info *dram,
85 struct rk3399_sdram_params *params);
86 void (*modify_param)(const struct chan_info *chan,
87 struct rk3399_sdram_params *params);
88 struct rk3399_sdram_params *
89 (*get_phy_index_params)(u32 phy_fn,
90 struct rk3399_sdram_params *params);
91 };
92
93 #if defined(CONFIG_TPL_BUILD) || \
94 (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
95
96 struct rockchip_dmc_plat {
97 #if CONFIG_IS_ENABLED(OF_PLATDATA)
98 struct dtd_rockchip_rk3399_dmc dtplat;
99 #else
100 struct rk3399_sdram_params sdram_params;
101 #endif
102 struct regmap *map;
103 };
104
105 struct io_setting {
106 u32 mhz;
107 u32 mr5;
108 /* dram side */
109 u32 dq_odt;
110 u32 ca_odt;
111 u32 pdds;
112 u32 dq_vref;
113 u32 ca_vref;
114 /* phy side */
115 u32 rd_odt;
116 u32 wr_dq_drv;
117 u32 wr_ca_drv;
118 u32 wr_ckcs_drv;
119 u32 rd_odt_en;
120 u32 rd_vref;
121 } lpddr4_io_setting[] = {
122 {
123 50 * MHz,
124 0,
125 /* dram side */
126 0, /* dq_odt; */
127 0, /* ca_odt; */
128 6, /* pdds; */
129 0x72, /* dq_vref; */
130 0x72, /* ca_vref; */
131 /* phy side */
132 PHY_DRV_ODT_HI_Z, /* rd_odt; */
133 PHY_DRV_ODT_40, /* wr_dq_drv; */
134 PHY_DRV_ODT_40, /* wr_ca_drv; */
135 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
136 0, /* rd_odt_en;*/
137 41, /* rd_vref; (unit %, range 3.3% - 48.7%) */
138 },
139 {
140 600 * MHz,
141 0,
142 /* dram side */
143 1, /* dq_odt; */
144 0, /* ca_odt; */
145 6, /* pdds; */
146 0x72, /* dq_vref; */
147 0x72, /* ca_vref; */
148 /* phy side */
149 PHY_DRV_ODT_HI_Z, /* rd_odt; */
150 PHY_DRV_ODT_48, /* wr_dq_drv; */
151 PHY_DRV_ODT_40, /* wr_ca_drv; */
152 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
153 0, /* rd_odt_en; */
154 32, /* rd_vref; (unit %, range 3.3% - 48.7%) */
155 },
156 {
157 933 * MHz,
158 0,
159 /* dram side */
160 1, /* dq_odt; */
161 0, /* ca_odt; */
162 3, /* pdds; */
163 0x72, /* dq_vref; */
164 0x72, /* ca_vref; */
165 /* phy side */
166 PHY_DRV_ODT_80, /* rd_odt; */
167 PHY_DRV_ODT_40, /* wr_dq_drv; */
168 PHY_DRV_ODT_40, /* wr_ca_drv; */
169 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
170 1, /* rd_odt_en; */
171 20, /* rd_vref; (unit %, range 3.3% - 48.7%) */
172 },
173 {
174 1066 * MHz,
175 0,
176 /* dram side */
177 6, /* dq_odt; */
178 0, /* ca_odt; */
179 3, /* pdds; */
180 0x10, /* dq_vref; */
181 0x72, /* ca_vref; */
182 /* phy side */
183 PHY_DRV_ODT_80, /* rd_odt; */
184 PHY_DRV_ODT_60, /* wr_dq_drv; */
185 PHY_DRV_ODT_40, /* wr_ca_drv; */
186 PHY_DRV_ODT_40, /* wr_ckcs_drv; */
187 1, /* rd_odt_en; */
188 20, /* rd_vref; (unit %, range 3.3% - 48.7%) */
189 },
190 };
191
192 static struct io_setting *
lpddr4_get_io_settings(const struct rk3399_sdram_params * params,u32 mr5)193 lpddr4_get_io_settings(const struct rk3399_sdram_params *params, u32 mr5)
194 {
195 struct io_setting *io = NULL;
196 u32 n;
197
198 for (n = 0; n < ARRAY_SIZE(lpddr4_io_setting); n++) {
199 io = &lpddr4_io_setting[n];
200
201 if (io->mr5 != 0) {
202 if (io->mhz >= params->base.ddr_freq &&
203 io->mr5 == mr5)
204 break;
205 } else {
206 if (io->mhz >= params->base.ddr_freq)
207 break;
208 }
209 }
210
211 return io;
212 }
213
get_denali_ctl(const struct chan_info * chan,struct rk3399_sdram_params * params,bool reg)214 static void *get_denali_ctl(const struct chan_info *chan,
215 struct rk3399_sdram_params *params, bool reg)
216 {
217 return reg ? &chan->pctl->denali_ctl : ¶ms->pctl_regs.denali_ctl;
218 }
219
get_denali_phy(const struct chan_info * chan,struct rk3399_sdram_params * params,bool reg)220 static void *get_denali_phy(const struct chan_info *chan,
221 struct rk3399_sdram_params *params, bool reg)
222 {
223 return reg ? &chan->publ->denali_phy : ¶ms->phy_regs.denali_phy;
224 }
225
get_ddrc0_con(struct dram_info * dram,u8 channel)226 static void *get_ddrc0_con(struct dram_info *dram, u8 channel)
227 {
228 return (channel == 0) ? &dram->grf->ddrc0_con0 : &dram->grf->ddrc1_con0;
229 }
230
rkclk_ddr_reset(struct rk3399_cru * cru,u32 channel,u32 ctl,u32 phy)231 static void rkclk_ddr_reset(struct rk3399_cru *cru, u32 channel, u32 ctl,
232 u32 phy)
233 {
234 channel &= 0x1;
235 ctl &= 0x1;
236 phy &= 0x1;
237 writel(CRU_SFTRST_DDR_CTRL(channel, ctl) |
238 CRU_SFTRST_DDR_PHY(channel, phy),
239 &cru->softrst_con[4]);
240 }
241
phy_pctrl_reset(struct rk3399_cru * cru,u32 channel)242 static void phy_pctrl_reset(struct rk3399_cru *cru, u32 channel)
243 {
244 rkclk_ddr_reset(cru, channel, 1, 1);
245 udelay(10);
246
247 rkclk_ddr_reset(cru, channel, 1, 0);
248 udelay(10);
249
250 rkclk_ddr_reset(cru, channel, 0, 0);
251 udelay(10);
252 }
253
phy_dll_bypass_set(struct rk3399_ddr_publ_regs * ddr_publ_regs,u32 freq)254 static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
255 u32 freq)
256 {
257 u32 *denali_phy = ddr_publ_regs->denali_phy;
258
259 /* From IP spec, only freq small than 125 can enter dll bypass mode */
260 if (freq <= 125) {
261 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
262 setbits_le32(&denali_phy[86], (0x3 << 2) << 8);
263 setbits_le32(&denali_phy[214], (0x3 << 2) << 8);
264 setbits_le32(&denali_phy[342], (0x3 << 2) << 8);
265 setbits_le32(&denali_phy[470], (0x3 << 2) << 8);
266
267 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
268 setbits_le32(&denali_phy[547], (0x3 << 2) << 16);
269 setbits_le32(&denali_phy[675], (0x3 << 2) << 16);
270 setbits_le32(&denali_phy[803], (0x3 << 2) << 16);
271 } else {
272 /* phy_sw_master_mode_X PHY_86/214/342/470 4bits offset_8 */
273 clrbits_le32(&denali_phy[86], (0x3 << 2) << 8);
274 clrbits_le32(&denali_phy[214], (0x3 << 2) << 8);
275 clrbits_le32(&denali_phy[342], (0x3 << 2) << 8);
276 clrbits_le32(&denali_phy[470], (0x3 << 2) << 8);
277
278 /* phy_adrctl_sw_master_mode PHY_547/675/803 4bits offset_16 */
279 clrbits_le32(&denali_phy[547], (0x3 << 2) << 16);
280 clrbits_le32(&denali_phy[675], (0x3 << 2) << 16);
281 clrbits_le32(&denali_phy[803], (0x3 << 2) << 16);
282 }
283 }
284
set_memory_map(const struct chan_info * chan,u32 channel,const struct rk3399_sdram_params * params)285 static void set_memory_map(const struct chan_info *chan, u32 channel,
286 const struct rk3399_sdram_params *params)
287 {
288 const struct rk3399_sdram_channel *sdram_ch = ¶ms->ch[channel];
289 u32 *denali_ctl = chan->pctl->denali_ctl;
290 u32 *denali_pi = chan->pi->denali_pi;
291 u32 cs_map;
292 u32 reduc;
293 u32 row;
294
295 /* Get row number from ddrconfig setting */
296 if (sdram_ch->cap_info.ddrconfig < 2 ||
297 sdram_ch->cap_info.ddrconfig == 4)
298 row = 16;
299 else if (sdram_ch->cap_info.ddrconfig == 3 ||
300 sdram_ch->cap_info.ddrconfig == 5)
301 row = 14;
302 else
303 row = 15;
304
305 cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1;
306 reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1;
307
308 /* Set the dram configuration to ctrl */
309 clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col));
310 clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
311 ((3 - sdram_ch->cap_info.bk) << 16) |
312 ((16 - row) << 24));
313
314 clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
315 cs_map | (reduc << 16));
316
317 /* PI_199 PI_COL_DIFF:RW:0:4 */
318 clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col));
319
320 /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
321 clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
322 ((3 - sdram_ch->cap_info.bk) << 16) |
323 ((16 - row) << 24));
324
325 if (params->base.dramtype == LPDDR4) {
326 if (cs_map == 1)
327 cs_map = 0x5;
328 else if (cs_map == 2)
329 cs_map = 0xa;
330 else
331 cs_map = 0xF;
332 }
333
334 /* PI_41 PI_CS_MAP:RW:24:4 */
335 clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
336 if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3)
337 writel(0x2EC7FFFF, &denali_pi[34]);
338 }
339
phy_io_config(const struct chan_info * chan,const struct rk3399_sdram_params * params,u32 mr5)340 static int phy_io_config(const struct chan_info *chan,
341 const struct rk3399_sdram_params *params, u32 mr5)
342 {
343 u32 *denali_phy = chan->publ->denali_phy;
344 u32 *denali_ctl = chan->pctl->denali_ctl;
345 u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;
346 u32 mode_sel;
347 u32 speed;
348 u32 reg_value;
349 u32 ds_value, odt_value;
350
351 /* vref setting & mode setting */
352 if (params->base.dramtype == LPDDR4) {
353 struct io_setting *io = lpddr4_get_io_settings(params, mr5);
354 u32 rd_vref = io->rd_vref * 1000;
355
356 if (rd_vref < 36700) {
357 /* MODE_LV[2:0] = LPDDR4 (Range 2)*/
358 vref_mode_dq = 0x7;
359 /* MODE[2:0]= LPDDR4 Range 2(0.4*VDDQ) */
360 mode_sel = 0x5;
361 vref_value_dq = (rd_vref - 3300) / 521;
362 } else {
363 /* MODE_LV[2:0] = LPDDR4 (Range 1)*/
364 vref_mode_dq = 0x6;
365 /* MODE[2:0]= LPDDR4 Range 1(0.33*VDDQ) */
366 mode_sel = 0x4;
367 vref_value_dq = (rd_vref - 15300) / 521;
368 }
369 vref_mode_ac = 0x6;
370 /* VDDQ/3/2=16.8% */
371 vref_value_ac = 0x3;
372 } else if (params->base.dramtype == LPDDR3) {
373 if (params->base.odt == 1) {
374 vref_mode_dq = 0x5; /* LPDDR3 ODT */
375 ds_value = readl(&denali_ctl[138]) & 0xf;
376 odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;
377 if (ds_value == LPDDR3_DS_48) {
378 switch (odt_value) {
379 case PHY_DRV_ODT_240:
380 vref_value_dq = 0x1B;
381 break;
382 case PHY_DRV_ODT_120:
383 vref_value_dq = 0x26;
384 break;
385 case PHY_DRV_ODT_60:
386 vref_value_dq = 0x36;
387 break;
388 default:
389 debug("Invalid ODT value.\n");
390 return -EINVAL;
391 }
392 } else if (ds_value == LPDDR3_DS_40) {
393 switch (odt_value) {
394 case PHY_DRV_ODT_240:
395 vref_value_dq = 0x19;
396 break;
397 case PHY_DRV_ODT_120:
398 vref_value_dq = 0x23;
399 break;
400 case PHY_DRV_ODT_60:
401 vref_value_dq = 0x31;
402 break;
403 default:
404 debug("Invalid ODT value.\n");
405 return -EINVAL;
406 }
407 } else if (ds_value == LPDDR3_DS_34) {
408 switch (odt_value) {
409 case PHY_DRV_ODT_240:
410 vref_value_dq = 0x17;
411 break;
412 case PHY_DRV_ODT_120:
413 vref_value_dq = 0x20;
414 break;
415 case PHY_DRV_ODT_60:
416 vref_value_dq = 0x2e;
417 break;
418 default:
419 debug("Invalid ODT value.\n");
420 return -EINVAL;
421 }
422 } else {
423 debug("Invalid DRV value.\n");
424 return -EINVAL;
425 }
426 } else {
427 vref_mode_dq = 0x2; /* LPDDR3 */
428 vref_value_dq = 0x1f;
429 }
430 vref_mode_ac = 0x2;
431 vref_value_ac = 0x1f;
432 mode_sel = 0x0;
433 } else if (params->base.dramtype == DDR3) {
434 /* DDR3L */
435 vref_mode_dq = 0x1;
436 vref_value_dq = 0x1f;
437 vref_mode_ac = 0x1;
438 vref_value_ac = 0x1f;
439 mode_sel = 0x1;
440 } else {
441 debug("Unknown DRAM type.\n");
442 return -EINVAL;
443 }
444
445 reg_value = (vref_mode_dq << 9) | (0x1 << 8) | vref_value_dq;
446
447 /* PHY_913 PHY_PAD_VREF_CTRL_DQ_0 12bits offset_8 */
448 clrsetbits_le32(&denali_phy[913], 0xfff << 8, reg_value << 8);
449 /* PHY_914 PHY_PAD_VREF_CTRL_DQ_1 12bits offset_0 */
450 clrsetbits_le32(&denali_phy[914], 0xfff, reg_value);
451 /* PHY_914 PHY_PAD_VREF_CTRL_DQ_2 12bits offset_16 */
452 clrsetbits_le32(&denali_phy[914], 0xfff << 16, reg_value << 16);
453 /* PHY_915 PHY_PAD_VREF_CTRL_DQ_3 12bits offset_0 */
454 clrsetbits_le32(&denali_phy[915], 0xfff, reg_value);
455
456 reg_value = (vref_mode_ac << 9) | (0x1 << 8) | vref_value_ac;
457
458 /* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
459 clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
460
461 /* PHY_924 PHY_PAD_FDBK_DRIVE */
462 clrsetbits_le32(&denali_phy[924], 0x7 << 15, mode_sel << 15);
463 /* PHY_926 PHY_PAD_DATA_DRIVE */
464 clrsetbits_le32(&denali_phy[926], 0x7 << 6, mode_sel << 6);
465 /* PHY_927 PHY_PAD_DQS_DRIVE */
466 clrsetbits_le32(&denali_phy[927], 0x7 << 6, mode_sel << 6);
467 /* PHY_928 PHY_PAD_ADDR_DRIVE */
468 clrsetbits_le32(&denali_phy[928], 0x7 << 14, mode_sel << 14);
469 /* PHY_929 PHY_PAD_CLK_DRIVE */
470 clrsetbits_le32(&denali_phy[929], 0x7 << 14, mode_sel << 14);
471 /* PHY_935 PHY_PAD_CKE_DRIVE */
472 clrsetbits_le32(&denali_phy[935], 0x7 << 14, mode_sel << 14);
473 /* PHY_937 PHY_PAD_RST_DRIVE */
474 clrsetbits_le32(&denali_phy[937], 0x7 << 14, mode_sel << 14);
475 /* PHY_939 PHY_PAD_CS_DRIVE */
476 clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
477
478 if (params->base.dramtype == LPDDR4) {
479 /* BOOSTP_EN & BOOSTN_EN */
480 reg_value = ((PHY_BOOSTP_EN << 4) | PHY_BOOSTN_EN);
481 /* PHY_925 PHY_PAD_FDBK_DRIVE2 */
482 clrsetbits_le32(&denali_phy[925], 0xff << 8, reg_value << 8);
483 /* PHY_926 PHY_PAD_DATA_DRIVE */
484 clrsetbits_le32(&denali_phy[926], 0xff << 12, reg_value << 12);
485 /* PHY_927 PHY_PAD_DQS_DRIVE */
486 clrsetbits_le32(&denali_phy[927], 0xff << 14, reg_value << 14);
487 /* PHY_928 PHY_PAD_ADDR_DRIVE */
488 clrsetbits_le32(&denali_phy[928], 0xff << 20, reg_value << 20);
489 /* PHY_929 PHY_PAD_CLK_DRIVE */
490 clrsetbits_le32(&denali_phy[929], 0xff << 22, reg_value << 22);
491 /* PHY_935 PHY_PAD_CKE_DRIVE */
492 clrsetbits_le32(&denali_phy[935], 0xff << 20, reg_value << 20);
493 /* PHY_937 PHY_PAD_RST_DRIVE */
494 clrsetbits_le32(&denali_phy[937], 0xff << 20, reg_value << 20);
495 /* PHY_939 PHY_PAD_CS_DRIVE */
496 clrsetbits_le32(&denali_phy[939], 0xff << 20, reg_value << 20);
497
498 /* SLEWP_EN & SLEWN_EN */
499 reg_value = ((PHY_SLEWP_EN << 3) | PHY_SLEWN_EN);
500 /* PHY_924 PHY_PAD_FDBK_DRIVE */
501 clrsetbits_le32(&denali_phy[924], 0x3f << 8, reg_value << 8);
502 /* PHY_926 PHY_PAD_DATA_DRIVE */
503 clrsetbits_le32(&denali_phy[926], 0x3f, reg_value);
504 /* PHY_927 PHY_PAD_DQS_DRIVE */
505 clrsetbits_le32(&denali_phy[927], 0x3f, reg_value);
506 /* PHY_928 PHY_PAD_ADDR_DRIVE */
507 clrsetbits_le32(&denali_phy[928], 0x3f << 8, reg_value << 8);
508 /* PHY_929 PHY_PAD_CLK_DRIVE */
509 clrsetbits_le32(&denali_phy[929], 0x3f << 8, reg_value << 8);
510 /* PHY_935 PHY_PAD_CKE_DRIVE */
511 clrsetbits_le32(&denali_phy[935], 0x3f << 8, reg_value << 8);
512 /* PHY_937 PHY_PAD_RST_DRIVE */
513 clrsetbits_le32(&denali_phy[937], 0x3f << 8, reg_value << 8);
514 /* PHY_939 PHY_PAD_CS_DRIVE */
515 clrsetbits_le32(&denali_phy[939], 0x3f << 8, reg_value << 8);
516 }
517
518 /* speed setting */
519 speed = 0x2;
520
521 /* PHY_924 PHY_PAD_FDBK_DRIVE */
522 clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
523 /* PHY_926 PHY_PAD_DATA_DRIVE */
524 clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
525 /* PHY_927 PHY_PAD_DQS_DRIVE */
526 clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
527 /* PHY_928 PHY_PAD_ADDR_DRIVE */
528 clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
529 /* PHY_929 PHY_PAD_CLK_DRIVE */
530 clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
531 /* PHY_935 PHY_PAD_CKE_DRIVE */
532 clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
533 /* PHY_937 PHY_PAD_RST_DRIVE */
534 clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
535 /* PHY_939 PHY_PAD_CS_DRIVE */
536 clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
537
538 if (params->base.dramtype == LPDDR4) {
539 /* RX_CM_INPUT */
540 reg_value = PHY_RX_CM_INPUT;
541 /* PHY_924 PHY_PAD_FDBK_DRIVE */
542 clrsetbits_le32(&denali_phy[924], 0x1 << 14, reg_value << 14);
543 /* PHY_926 PHY_PAD_DATA_DRIVE */
544 clrsetbits_le32(&denali_phy[926], 0x1 << 11, reg_value << 11);
545 /* PHY_927 PHY_PAD_DQS_DRIVE */
546 clrsetbits_le32(&denali_phy[927], 0x1 << 13, reg_value << 13);
547 /* PHY_928 PHY_PAD_ADDR_DRIVE */
548 clrsetbits_le32(&denali_phy[928], 0x1 << 19, reg_value << 19);
549 /* PHY_929 PHY_PAD_CLK_DRIVE */
550 clrsetbits_le32(&denali_phy[929], 0x1 << 21, reg_value << 21);
551 /* PHY_935 PHY_PAD_CKE_DRIVE */
552 clrsetbits_le32(&denali_phy[935], 0x1 << 19, reg_value << 19);
553 /* PHY_937 PHY_PAD_RST_DRIVE */
554 clrsetbits_le32(&denali_phy[937], 0x1 << 19, reg_value << 19);
555 /* PHY_939 PHY_PAD_CS_DRIVE */
556 clrsetbits_le32(&denali_phy[939], 0x1 << 19, reg_value << 19);
557 }
558
559 return 0;
560 }
561
set_ds_odt(const struct chan_info * chan,struct rk3399_sdram_params * params,bool ctl_phy_reg,u32 mr5)562 static void set_ds_odt(const struct chan_info *chan,
563 struct rk3399_sdram_params *params,
564 bool ctl_phy_reg, u32 mr5)
565 {
566 u32 *denali_phy = get_denali_phy(chan, params, ctl_phy_reg);
567 u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
568 u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
569 u32 tsel_idle_select_p, tsel_rd_select_p;
570 u32 tsel_idle_select_n, tsel_rd_select_n;
571 u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
572 u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
573 u32 tsel_ckcs_select_p, tsel_ckcs_select_n;
574 struct io_setting *io = NULL;
575 u32 soc_odt = 0;
576 u32 reg_value;
577
578 if (params->base.dramtype == LPDDR4) {
579 io = lpddr4_get_io_settings(params, mr5);
580
581 tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
582 tsel_rd_select_n = io->rd_odt;
583
584 tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
585 tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
586
587 tsel_wr_select_dq_p = io->wr_dq_drv;
588 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
589
590 tsel_wr_select_ca_p = io->wr_ca_drv;
591 tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
592
593 tsel_ckcs_select_p = io->wr_ckcs_drv;
594 tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
595
596 switch (tsel_rd_select_n) {
597 case PHY_DRV_ODT_240:
598 soc_odt = 1;
599 break;
600 case PHY_DRV_ODT_120:
601 soc_odt = 2;
602 break;
603 case PHY_DRV_ODT_80:
604 soc_odt = 3;
605 break;
606 case PHY_DRV_ODT_60:
607 soc_odt = 4;
608 break;
609 case PHY_DRV_ODT_48:
610 soc_odt = 5;
611 break;
612 case PHY_DRV_ODT_40:
613 soc_odt = 6;
614 break;
615 case PHY_DRV_ODT_34_3:
616 soc_odt = 6;
617 printf("%s: Unable to support LPDDR4 MR22 Soc ODT\n",
618 __func__);
619 break;
620 case PHY_DRV_ODT_HI_Z:
621 default:
622 soc_odt = 0;
623 break;
624 }
625 } else if (params->base.dramtype == LPDDR3) {
626 tsel_rd_select_p = PHY_DRV_ODT_240;
627 tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
628
629 tsel_idle_select_p = PHY_DRV_ODT_240;
630 tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
631
632 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
633 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
634
635 tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
636 tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
637
638 tsel_ckcs_select_p = PHY_DRV_ODT_34_3;
639 tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
640 } else {
641 tsel_rd_select_p = PHY_DRV_ODT_240;
642 tsel_rd_select_n = PHY_DRV_ODT_240;
643
644 tsel_idle_select_p = PHY_DRV_ODT_240;
645 tsel_idle_select_n = PHY_DRV_ODT_240;
646
647 tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
648 tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
649
650 tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
651 tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
652
653 tsel_ckcs_select_p = PHY_DRV_ODT_34_3;
654 tsel_ckcs_select_n = PHY_DRV_ODT_34_3;
655 }
656
657 if (params->base.odt == 1) {
658 tsel_rd_en = 1;
659
660 if (params->base.dramtype == LPDDR4)
661 tsel_rd_en = io->rd_odt_en;
662 } else {
663 tsel_rd_en = 0;
664 }
665
666 tsel_wr_en = 0;
667 tsel_idle_en = 0;
668
669 /* F0_0 */
670 clrsetbits_le32(&denali_ctl[145], 0xFF << 16,
671 (soc_odt | (CS0_MR22_VAL << 3)) << 16);
672 /* F2_0, F1_0 */
673 clrsetbits_le32(&denali_ctl[146], 0xFF00FF,
674 ((soc_odt | (CS0_MR22_VAL << 3)) << 16) |
675 (soc_odt | (CS0_MR22_VAL << 3)));
676 /* F0_1 */
677 clrsetbits_le32(&denali_ctl[159], 0xFF << 16,
678 (soc_odt | (CS1_MR22_VAL << 3)) << 16);
679 /* F2_1, F1_1 */
680 clrsetbits_le32(&denali_ctl[160], 0xFF00FF,
681 ((soc_odt | (CS1_MR22_VAL << 3)) << 16) |
682 (soc_odt | (CS1_MR22_VAL << 3)));
683
684 /*
685 * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0
686 * sets termination values for read/idle cycles and drive strength
687 * for write cycles for DQ/DM
688 */
689 reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
690 (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) |
691 (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
692 clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
693 clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);
694 clrsetbits_le32(&denali_phy[262], 0xffffff, reg_value);
695 clrsetbits_le32(&denali_phy[390], 0xffffff, reg_value);
696
697 /*
698 * phy_dqs_tsel_select_X 24bits DENALI_PHY_7/135/263/391 offset_0
699 * sets termination values for read/idle cycles and drive strength
700 * for write cycles for DQS
701 */
702 clrsetbits_le32(&denali_phy[7], 0xffffff, reg_value);
703 clrsetbits_le32(&denali_phy[135], 0xffffff, reg_value);
704 clrsetbits_le32(&denali_phy[263], 0xffffff, reg_value);
705 clrsetbits_le32(&denali_phy[391], 0xffffff, reg_value);
706
707 /* phy_adr_tsel_select_ 8bits DENALI_PHY_544/672/800 offset_0 */
708 reg_value = tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 0x4);
709 if (params->base.dramtype == LPDDR4) {
710 /* LPDDR4 these register read always return 0, so
711 * can not use clrsetbits_le32(), need to write32
712 */
713 writel((0x300 << 8) | reg_value, &denali_phy[544]);
714 writel((0x300 << 8) | reg_value, &denali_phy[672]);
715 writel((0x300 << 8) | reg_value, &denali_phy[800]);
716 } else {
717 clrsetbits_le32(&denali_phy[544], 0xff, reg_value);
718 clrsetbits_le32(&denali_phy[672], 0xff, reg_value);
719 clrsetbits_le32(&denali_phy[800], 0xff, reg_value);
720 }
721
722 /* phy_pad_addr_drive 8bits DENALI_PHY_928 offset_0 */
723 clrsetbits_le32(&denali_phy[928], 0xff, reg_value);
724
725 /* phy_pad_rst_drive 8bits DENALI_PHY_937 offset_0 */
726 if (!ctl_phy_reg)
727 clrsetbits_le32(&denali_phy[937], 0xff, reg_value);
728
729 /* phy_pad_cke_drive 8bits DENALI_PHY_935 offset_0 */
730 clrsetbits_le32(&denali_phy[935], 0xff, reg_value);
731
732 /* phy_pad_cs_drive 8bits DENALI_PHY_939 offset_0 */
733 clrsetbits_le32(&denali_phy[939], 0xff,
734 tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4));
735
736 /* phy_pad_clk_drive 8bits DENALI_PHY_929 offset_0 */
737 clrsetbits_le32(&denali_phy[929], 0xff,
738 tsel_ckcs_select_n | (tsel_ckcs_select_p << 0x4));
739
740 /* phy_pad_fdbk_drive 23bit DENALI_PHY_924/925 */
741 clrsetbits_le32(&denali_phy[924], 0xff,
742 tsel_wr_select_ca_n | (tsel_wr_select_ca_p << 4));
743 clrsetbits_le32(&denali_phy[925], 0xff,
744 tsel_wr_select_dq_n | (tsel_wr_select_dq_p << 4));
745
746 /* phy_dq_tsel_enable_X 3bits DENALI_PHY_5/133/261/389 offset_16 */
747 reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
748 << 16;
749 clrsetbits_le32(&denali_phy[5], 0x7 << 16, reg_value);
750 clrsetbits_le32(&denali_phy[133], 0x7 << 16, reg_value);
751 clrsetbits_le32(&denali_phy[261], 0x7 << 16, reg_value);
752 clrsetbits_le32(&denali_phy[389], 0x7 << 16, reg_value);
753
754 /* phy_dqs_tsel_enable_X 3bits DENALI_PHY_6/134/262/390 offset_24 */
755 reg_value = (tsel_rd_en | (tsel_wr_en << 1) | (tsel_idle_en << 2))
756 << 24;
757 clrsetbits_le32(&denali_phy[6], 0x7 << 24, reg_value);
758 clrsetbits_le32(&denali_phy[134], 0x7 << 24, reg_value);
759 clrsetbits_le32(&denali_phy[262], 0x7 << 24, reg_value);
760 clrsetbits_le32(&denali_phy[390], 0x7 << 24, reg_value);
761
762 /* phy_adr_tsel_enable_ 1bit DENALI_PHY_518/646/774 offset_8 */
763 reg_value = tsel_wr_en << 8;
764 clrsetbits_le32(&denali_phy[518], 0x1 << 8, reg_value);
765 clrsetbits_le32(&denali_phy[646], 0x1 << 8, reg_value);
766 clrsetbits_le32(&denali_phy[774], 0x1 << 8, reg_value);
767
768 /* phy_pad_addr_term tsel 1bit DENALI_PHY_933 offset_17 */
769 reg_value = tsel_wr_en << 17;
770 clrsetbits_le32(&denali_phy[933], 0x1 << 17, reg_value);
771 /*
772 * pad_rst/cke/cs/clk_term tsel 1bits
773 * DENALI_PHY_938/936/940/934 offset_17
774 */
775 clrsetbits_le32(&denali_phy[938], 0x1 << 17, reg_value);
776 clrsetbits_le32(&denali_phy[936], 0x1 << 17, reg_value);
777 clrsetbits_le32(&denali_phy[940], 0x1 << 17, reg_value);
778 clrsetbits_le32(&denali_phy[934], 0x1 << 17, reg_value);
779
780 /* phy_pad_fdbk_term 1bit DENALI_PHY_930 offset_17 */
781 clrsetbits_le32(&denali_phy[930], 0x1 << 17, reg_value);
782
783 phy_io_config(chan, params, mr5);
784 }
785
pctl_start(struct dram_info * dram,struct rk3399_sdram_params * params,u32 channel_mask)786 static void pctl_start(struct dram_info *dram,
787 struct rk3399_sdram_params *params,
788 u32 channel_mask)
789 {
790 const struct chan_info *chan_0 = &dram->chan[0];
791 const struct chan_info *chan_1 = &dram->chan[1];
792
793 u32 *denali_ctl_0 = chan_0->pctl->denali_ctl;
794 u32 *denali_phy_0 = chan_0->publ->denali_phy;
795 u32 *ddrc0_con_0 = get_ddrc0_con(dram, 0);
796 u32 *denali_ctl_1 = chan_1->pctl->denali_ctl;
797 u32 *denali_phy_1 = chan_1->publ->denali_phy;
798 u32 *ddrc1_con_0 = get_ddrc0_con(dram, 1);
799 u32 count = 0;
800 u32 byte, tmp;
801
802 /* PHY_DLL_RST_EN */
803 if (channel_mask & 1) {
804 writel(0x01000000, &ddrc0_con_0);
805 clrsetbits_le32(&denali_phy_0[957], 0x3 << 24, 0x2 << 24);
806 }
807
808 if (channel_mask & 1) {
809 count = 0;
810 while (!(readl(&denali_ctl_0[203]) & (1 << 3))) {
811 if (count > 1000) {
812 printf("%s: Failed to init pctl channel 0\n",
813 __func__);
814 while (1)
815 ;
816 }
817 udelay(1);
818 count++;
819 }
820
821 writel(0x01000100, &ddrc0_con_0);
822 for (byte = 0; byte < 4; byte++) {
823 tmp = 0x820;
824 writel((tmp << 16) | tmp,
825 &denali_phy_0[53 + (128 * byte)]);
826 writel((tmp << 16) | tmp,
827 &denali_phy_0[54 + (128 * byte)]);
828 writel((tmp << 16) | tmp,
829 &denali_phy_0[55 + (128 * byte)]);
830 writel((tmp << 16) | tmp,
831 &denali_phy_0[56 + (128 * byte)]);
832 writel((tmp << 16) | tmp,
833 &denali_phy_0[57 + (128 * byte)]);
834 clrsetbits_le32(&denali_phy_0[58 + (128 * byte)],
835 0xffff, tmp);
836 }
837 clrsetbits_le32(&denali_ctl_0[68], PWRUP_SREFRESH_EXIT,
838 dram->pwrup_srefresh_exit[0]);
839 }
840
841 if (channel_mask & 2) {
842 writel(0x01000000, &ddrc1_con_0);
843 clrsetbits_le32(&denali_phy_1[957], 0x3 << 24, 0x2 << 24);
844 }
845 if (channel_mask & 2) {
846 count = 0;
847 while (!(readl(&denali_ctl_1[203]) & (1 << 3))) {
848 if (count > 1000) {
849 printf("%s: Failed to init pctl channel 1\n",
850 __func__);
851 while (1)
852 ;
853 }
854 udelay(1);
855 count++;
856 }
857
858 writel(0x01000100, &ddrc1_con_0);
859 for (byte = 0; byte < 4; byte++) {
860 tmp = 0x820;
861 writel((tmp << 16) | tmp,
862 &denali_phy_1[53 + (128 * byte)]);
863 writel((tmp << 16) | tmp,
864 &denali_phy_1[54 + (128 * byte)]);
865 writel((tmp << 16) | tmp,
866 &denali_phy_1[55 + (128 * byte)]);
867 writel((tmp << 16) | tmp,
868 &denali_phy_1[56 + (128 * byte)]);
869 writel((tmp << 16) | tmp,
870 &denali_phy_1[57 + (128 * byte)]);
871 clrsetbits_le32(&denali_phy_1[58 + (128 * byte)],
872 0xffff, tmp);
873 }
874
875 clrsetbits_le32(&denali_ctl_1[68], PWRUP_SREFRESH_EXIT,
876 dram->pwrup_srefresh_exit[1]);
877
878 /*
879 * restore channel 1 RESET original setting
880 * to avoid 240ohm too weak to prevent ESD test
881 */
882 if (params->base.dramtype == LPDDR4)
883 clrsetbits_le32(&denali_phy_1[937], 0xff,
884 params->phy_regs.denali_phy[937] &
885 0xFF);
886 }
887 }
888
pctl_cfg(struct dram_info * dram,const struct chan_info * chan,u32 channel,struct rk3399_sdram_params * params)889 static int pctl_cfg(struct dram_info *dram, const struct chan_info *chan,
890 u32 channel, struct rk3399_sdram_params *params)
891 {
892 u32 *denali_ctl = chan->pctl->denali_ctl;
893 u32 *denali_pi = chan->pi->denali_pi;
894 u32 *denali_phy = chan->publ->denali_phy;
895 const u32 *params_ctl = params->pctl_regs.denali_ctl;
896 const u32 *params_phy = params->phy_regs.denali_phy;
897 u32 tmp, tmp1, tmp2;
898 struct rk3399_sdram_params *params_cfg;
899 u32 byte;
900
901 dram->ops->modify_param(chan, params);
902 /*
903 * work around controller bug:
904 * Do not program DRAM_CLASS until NO_PHY_IND_TRAIN_INT is programmed
905 */
906 sdram_copy_to_reg(&denali_ctl[1], ¶ms_ctl[1],
907 sizeof(struct rk3399_ddr_pctl_regs) - 4);
908 writel(params_ctl[0], &denali_ctl[0]);
909
910 /*
911 * two channel init at the same time, then ZQ Cal Start
912 * at the same time, it will use the same RZQ, but cannot
913 * start at the same time.
914 *
915 * So, increase tINIT3 for channel 1, will avoid two
916 * channel ZQ Cal Start at the same time
917 */
918 if (params->base.dramtype == LPDDR4 && channel == 1) {
919 tmp = ((params->base.ddr_freq * MHz + 999) / 1000);
920 tmp1 = readl(&denali_ctl[14]);
921 writel(tmp + tmp1, &denali_ctl[14]);
922 }
923
924 sdram_copy_to_reg(denali_pi, ¶ms->pi_regs.denali_pi[0],
925 sizeof(struct rk3399_ddr_pi_regs));
926
927 /* rank count need to set for init */
928 set_memory_map(chan, channel, params);
929
930 writel(params->phy_regs.denali_phy[910], &denali_phy[910]);
931 writel(params->phy_regs.denali_phy[911], &denali_phy[911]);
932 writel(params->phy_regs.denali_phy[912], &denali_phy[912]);
933
934 if (params->base.dramtype == LPDDR4) {
935 writel(params->phy_regs.denali_phy[898], &denali_phy[898]);
936 writel(params->phy_regs.denali_phy[919], &denali_phy[919]);
937 }
938
939 dram->pwrup_srefresh_exit[channel] = readl(&denali_ctl[68]) &
940 PWRUP_SREFRESH_EXIT;
941 clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);
942
943 /* PHY_DLL_RST_EN */
944 clrsetbits_le32(&denali_phy[957], 0x3 << 24, 1 << 24);
945
946 setbits_le32(&denali_pi[0], START);
947 setbits_le32(&denali_ctl[0], START);
948
949 /**
950 * LPDDR4 use PLL bypass mode for init
951 * not need to wait for the PLL to lock
952 */
953 if (params->base.dramtype != LPDDR4) {
954 /* Waiting for phy DLL lock */
955 while (1) {
956 tmp = readl(&denali_phy[920]);
957 tmp1 = readl(&denali_phy[921]);
958 tmp2 = readl(&denali_phy[922]);
959 if ((((tmp >> 16) & 0x1) == 0x1) &&
960 (((tmp1 >> 16) & 0x1) == 0x1) &&
961 (((tmp1 >> 0) & 0x1) == 0x1) &&
962 (((tmp2 >> 0) & 0x1) == 0x1))
963 break;
964 }
965 }
966
967 sdram_copy_to_reg(&denali_phy[896], ¶ms_phy[896], (958 - 895) * 4);
968 sdram_copy_to_reg(&denali_phy[0], ¶ms_phy[0], (90 - 0 + 1) * 4);
969 sdram_copy_to_reg(&denali_phy[128], ¶ms_phy[128],
970 (218 - 128 + 1) * 4);
971 sdram_copy_to_reg(&denali_phy[256], ¶ms_phy[256],
972 (346 - 256 + 1) * 4);
973 sdram_copy_to_reg(&denali_phy[384], ¶ms_phy[384],
974 (474 - 384 + 1) * 4);
975 sdram_copy_to_reg(&denali_phy[512], ¶ms_phy[512],
976 (549 - 512 + 1) * 4);
977 sdram_copy_to_reg(&denali_phy[640], ¶ms_phy[640],
978 (677 - 640 + 1) * 4);
979 sdram_copy_to_reg(&denali_phy[768], ¶ms_phy[768],
980 (805 - 768 + 1) * 4);
981
982 if (params->base.dramtype == LPDDR4)
983 params_cfg = dram->ops->get_phy_index_params(1, params);
984 else
985 params_cfg = dram->ops->get_phy_index_params(0, params);
986
987 clrsetbits_le32(¶ms_cfg->phy_regs.denali_phy[896], 0x3 << 8,
988 0 << 8);
989 writel(params_cfg->phy_regs.denali_phy[896], &denali_phy[896]);
990
991 writel(params->phy_regs.denali_phy[83] + (0x10 << 16),
992 &denali_phy[83]);
993 writel(params->phy_regs.denali_phy[84] + (0x10 << 8),
994 &denali_phy[84]);
995 writel(params->phy_regs.denali_phy[211] + (0x10 << 16),
996 &denali_phy[211]);
997 writel(params->phy_regs.denali_phy[212] + (0x10 << 8),
998 &denali_phy[212]);
999 writel(params->phy_regs.denali_phy[339] + (0x10 << 16),
1000 &denali_phy[339]);
1001 writel(params->phy_regs.denali_phy[340] + (0x10 << 8),
1002 &denali_phy[340]);
1003 writel(params->phy_regs.denali_phy[467] + (0x10 << 16),
1004 &denali_phy[467]);
1005 writel(params->phy_regs.denali_phy[468] + (0x10 << 8),
1006 &denali_phy[468]);
1007
1008 if (params->base.dramtype == LPDDR4) {
1009 /*
1010 * to improve write dqs and dq phase from 1.5ns to 3.5ns
1011 * at 50MHz. this's the measure result from oscilloscope
1012 * of dqs and dq write signal.
1013 */
1014 for (byte = 0; byte < 4; byte++) {
1015 tmp = 0x680;
1016 clrsetbits_le32(&denali_phy[1 + (128 * byte)],
1017 0xfff << 8, tmp << 8);
1018 }
1019 /*
1020 * to workaround 366ball two channel's RESET connect to
1021 * one RESET signal of die
1022 */
1023 if (channel == 1)
1024 clrsetbits_le32(&denali_phy[937], 0xff,
1025 PHY_DRV_ODT_240 |
1026 (PHY_DRV_ODT_240 << 0x4));
1027 }
1028
1029 return 0;
1030 }
1031
select_per_cs_training_index(const struct chan_info * chan,u32 rank)1032 static void select_per_cs_training_index(const struct chan_info *chan,
1033 u32 rank)
1034 {
1035 u32 *denali_phy = chan->publ->denali_phy;
1036
1037 /* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
1038 if ((readl(&denali_phy[84]) >> 16) & 1) {
1039 /*
1040 * PHY_8/136/264/392
1041 * phy_per_cs_training_index_X 1bit offset_24
1042 */
1043 clrsetbits_le32(&denali_phy[8], 0x1 << 24, rank << 24);
1044 clrsetbits_le32(&denali_phy[136], 0x1 << 24, rank << 24);
1045 clrsetbits_le32(&denali_phy[264], 0x1 << 24, rank << 24);
1046 clrsetbits_le32(&denali_phy[392], 0x1 << 24, rank << 24);
1047 }
1048 }
1049
override_write_leveling_value(const struct chan_info * chan)1050 static void override_write_leveling_value(const struct chan_info *chan)
1051 {
1052 u32 *denali_ctl = chan->pctl->denali_ctl;
1053 u32 *denali_phy = chan->publ->denali_phy;
1054 u32 byte;
1055
1056 /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
1057 setbits_le32(&denali_phy[896], 1);
1058
1059 /*
1060 * PHY_8/136/264/392
1061 * phy_per_cs_training_multicast_en_X 1bit offset_16
1062 */
1063 clrsetbits_le32(&denali_phy[8], 0x1 << 16, 1 << 16);
1064 clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16);
1065 clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16);
1066 clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16);
1067
1068 for (byte = 0; byte < 4; byte++)
1069 clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16,
1070 0x200 << 16);
1071
1072 /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */
1073 clrbits_le32(&denali_phy[896], 1);
1074
1075 /* CTL_200 ctrlupd_req 1bit offset_8 */
1076 clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8);
1077 }
1078
data_training_ca(const struct chan_info * chan,u32 channel,const struct rk3399_sdram_params * params)1079 static int data_training_ca(const struct chan_info *chan, u32 channel,
1080 const struct rk3399_sdram_params *params)
1081 {
1082 u32 *denali_pi = chan->pi->denali_pi;
1083 u32 *denali_phy = chan->publ->denali_phy;
1084 u32 i, tmp;
1085 u32 obs_0, obs_1, obs_2, obs_err = 0;
1086 u32 rank = params->ch[channel].cap_info.rank;
1087 u32 rank_mask;
1088
1089 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1090 writel(0x00003f7c, (&denali_pi[175]));
1091
1092 if (params->base.dramtype == LPDDR4)
1093 rank_mask = (rank == 1) ? 0x5 : 0xf;
1094 else
1095 rank_mask = (rank == 1) ? 0x1 : 0x3;
1096
1097 for (i = 0; i < 4; i++) {
1098 if (!(rank_mask & (1 << i)))
1099 continue;
1100
1101 select_per_cs_training_index(chan, i);
1102
1103 /* PI_100 PI_CALVL_EN:RW:8:2 */
1104 clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8);
1105
1106 /* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
1107 clrsetbits_le32(&denali_pi[92],
1108 (0x1 << 16) | (0x3 << 24),
1109 (0x1 << 16) | (i << 24));
1110
1111 /* Waiting for training complete */
1112 while (1) {
1113 /* PI_174 PI_INT_STATUS:RD:8:18 */
1114 tmp = readl(&denali_pi[174]) >> 8;
1115 /*
1116 * check status obs
1117 * PHY_532/660/789 phy_adr_calvl_obs1_:0:32
1118 */
1119 obs_0 = readl(&denali_phy[532]);
1120 obs_1 = readl(&denali_phy[660]);
1121 obs_2 = readl(&denali_phy[788]);
1122 if (((obs_0 >> 30) & 0x3) ||
1123 ((obs_1 >> 30) & 0x3) ||
1124 ((obs_2 >> 30) & 0x3))
1125 obs_err = 1;
1126 if ((((tmp >> 11) & 0x1) == 0x1) &&
1127 (((tmp >> 13) & 0x1) == 0x1) &&
1128 (((tmp >> 5) & 0x1) == 0x0) &&
1129 obs_err == 0)
1130 break;
1131 else if ((((tmp >> 5) & 0x1) == 0x1) ||
1132 (obs_err == 1))
1133 return -EIO;
1134 }
1135
1136 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1137 writel(0x00003f7c, (&denali_pi[175]));
1138 }
1139
1140 clrbits_le32(&denali_pi[100], 0x3 << 8);
1141
1142 return 0;
1143 }
1144
data_training_wl(const struct chan_info * chan,u32 channel,const struct rk3399_sdram_params * params)1145 static int data_training_wl(const struct chan_info *chan, u32 channel,
1146 const struct rk3399_sdram_params *params)
1147 {
1148 u32 *denali_pi = chan->pi->denali_pi;
1149 u32 *denali_phy = chan->publ->denali_phy;
1150 u32 i, tmp;
1151 u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
1152 u32 rank = params->ch[channel].cap_info.rank;
1153
1154 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1155 writel(0x00003f7c, (&denali_pi[175]));
1156
1157 for (i = 0; i < rank; i++) {
1158 select_per_cs_training_index(chan, i);
1159
1160 /* PI_60 PI_WRLVL_EN:RW:8:2 */
1161 clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
1162
1163 /* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
1164 clrsetbits_le32(&denali_pi[59],
1165 (0x1 << 8) | (0x3 << 16),
1166 (0x1 << 8) | (i << 16));
1167
1168 /* Waiting for training complete */
1169 while (1) {
1170 /* PI_174 PI_INT_STATUS:RD:8:18 */
1171 tmp = readl(&denali_pi[174]) >> 8;
1172
1173 /*
1174 * check status obs, if error maybe can not
1175 * get leveling done PHY_40/168/296/424
1176 * phy_wrlvl_status_obs_X:0:13
1177 */
1178 obs_0 = readl(&denali_phy[40]);
1179 obs_1 = readl(&denali_phy[168]);
1180 obs_2 = readl(&denali_phy[296]);
1181 obs_3 = readl(&denali_phy[424]);
1182 if (((obs_0 >> 12) & 0x1) ||
1183 ((obs_1 >> 12) & 0x1) ||
1184 ((obs_2 >> 12) & 0x1) ||
1185 ((obs_3 >> 12) & 0x1))
1186 obs_err = 1;
1187 if ((((tmp >> 10) & 0x1) == 0x1) &&
1188 (((tmp >> 13) & 0x1) == 0x1) &&
1189 (((tmp >> 4) & 0x1) == 0x0) &&
1190 obs_err == 0)
1191 break;
1192 else if ((((tmp >> 4) & 0x1) == 0x1) ||
1193 (obs_err == 1))
1194 return -EIO;
1195 }
1196
1197 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1198 writel(0x00003f7c, (&denali_pi[175]));
1199 }
1200
1201 override_write_leveling_value(chan);
1202 clrbits_le32(&denali_pi[60], 0x3 << 8);
1203
1204 return 0;
1205 }
1206
data_training_rg(const struct chan_info * chan,u32 channel,const struct rk3399_sdram_params * params)1207 static int data_training_rg(const struct chan_info *chan, u32 channel,
1208 const struct rk3399_sdram_params *params)
1209 {
1210 u32 *denali_pi = chan->pi->denali_pi;
1211 u32 *denali_phy = chan->publ->denali_phy;
1212 u32 i, tmp;
1213 u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
1214 u32 rank = params->ch[channel].cap_info.rank;
1215
1216 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1217 writel(0x00003f7c, (&denali_pi[175]));
1218
1219 for (i = 0; i < rank; i++) {
1220 select_per_cs_training_index(chan, i);
1221
1222 /* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
1223 clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
1224
1225 /*
1226 * PI_74 PI_RDLVL_GATE_REQ:WR:16:1
1227 * PI_RDLVL_CS:RW:24:2
1228 */
1229 clrsetbits_le32(&denali_pi[74],
1230 (0x1 << 16) | (0x3 << 24),
1231 (0x1 << 16) | (i << 24));
1232
1233 /* Waiting for training complete */
1234 while (1) {
1235 /* PI_174 PI_INT_STATUS:RD:8:18 */
1236 tmp = readl(&denali_pi[174]) >> 8;
1237
1238 /*
1239 * check status obs
1240 * PHY_43/171/299/427
1241 * PHY_GTLVL_STATUS_OBS_x:16:8
1242 */
1243 obs_0 = readl(&denali_phy[43]);
1244 obs_1 = readl(&denali_phy[171]);
1245 obs_2 = readl(&denali_phy[299]);
1246 obs_3 = readl(&denali_phy[427]);
1247 if (((obs_0 >> (16 + 6)) & 0x3) ||
1248 ((obs_1 >> (16 + 6)) & 0x3) ||
1249 ((obs_2 >> (16 + 6)) & 0x3) ||
1250 ((obs_3 >> (16 + 6)) & 0x3))
1251 obs_err = 1;
1252 if ((((tmp >> 9) & 0x1) == 0x1) &&
1253 (((tmp >> 13) & 0x1) == 0x1) &&
1254 (((tmp >> 3) & 0x1) == 0x0) &&
1255 obs_err == 0)
1256 break;
1257 else if ((((tmp >> 3) & 0x1) == 0x1) ||
1258 (obs_err == 1))
1259 return -EIO;
1260 }
1261
1262 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1263 writel(0x00003f7c, (&denali_pi[175]));
1264 }
1265
1266 clrbits_le32(&denali_pi[80], 0x3 << 24);
1267
1268 return 0;
1269 }
1270
data_training_rl(const struct chan_info * chan,u32 channel,const struct rk3399_sdram_params * params)1271 static int data_training_rl(const struct chan_info *chan, u32 channel,
1272 const struct rk3399_sdram_params *params)
1273 {
1274 u32 *denali_pi = chan->pi->denali_pi;
1275 u32 i, tmp;
1276 u32 rank = params->ch[channel].cap_info.rank;
1277
1278 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1279 writel(0x00003f7c, (&denali_pi[175]));
1280
1281 for (i = 0; i < rank; i++) {
1282 select_per_cs_training_index(chan, i);
1283
1284 /* PI_80 PI_RDLVL_EN:RW:16:2 */
1285 clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
1286
1287 /* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
1288 clrsetbits_le32(&denali_pi[74],
1289 (0x1 << 8) | (0x3 << 24),
1290 (0x1 << 8) | (i << 24));
1291
1292 /* Waiting for training complete */
1293 while (1) {
1294 /* PI_174 PI_INT_STATUS:RD:8:18 */
1295 tmp = readl(&denali_pi[174]) >> 8;
1296
1297 /*
1298 * make sure status obs not report error bit
1299 * PHY_46/174/302/430
1300 * phy_rdlvl_status_obs_X:16:8
1301 */
1302 if ((((tmp >> 8) & 0x1) == 0x1) &&
1303 (((tmp >> 13) & 0x1) == 0x1) &&
1304 (((tmp >> 2) & 0x1) == 0x0))
1305 break;
1306 else if (((tmp >> 2) & 0x1) == 0x1)
1307 return -EIO;
1308 }
1309
1310 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1311 writel(0x00003f7c, (&denali_pi[175]));
1312 }
1313
1314 clrbits_le32(&denali_pi[80], 0x3 << 16);
1315
1316 return 0;
1317 }
1318
data_training_wdql(const struct chan_info * chan,u32 channel,const struct rk3399_sdram_params * params)1319 static int data_training_wdql(const struct chan_info *chan, u32 channel,
1320 const struct rk3399_sdram_params *params)
1321 {
1322 u32 *denali_pi = chan->pi->denali_pi;
1323 u32 i, tmp;
1324 u32 rank = params->ch[channel].cap_info.rank;
1325 u32 rank_mask;
1326
1327 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1328 writel(0x00003f7c, (&denali_pi[175]));
1329
1330 if (params->base.dramtype == LPDDR4)
1331 rank_mask = (rank == 1) ? 0x5 : 0xf;
1332 else
1333 rank_mask = (rank == 1) ? 0x1 : 0x3;
1334
1335 for (i = 0; i < 4; i++) {
1336 if (!(rank_mask & (1 << i)))
1337 continue;
1338
1339 select_per_cs_training_index(chan, i);
1340
1341 /*
1342 * disable PI_WDQLVL_VREF_EN before wdq leveling?
1343 * PI_117 PI_WDQLVL_VREF_EN:RW:8:1
1344 */
1345 clrbits_le32(&denali_pi[117], 0x1 << 8);
1346 /* PI_124 PI_WDQLVL_EN:RW:16:2 */
1347 clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16);
1348
1349 /* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
1350 clrsetbits_le32(&denali_pi[121],
1351 (0x1 << 8) | (0x3 << 16),
1352 (0x1 << 8) | (i << 16));
1353
1354 /* Waiting for training complete */
1355 while (1) {
1356 /* PI_174 PI_INT_STATUS:RD:8:18 */
1357 tmp = readl(&denali_pi[174]) >> 8;
1358 if ((((tmp >> 12) & 0x1) == 0x1) &&
1359 (((tmp >> 13) & 0x1) == 0x1) &&
1360 (((tmp >> 6) & 0x1) == 0x0))
1361 break;
1362 else if (((tmp >> 6) & 0x1) == 0x1)
1363 return -EIO;
1364 }
1365
1366 /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
1367 writel(0x00003f7c, (&denali_pi[175]));
1368 }
1369
1370 clrbits_le32(&denali_pi[124], 0x3 << 16);
1371
1372 return 0;
1373 }
1374
data_training(struct dram_info * dram,u32 channel,const struct rk3399_sdram_params * params,u32 training_flag)1375 static int data_training(struct dram_info *dram, u32 channel,
1376 const struct rk3399_sdram_params *params,
1377 u32 training_flag)
1378 {
1379 struct chan_info *chan = &dram->chan[channel];
1380 u32 *denali_phy = chan->publ->denali_phy;
1381 int ret;
1382
1383 /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
1384 setbits_le32(&denali_phy[927], (1 << 22));
1385
1386 if (training_flag == PI_FULL_TRAINING) {
1387 if (params->base.dramtype == LPDDR4) {
1388 training_flag = PI_WRITE_LEVELING |
1389 PI_READ_GATE_TRAINING |
1390 PI_READ_LEVELING | PI_WDQ_LEVELING;
1391 } else if (params->base.dramtype == LPDDR3) {
1392 training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
1393 PI_READ_GATE_TRAINING;
1394 } else if (params->base.dramtype == DDR3) {
1395 training_flag = PI_WRITE_LEVELING |
1396 PI_READ_GATE_TRAINING |
1397 PI_READ_LEVELING;
1398 }
1399 }
1400
1401 /* ca training(LPDDR4,LPDDR3 support) */
1402 if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING) {
1403 ret = data_training_ca(chan, channel, params);
1404 if (ret < 0) {
1405 debug("%s: data training ca failed\n", __func__);
1406 return ret;
1407 }
1408 }
1409
1410 /* write leveling(LPDDR4,LPDDR3,DDR3 support) */
1411 if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING) {
1412 ret = data_training_wl(chan, channel, params);
1413 if (ret < 0) {
1414 debug("%s: data training wl failed\n", __func__);
1415 return ret;
1416 }
1417 }
1418
1419 /* read gate training(LPDDR4,LPDDR3,DDR3 support) */
1420 if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING) {
1421 ret = data_training_rg(chan, channel, params);
1422 if (ret < 0) {
1423 debug("%s: data training rg failed\n", __func__);
1424 return ret;
1425 }
1426 }
1427
1428 /* read leveling(LPDDR4,LPDDR3,DDR3 support) */
1429 if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING) {
1430 ret = data_training_rl(chan, channel, params);
1431 if (ret < 0) {
1432 debug("%s: data training rl failed\n", __func__);
1433 return ret;
1434 }
1435 }
1436
1437 /* wdq leveling(LPDDR4 support) */
1438 if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING) {
1439 ret = data_training_wdql(chan, channel, params);
1440 if (ret < 0) {
1441 debug("%s: data training wdql failed\n", __func__);
1442 return ret;
1443 }
1444 }
1445
1446 /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */
1447 clrbits_le32(&denali_phy[927], (1 << 22));
1448
1449 return 0;
1450 }
1451
set_ddrconfig(const struct chan_info * chan,const struct rk3399_sdram_params * params,unsigned char channel,u32 ddrconfig)1452 static void set_ddrconfig(const struct chan_info *chan,
1453 const struct rk3399_sdram_params *params,
1454 unsigned char channel, u32 ddrconfig)
1455 {
1456 /* only need to set ddrconfig */
1457 struct msch_regs *ddr_msch_regs = chan->msch;
1458 unsigned int cs0_cap = 0;
1459 unsigned int cs1_cap = 0;
1460
1461 cs0_cap = (1 << (params->ch[channel].cap_info.cs0_row
1462 + params->ch[channel].cap_info.col
1463 + params->ch[channel].cap_info.bk
1464 + params->ch[channel].cap_info.bw - 20));
1465 if (params->ch[channel].cap_info.rank > 1)
1466 cs1_cap = cs0_cap >> (params->ch[channel].cap_info.cs0_row
1467 - params->ch[channel].cap_info.cs1_row);
1468 if (params->ch[channel].cap_info.row_3_4) {
1469 cs0_cap = cs0_cap * 3 / 4;
1470 cs1_cap = cs1_cap * 3 / 4;
1471 }
1472
1473 writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf);
1474 writel(((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8),
1475 &ddr_msch_regs->ddrsize);
1476 }
1477
sdram_msch_config(struct msch_regs * msch,struct sdram_msch_timings * noc_timings)1478 static void sdram_msch_config(struct msch_regs *msch,
1479 struct sdram_msch_timings *noc_timings)
1480 {
1481 writel(noc_timings->ddrtiminga0.d32,
1482 &msch->ddrtiminga0.d32);
1483 writel(noc_timings->ddrtimingb0.d32,
1484 &msch->ddrtimingb0.d32);
1485 writel(noc_timings->ddrtimingc0.d32,
1486 &msch->ddrtimingc0.d32);
1487 writel(noc_timings->devtodev0.d32,
1488 &msch->devtodev0.d32);
1489 writel(noc_timings->ddrmode.d32,
1490 &msch->ddrmode.d32);
1491 }
1492
dram_all_config(struct dram_info * dram,struct rk3399_sdram_params * params)1493 static void dram_all_config(struct dram_info *dram,
1494 struct rk3399_sdram_params *params)
1495 {
1496 u32 sys_reg2 = 0;
1497 u32 sys_reg3 = 0;
1498 unsigned int channel, idx;
1499
1500 for (channel = 0, idx = 0;
1501 (idx < params->base.num_channels) && (channel < 2);
1502 channel++) {
1503 struct msch_regs *ddr_msch_regs;
1504 struct sdram_msch_timings *noc_timing;
1505
1506 if (params->ch[channel].cap_info.col == 0)
1507 continue;
1508 idx++;
1509 sdram_org_config(¶ms->ch[channel].cap_info,
1510 ¶ms->base, &sys_reg2,
1511 &sys_reg3, channel);
1512 ddr_msch_regs = dram->chan[channel].msch;
1513 noc_timing = ¶ms->ch[channel].noc_timings;
1514 sdram_msch_config(ddr_msch_regs, noc_timing);
1515
1516 /**
1517 * rank 1 memory clock disable (dfi_dram_clk_disable = 1)
1518 *
1519 * The hardware for LPDDR4 with
1520 * - CLK0P/N connect to lower 16-bits
1521 * - CLK1P/N connect to higher 16-bits
1522 *
1523 * dfi dram clk is configured via CLK1P/N, so disabling
1524 * dfi dram clk will disable the CLK1P/N as well for lpddr4.
1525 */
1526 if (params->ch[channel].cap_info.rank == 1 &&
1527 params->base.dramtype != LPDDR4)
1528 setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
1529 1 << 17);
1530 }
1531
1532 writel(sys_reg2, &dram->pmugrf->os_reg2);
1533 writel(sys_reg3, &dram->pmugrf->os_reg3);
1534 rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
1535 params->base.stride << 10);
1536
1537 /* reboot hold register set */
1538 writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) |
1539 PRESET_GPIO1_HOLD(1),
1540 &dram->pmucru->pmucru_rstnhold_con[1]);
1541 clrsetbits_le32(&dram->cru->glb_rst_con, 0x3, 0x3);
1542 }
1543
set_cap_relate_config(const struct chan_info * chan,struct rk3399_sdram_params * params,unsigned int channel)1544 static void set_cap_relate_config(const struct chan_info *chan,
1545 struct rk3399_sdram_params *params,
1546 unsigned int channel)
1547 {
1548 u32 *denali_ctl = chan->pctl->denali_ctl;
1549 u32 tmp;
1550 struct sdram_msch_timings *noc_timing;
1551
1552 if (params->base.dramtype == LPDDR3) {
1553 tmp = (8 << params->ch[channel].cap_info.bw) /
1554 (8 << params->ch[channel].cap_info.dbw);
1555
1556 /**
1557 * memdata_ratio
1558 * 1 -> 0, 2 -> 1, 4 -> 2
1559 */
1560 clrsetbits_le32(&denali_ctl[197], 0x7,
1561 (tmp >> 1));
1562 clrsetbits_le32(&denali_ctl[198], 0x7 << 8,
1563 (tmp >> 1) << 8);
1564 }
1565
1566 noc_timing = ¶ms->ch[channel].noc_timings;
1567
1568 /*
1569 * noc timing bw relate timing is 32 bit, and real bw is 16bit
1570 * actually noc reg is setting at function dram_all_config
1571 */
1572 if (params->ch[channel].cap_info.bw == 16 &&
1573 noc_timing->ddrmode.b.mwrsize == 2) {
1574 if (noc_timing->ddrmode.b.burstsize)
1575 noc_timing->ddrmode.b.burstsize -= 1;
1576 noc_timing->ddrmode.b.mwrsize -= 1;
1577 noc_timing->ddrtimingc0.b.burstpenalty *= 2;
1578 noc_timing->ddrtimingc0.b.wrtomwr *= 2;
1579 }
1580 }
1581
calculate_ddrconfig(struct rk3399_sdram_params * params,u32 channel)1582 static u32 calculate_ddrconfig(struct rk3399_sdram_params *params, u32 channel)
1583 {
1584 unsigned int cs0_row = params->ch[channel].cap_info.cs0_row;
1585 unsigned int col = params->ch[channel].cap_info.col;
1586 unsigned int bw = params->ch[channel].cap_info.bw;
1587 u16 ddr_cfg_2_rbc[] = {
1588 /*
1589 * [6] highest bit col
1590 * [5:3] max row(14+n)
1591 * [2] insertion row
1592 * [1:0] col(9+n),col, data bus 32bit
1593 *
1594 * highbitcol, max_row, insertion_row, col
1595 */
1596 ((0 << 6) | (2 << 3) | (0 << 2) | 0), /* 0 */
1597 ((0 << 6) | (2 << 3) | (0 << 2) | 1), /* 1 */
1598 ((0 << 6) | (1 << 3) | (0 << 2) | 2), /* 2 */
1599 ((0 << 6) | (0 << 3) | (0 << 2) | 3), /* 3 */
1600 ((0 << 6) | (2 << 3) | (1 << 2) | 1), /* 4 */
1601 ((0 << 6) | (1 << 3) | (1 << 2) | 2), /* 5 */
1602 ((1 << 6) | (0 << 3) | (0 << 2) | 2), /* 6 */
1603 ((1 << 6) | (1 << 3) | (0 << 2) | 2), /* 7 */
1604 };
1605 u32 i;
1606
1607 col -= (bw == 2) ? 0 : 1;
1608 col -= 9;
1609
1610 for (i = 0; i < 4; i++) {
1611 if ((col == (ddr_cfg_2_rbc[i] & 0x3)) &&
1612 (cs0_row <= (((ddr_cfg_2_rbc[i] >> 3) & 0x7) + 14)))
1613 break;
1614 }
1615
1616 if (i >= 4)
1617 i = -EINVAL;
1618
1619 return i;
1620 }
1621
set_ddr_stride(struct rk3399_pmusgrf_regs * pmusgrf,u32 stride)1622 static void set_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf, u32 stride)
1623 {
1624 rk_clrsetreg(&pmusgrf->soc_con4, 0x1f << 10, stride << 10);
1625 }
1626
1627 #if !defined(CONFIG_RAM_RK3399_LPDDR4)
data_training_first(struct dram_info * dram,u32 channel,u8 rank,struct rk3399_sdram_params * params)1628 static int data_training_first(struct dram_info *dram, u32 channel, u8 rank,
1629 struct rk3399_sdram_params *params)
1630 {
1631 u8 training_flag = PI_READ_GATE_TRAINING;
1632
1633 /*
1634 * LPDDR3 CA training msut be trigger before
1635 * other training.
1636 * DDR3 is not have CA training.
1637 */
1638
1639 if (params->base.dramtype == LPDDR3)
1640 training_flag |= PI_CA_TRAINING;
1641
1642 return data_training(dram, channel, params, training_flag);
1643 }
1644
switch_to_phy_index1(struct dram_info * dram,struct rk3399_sdram_params * params)1645 static int switch_to_phy_index1(struct dram_info *dram,
1646 struct rk3399_sdram_params *params)
1647 {
1648 u32 channel;
1649 u32 *denali_phy;
1650 u32 ch_count = params->base.num_channels;
1651 int ret;
1652 int i = 0;
1653
1654 writel(RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1,
1655 1 << 4 | 1 << 2 | 1),
1656 &dram->cic->cic_ctrl0);
1657 while (!(readl(&dram->cic->cic_status0) & (1 << 2))) {
1658 mdelay(10);
1659 i++;
1660 if (i > 10) {
1661 debug("index1 frequency change overtime\n");
1662 return -ETIME;
1663 }
1664 }
1665
1666 i = 0;
1667 writel(RK_CLRSETBITS(1 << 1, 1 << 1), &dram->cic->cic_ctrl0);
1668 while (!(readl(&dram->cic->cic_status0) & (1 << 0))) {
1669 mdelay(10);
1670 i++;
1671 if (i > 10) {
1672 debug("index1 frequency done overtime\n");
1673 return -ETIME;
1674 }
1675 }
1676
1677 for (channel = 0; channel < ch_count; channel++) {
1678 denali_phy = dram->chan[channel].publ->denali_phy;
1679 clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
1680 ret = data_training(dram, channel, params, PI_FULL_TRAINING);
1681 if (ret < 0) {
1682 debug("index1 training failed\n");
1683 return ret;
1684 }
1685 }
1686
1687 return 0;
1688 }
1689
1690 struct rk3399_sdram_params
get_phy_index_params(u32 phy_fn,struct rk3399_sdram_params * params)1691 *get_phy_index_params(u32 phy_fn,
1692 struct rk3399_sdram_params *params)
1693 {
1694 if (phy_fn == 0)
1695 return params;
1696 else
1697 return NULL;
1698 }
1699
modify_param(const struct chan_info * chan,struct rk3399_sdram_params * params)1700 void modify_param(const struct chan_info *chan,
1701 struct rk3399_sdram_params *params)
1702 {
1703 struct rk3399_sdram_params *params_cfg;
1704 u32 *denali_pi_params;
1705
1706 denali_pi_params = params->pi_regs.denali_pi;
1707
1708 /* modify PHY F0/F1/F2 params */
1709 params_cfg = get_phy_index_params(0, params);
1710 set_ds_odt(chan, params_cfg, false, 0);
1711
1712 clrsetbits_le32(&denali_pi_params[45], 0x1 << 24, 0x1 << 24);
1713 clrsetbits_le32(&denali_pi_params[61], 0x1 << 24, 0x1 << 24);
1714 clrsetbits_le32(&denali_pi_params[76], 0x1 << 24, 0x1 << 24);
1715 clrsetbits_le32(&denali_pi_params[77], 0x1, 0x1);
1716 }
1717 #else
1718
1719 struct rk3399_sdram_params dfs_cfgs_lpddr4[] = {
1720 #include "sdram-rk3399-lpddr4-400.inc"
1721 #include "sdram-rk3399-lpddr4-800.inc"
1722 };
1723
1724 static struct rk3399_sdram_params
lpddr4_get_phy_index_params(u32 phy_fn,struct rk3399_sdram_params * params)1725 *lpddr4_get_phy_index_params(u32 phy_fn,
1726 struct rk3399_sdram_params *params)
1727 {
1728 if (phy_fn == 0)
1729 return params;
1730 else if (phy_fn == 1)
1731 return &dfs_cfgs_lpddr4[1];
1732 else if (phy_fn == 2)
1733 return &dfs_cfgs_lpddr4[0];
1734 else
1735 return NULL;
1736 }
1737
get_denali_pi(const struct chan_info * chan,struct rk3399_sdram_params * params,bool reg)1738 static void *get_denali_pi(const struct chan_info *chan,
1739 struct rk3399_sdram_params *params, bool reg)
1740 {
1741 return reg ? &chan->pi->denali_pi : ¶ms->pi_regs.denali_pi;
1742 }
1743
lpddr4_get_phy_fn(struct rk3399_sdram_params * params,u32 ctl_fn)1744 static u32 lpddr4_get_phy_fn(struct rk3399_sdram_params *params, u32 ctl_fn)
1745 {
1746 u32 lpddr4_phy_fn[] = {1, 0, 0xb};
1747
1748 return lpddr4_phy_fn[ctl_fn];
1749 }
1750
lpddr4_get_ctl_fn(struct rk3399_sdram_params * params,u32 phy_fn)1751 static u32 lpddr4_get_ctl_fn(struct rk3399_sdram_params *params, u32 phy_fn)
1752 {
1753 u32 lpddr4_ctl_fn[] = {1, 0, 2};
1754
1755 return lpddr4_ctl_fn[phy_fn];
1756 }
1757
get_ddr_stride(struct rk3399_pmusgrf_regs * pmusgrf)1758 static u32 get_ddr_stride(struct rk3399_pmusgrf_regs *pmusgrf)
1759 {
1760 return ((readl(&pmusgrf->soc_con4) >> 10) & 0x1F);
1761 }
1762
1763 /*
1764 * read mr_num mode register
1765 * rank = 1: cs0
1766 * rank = 2: cs1
1767 */
read_mr(struct rk3399_ddr_pctl_regs * ddr_pctl_regs,u32 rank,u32 mr_num,u32 * buf)1768 static int read_mr(struct rk3399_ddr_pctl_regs *ddr_pctl_regs, u32 rank,
1769 u32 mr_num, u32 *buf)
1770 {
1771 s32 timeout = 100;
1772
1773 writel(((1 << 16) | (((rank == 2) ? 1 : 0) << 8) | mr_num) << 8,
1774 &ddr_pctl_regs->denali_ctl[118]);
1775
1776 while (0 == (readl(&ddr_pctl_regs->denali_ctl[203]) &
1777 ((1 << 21) | (1 << 12)))) {
1778 udelay(1);
1779
1780 if (timeout <= 0) {
1781 printf("%s: pctl timeout!\n", __func__);
1782 return -ETIMEDOUT;
1783 }
1784
1785 timeout--;
1786 }
1787
1788 if (!(readl(&ddr_pctl_regs->denali_ctl[203]) & (1 << 12))) {
1789 *buf = readl(&ddr_pctl_regs->denali_ctl[119]) & 0xFF;
1790 } else {
1791 printf("%s: read mr failed with 0x%x status\n", __func__,
1792 readl(&ddr_pctl_regs->denali_ctl[17]) & 0x3);
1793 *buf = 0;
1794 }
1795
1796 setbits_le32(&ddr_pctl_regs->denali_ctl[205], (1 << 21) | (1 << 12));
1797
1798 return 0;
1799 }
1800
lpddr4_mr_detect(struct dram_info * dram,u32 channel,u8 rank,struct rk3399_sdram_params * params)1801 static int lpddr4_mr_detect(struct dram_info *dram, u32 channel, u8 rank,
1802 struct rk3399_sdram_params *params)
1803 {
1804 u64 cs0_cap;
1805 u32 stride;
1806 u32 cs = 0, col = 0, bk = 0, bw = 0, row_3_4 = 0;
1807 u32 cs0_row = 0, cs1_row = 0, ddrconfig = 0;
1808 u32 mr5, mr12, mr14;
1809 struct chan_info *chan = &dram->chan[channel];
1810 struct rk3399_ddr_pctl_regs *ddr_pctl_regs = chan->pctl;
1811 void __iomem *addr = NULL;
1812 int ret = 0;
1813 u32 val;
1814
1815 stride = get_ddr_stride(dram->pmusgrf);
1816
1817 if (params->ch[channel].cap_info.col == 0) {
1818 ret = -EPERM;
1819 goto end;
1820 }
1821
1822 cs = params->ch[channel].cap_info.rank;
1823 col = params->ch[channel].cap_info.col;
1824 bk = params->ch[channel].cap_info.bk;
1825 bw = params->ch[channel].cap_info.bw;
1826 row_3_4 = params->ch[channel].cap_info.row_3_4;
1827 cs0_row = params->ch[channel].cap_info.cs0_row;
1828 cs1_row = params->ch[channel].cap_info.cs1_row;
1829 ddrconfig = params->ch[channel].cap_info.ddrconfig;
1830
1831 /* 2GB */
1832 params->ch[channel].cap_info.rank = 2;
1833 params->ch[channel].cap_info.col = 10;
1834 params->ch[channel].cap_info.bk = 3;
1835 params->ch[channel].cap_info.bw = 2;
1836 params->ch[channel].cap_info.row_3_4 = 0;
1837 params->ch[channel].cap_info.cs0_row = 15;
1838 params->ch[channel].cap_info.cs1_row = 15;
1839 params->ch[channel].cap_info.ddrconfig = 1;
1840
1841 set_memory_map(chan, channel, params);
1842 params->ch[channel].cap_info.ddrconfig =
1843 calculate_ddrconfig(params, channel);
1844 set_ddrconfig(chan, params, channel,
1845 params->ch[channel].cap_info.ddrconfig);
1846 set_cap_relate_config(chan, params, channel);
1847
1848 cs0_cap = (1 << (params->ch[channel].cap_info.bw
1849 + params->ch[channel].cap_info.col
1850 + params->ch[channel].cap_info.bk
1851 + params->ch[channel].cap_info.cs0_row));
1852
1853 if (params->ch[channel].cap_info.row_3_4)
1854 cs0_cap = cs0_cap * 3 / 4;
1855
1856 if (channel == 0)
1857 set_ddr_stride(dram->pmusgrf, 0x17);
1858 else
1859 set_ddr_stride(dram->pmusgrf, 0x18);
1860
1861 /* read and write data to DRAM, avoid be optimized by compiler. */
1862 if (rank == 1)
1863 addr = (void __iomem *)0x100;
1864 else if (rank == 2)
1865 addr = (void __iomem *)(cs0_cap + 0x100);
1866
1867 val = readl(addr);
1868 writel(val + 1, addr);
1869
1870 read_mr(ddr_pctl_regs, rank, 5, &mr5);
1871 read_mr(ddr_pctl_regs, rank, 12, &mr12);
1872 read_mr(ddr_pctl_regs, rank, 14, &mr14);
1873
1874 if (mr5 == 0 || mr12 != 0x4d || mr14 != 0x4d) {
1875 ret = -EINVAL;
1876 goto end;
1877 }
1878 end:
1879 params->ch[channel].cap_info.rank = cs;
1880 params->ch[channel].cap_info.col = col;
1881 params->ch[channel].cap_info.bk = bk;
1882 params->ch[channel].cap_info.bw = bw;
1883 params->ch[channel].cap_info.row_3_4 = row_3_4;
1884 params->ch[channel].cap_info.cs0_row = cs0_row;
1885 params->ch[channel].cap_info.cs1_row = cs1_row;
1886 params->ch[channel].cap_info.ddrconfig = ddrconfig;
1887
1888 set_ddr_stride(dram->pmusgrf, stride);
1889
1890 return ret;
1891 }
1892
set_lpddr4_dq_odt(const struct chan_info * chan,struct rk3399_sdram_params * params,u32 ctl_fn,bool en,bool ctl_phy_reg,u32 mr5)1893 static void set_lpddr4_dq_odt(const struct chan_info *chan,
1894 struct rk3399_sdram_params *params, u32 ctl_fn,
1895 bool en, bool ctl_phy_reg, u32 mr5)
1896 {
1897 u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
1898 u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
1899 struct io_setting *io;
1900 u32 reg_value;
1901
1902 io = lpddr4_get_io_settings(params, mr5);
1903 if (en)
1904 reg_value = io->dq_odt;
1905 else
1906 reg_value = 0;
1907
1908 switch (ctl_fn) {
1909 case 0:
1910 clrsetbits_le32(&denali_ctl[139], 0x7 << 24, reg_value << 24);
1911 clrsetbits_le32(&denali_ctl[153], 0x7 << 24, reg_value << 24);
1912
1913 clrsetbits_le32(&denali_pi[132], 0x7 << 0, (reg_value << 0));
1914 clrsetbits_le32(&denali_pi[139], 0x7 << 16, (reg_value << 16));
1915 clrsetbits_le32(&denali_pi[147], 0x7 << 0, (reg_value << 0));
1916 clrsetbits_le32(&denali_pi[154], 0x7 << 16, (reg_value << 16));
1917 break;
1918 case 1:
1919 clrsetbits_le32(&denali_ctl[140], 0x7 << 0, reg_value << 0);
1920 clrsetbits_le32(&denali_ctl[154], 0x7 << 0, reg_value << 0);
1921
1922 clrsetbits_le32(&denali_pi[129], 0x7 << 16, (reg_value << 16));
1923 clrsetbits_le32(&denali_pi[137], 0x7 << 0, (reg_value << 0));
1924 clrsetbits_le32(&denali_pi[144], 0x7 << 16, (reg_value << 16));
1925 clrsetbits_le32(&denali_pi[152], 0x7 << 0, (reg_value << 0));
1926 break;
1927 case 2:
1928 default:
1929 clrsetbits_le32(&denali_ctl[140], 0x7 << 8, (reg_value << 8));
1930 clrsetbits_le32(&denali_ctl[154], 0x7 << 8, (reg_value << 8));
1931
1932 clrsetbits_le32(&denali_pi[127], 0x7 << 0, (reg_value << 0));
1933 clrsetbits_le32(&denali_pi[134], 0x7 << 16, (reg_value << 16));
1934 clrsetbits_le32(&denali_pi[142], 0x7 << 0, (reg_value << 0));
1935 clrsetbits_le32(&denali_pi[149], 0x7 << 16, (reg_value << 16));
1936 break;
1937 }
1938 }
1939
set_lpddr4_ca_odt(const struct chan_info * chan,struct rk3399_sdram_params * params,u32 ctl_fn,bool en,bool ctl_phy_reg,u32 mr5)1940 static void set_lpddr4_ca_odt(const struct chan_info *chan,
1941 struct rk3399_sdram_params *params, u32 ctl_fn,
1942 bool en, bool ctl_phy_reg, u32 mr5)
1943 {
1944 u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
1945 u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
1946 struct io_setting *io;
1947 u32 reg_value;
1948
1949 io = lpddr4_get_io_settings(params, mr5);
1950 if (en)
1951 reg_value = io->ca_odt;
1952 else
1953 reg_value = 0;
1954
1955 switch (ctl_fn) {
1956 case 0:
1957 clrsetbits_le32(&denali_ctl[139], 0x7 << 28, reg_value << 28);
1958 clrsetbits_le32(&denali_ctl[153], 0x7 << 28, reg_value << 28);
1959
1960 clrsetbits_le32(&denali_pi[132], 0x7 << 4, reg_value << 4);
1961 clrsetbits_le32(&denali_pi[139], 0x7 << 20, reg_value << 20);
1962 clrsetbits_le32(&denali_pi[147], 0x7 << 4, reg_value << 4);
1963 clrsetbits_le32(&denali_pi[154], 0x7 << 20, reg_value << 20);
1964 break;
1965 case 1:
1966 clrsetbits_le32(&denali_ctl[140], 0x7 << 4, reg_value << 4);
1967 clrsetbits_le32(&denali_ctl[154], 0x7 << 4, reg_value << 4);
1968
1969 clrsetbits_le32(&denali_pi[129], 0x7 << 20, reg_value << 20);
1970 clrsetbits_le32(&denali_pi[137], 0x7 << 4, reg_value << 4);
1971 clrsetbits_le32(&denali_pi[144], 0x7 << 20, reg_value << 20);
1972 clrsetbits_le32(&denali_pi[152], 0x7 << 4, reg_value << 4);
1973 break;
1974 case 2:
1975 default:
1976 clrsetbits_le32(&denali_ctl[140], 0x7 << 12, (reg_value << 12));
1977 clrsetbits_le32(&denali_ctl[154], 0x7 << 12, (reg_value << 12));
1978
1979 clrsetbits_le32(&denali_pi[127], 0x7 << 4, reg_value << 4);
1980 clrsetbits_le32(&denali_pi[134], 0x7 << 20, reg_value << 20);
1981 clrsetbits_le32(&denali_pi[142], 0x7 << 4, reg_value << 4);
1982 clrsetbits_le32(&denali_pi[149], 0x7 << 20, reg_value << 20);
1983 break;
1984 }
1985 }
1986
set_lpddr4_MR3(const struct chan_info * chan,struct rk3399_sdram_params * params,u32 ctl_fn,bool ctl_phy_reg,u32 mr5)1987 static void set_lpddr4_MR3(const struct chan_info *chan,
1988 struct rk3399_sdram_params *params, u32 ctl_fn,
1989 bool ctl_phy_reg, u32 mr5)
1990 {
1991 u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
1992 u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
1993 struct io_setting *io;
1994 u32 reg_value;
1995
1996 io = lpddr4_get_io_settings(params, mr5);
1997
1998 reg_value = ((io->pdds << 3) | 1);
1999
2000 switch (ctl_fn) {
2001 case 0:
2002 clrsetbits_le32(&denali_ctl[138], 0xFFFF, reg_value);
2003 clrsetbits_le32(&denali_ctl[152], 0xFFFF, reg_value);
2004
2005 clrsetbits_le32(&denali_pi[131], 0xFFFF << 16, reg_value << 16);
2006 clrsetbits_le32(&denali_pi[139], 0xFFFF, reg_value);
2007 clrsetbits_le32(&denali_pi[146], 0xFFFF << 16, reg_value << 16);
2008 clrsetbits_le32(&denali_pi[154], 0xFFFF, reg_value);
2009 break;
2010 case 1:
2011 clrsetbits_le32(&denali_ctl[138], 0xFFFF << 16,
2012 reg_value << 16);
2013 clrsetbits_le32(&denali_ctl[152], 0xFFFF << 16,
2014 reg_value << 16);
2015
2016 clrsetbits_le32(&denali_pi[129], 0xFFFF, reg_value);
2017 clrsetbits_le32(&denali_pi[136], 0xFFFF << 16, reg_value << 16);
2018 clrsetbits_le32(&denali_pi[144], 0xFFFF, reg_value);
2019 clrsetbits_le32(&denali_pi[151], 0xFFFF << 16, reg_value << 16);
2020 break;
2021 case 2:
2022 default:
2023 clrsetbits_le32(&denali_ctl[139], 0xFFFF, reg_value);
2024 clrsetbits_le32(&denali_ctl[153], 0xFFFF, reg_value);
2025
2026 clrsetbits_le32(&denali_pi[126], 0xFFFF << 16, reg_value << 16);
2027 clrsetbits_le32(&denali_pi[134], 0xFFFF, reg_value);
2028 clrsetbits_le32(&denali_pi[141], 0xFFFF << 16, reg_value << 16);
2029 clrsetbits_le32(&denali_pi[149], 0xFFFF, reg_value);
2030 break;
2031 }
2032 }
2033
set_lpddr4_MR12(const struct chan_info * chan,struct rk3399_sdram_params * params,u32 ctl_fn,bool ctl_phy_reg,u32 mr5)2034 static void set_lpddr4_MR12(const struct chan_info *chan,
2035 struct rk3399_sdram_params *params, u32 ctl_fn,
2036 bool ctl_phy_reg, u32 mr5)
2037 {
2038 u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
2039 u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
2040 struct io_setting *io;
2041 u32 reg_value;
2042
2043 io = lpddr4_get_io_settings(params, mr5);
2044
2045 reg_value = io->ca_vref;
2046
2047 switch (ctl_fn) {
2048 case 0:
2049 clrsetbits_le32(&denali_ctl[140], 0xFFFF << 16,
2050 reg_value << 16);
2051 clrsetbits_le32(&denali_ctl[154], 0xFFFF << 16,
2052 reg_value << 16);
2053
2054 clrsetbits_le32(&denali_pi[132], 0xFF << 8, reg_value << 8);
2055 clrsetbits_le32(&denali_pi[139], 0xFF << 24, reg_value << 24);
2056 clrsetbits_le32(&denali_pi[147], 0xFF << 8, reg_value << 8);
2057 clrsetbits_le32(&denali_pi[154], 0xFF << 24, reg_value << 24);
2058 break;
2059 case 1:
2060 clrsetbits_le32(&denali_ctl[141], 0xFFFF, reg_value);
2061 clrsetbits_le32(&denali_ctl[155], 0xFFFF, reg_value);
2062
2063 clrsetbits_le32(&denali_pi[129], 0xFF << 24, reg_value << 24);
2064 clrsetbits_le32(&denali_pi[137], 0xFF << 8, reg_value << 8);
2065 clrsetbits_le32(&denali_pi[144], 0xFF << 24, reg_value << 24);
2066 clrsetbits_le32(&denali_pi[152], 0xFF << 8, reg_value << 8);
2067 break;
2068 case 2:
2069 default:
2070 clrsetbits_le32(&denali_ctl[141], 0xFFFF << 16,
2071 reg_value << 16);
2072 clrsetbits_le32(&denali_ctl[155], 0xFFFF << 16,
2073 reg_value << 16);
2074
2075 clrsetbits_le32(&denali_pi[127], 0xFF << 8, reg_value << 8);
2076 clrsetbits_le32(&denali_pi[134], 0xFF << 24, reg_value << 24);
2077 clrsetbits_le32(&denali_pi[142], 0xFF << 8, reg_value << 8);
2078 clrsetbits_le32(&denali_pi[149], 0xFF << 24, reg_value << 24);
2079 break;
2080 }
2081 }
2082
set_lpddr4_MR14(const struct chan_info * chan,struct rk3399_sdram_params * params,u32 ctl_fn,bool ctl_phy_reg,u32 mr5)2083 static void set_lpddr4_MR14(const struct chan_info *chan,
2084 struct rk3399_sdram_params *params, u32 ctl_fn,
2085 bool ctl_phy_reg, u32 mr5)
2086 {
2087 u32 *denali_ctl = get_denali_ctl(chan, params, ctl_phy_reg);
2088 u32 *denali_pi = get_denali_pi(chan, params, ctl_phy_reg);
2089 struct io_setting *io;
2090 u32 reg_value;
2091
2092 io = lpddr4_get_io_settings(params, mr5);
2093
2094 reg_value = io->dq_vref;
2095
2096 switch (ctl_fn) {
2097 case 0:
2098 clrsetbits_le32(&denali_ctl[142], 0xFFFF << 16,
2099 reg_value << 16);
2100 clrsetbits_le32(&denali_ctl[156], 0xFFFF << 16,
2101 reg_value << 16);
2102
2103 clrsetbits_le32(&denali_pi[132], 0xFF << 16, reg_value << 16);
2104 clrsetbits_le32(&denali_pi[140], 0xFF << 0, reg_value << 0);
2105 clrsetbits_le32(&denali_pi[147], 0xFF << 16, reg_value << 16);
2106 clrsetbits_le32(&denali_pi[155], 0xFF << 0, reg_value << 0);
2107 break;
2108 case 1:
2109 clrsetbits_le32(&denali_ctl[143], 0xFFFF, reg_value);
2110 clrsetbits_le32(&denali_ctl[157], 0xFFFF, reg_value);
2111
2112 clrsetbits_le32(&denali_pi[130], 0xFF << 0, reg_value << 0);
2113 clrsetbits_le32(&denali_pi[137], 0xFF << 16, reg_value << 16);
2114 clrsetbits_le32(&denali_pi[145], 0xFF << 0, reg_value << 0);
2115 clrsetbits_le32(&denali_pi[152], 0xFF << 16, reg_value << 16);
2116 break;
2117 case 2:
2118 default:
2119 clrsetbits_le32(&denali_ctl[143], 0xFFFF << 16,
2120 reg_value << 16);
2121 clrsetbits_le32(&denali_ctl[157], 0xFFFF << 16,
2122 reg_value << 16);
2123
2124 clrsetbits_le32(&denali_pi[127], 0xFF << 16, reg_value << 16);
2125 clrsetbits_le32(&denali_pi[135], 0xFF << 0, reg_value << 0);
2126 clrsetbits_le32(&denali_pi[142], 0xFF << 16, reg_value << 16);
2127 clrsetbits_le32(&denali_pi[150], 0xFF << 0, reg_value << 0);
2128 break;
2129 }
2130 }
2131
lpddr4_modify_param(const struct chan_info * chan,struct rk3399_sdram_params * params)2132 void lpddr4_modify_param(const struct chan_info *chan,
2133 struct rk3399_sdram_params *params)
2134 {
2135 struct rk3399_sdram_params *params_cfg;
2136 u32 *denali_ctl_params;
2137 u32 *denali_pi_params;
2138 u32 *denali_phy_params;
2139
2140 denali_ctl_params = params->pctl_regs.denali_ctl;
2141 denali_pi_params = params->pi_regs.denali_pi;
2142 denali_phy_params = params->phy_regs.denali_phy;
2143
2144 set_lpddr4_dq_odt(chan, params, 2, true, false, 0);
2145 set_lpddr4_ca_odt(chan, params, 2, true, false, 0);
2146 set_lpddr4_MR3(chan, params, 2, false, 0);
2147 set_lpddr4_MR12(chan, params, 2, false, 0);
2148 set_lpddr4_MR14(chan, params, 2, false, 0);
2149 params_cfg = lpddr4_get_phy_index_params(0, params);
2150 set_ds_odt(chan, params_cfg, false, 0);
2151 /* read two cycle preamble */
2152 clrsetbits_le32(&denali_ctl_params[200], 0x3 << 24, 0x3 << 24);
2153 clrsetbits_le32(&denali_phy_params[7], 0x3 << 24, 0x3 << 24);
2154 clrsetbits_le32(&denali_phy_params[135], 0x3 << 24, 0x3 << 24);
2155 clrsetbits_le32(&denali_phy_params[263], 0x3 << 24, 0x3 << 24);
2156 clrsetbits_le32(&denali_phy_params[391], 0x3 << 24, 0x3 << 24);
2157
2158 /* boot frequency two cycle preamble */
2159 clrsetbits_le32(&denali_phy_params[2], 0x3 << 16, 0x3 << 16);
2160 clrsetbits_le32(&denali_phy_params[130], 0x3 << 16, 0x3 << 16);
2161 clrsetbits_le32(&denali_phy_params[258], 0x3 << 16, 0x3 << 16);
2162 clrsetbits_le32(&denali_phy_params[386], 0x3 << 16, 0x3 << 16);
2163
2164 clrsetbits_le32(&denali_pi_params[45], 0x3 << 8, 0x3 << 8);
2165 clrsetbits_le32(&denali_pi_params[58], 0x1, 0x1);
2166
2167 /*
2168 * bypass mode need PHY_SLICE_PWR_RDC_DISABLE_x = 1,
2169 * boot frequency mode use bypass mode
2170 */
2171 setbits_le32(&denali_phy_params[10], 1 << 16);
2172 setbits_le32(&denali_phy_params[138], 1 << 16);
2173 setbits_le32(&denali_phy_params[266], 1 << 16);
2174 setbits_le32(&denali_phy_params[394], 1 << 16);
2175
2176 clrsetbits_le32(&denali_pi_params[45], 0x1 << 24, 0x1 << 24);
2177 clrsetbits_le32(&denali_pi_params[61], 0x1 << 24, 0x1 << 24);
2178 clrsetbits_le32(&denali_pi_params[76], 0x1 << 24, 0x1 << 24);
2179 clrsetbits_le32(&denali_pi_params[77], 0x1, 0x1);
2180 }
2181
lpddr4_copy_phy(struct dram_info * dram,struct rk3399_sdram_params * params,u32 phy_fn,struct rk3399_sdram_params * params_cfg,u32 channel)2182 static void lpddr4_copy_phy(struct dram_info *dram,
2183 struct rk3399_sdram_params *params, u32 phy_fn,
2184 struct rk3399_sdram_params *params_cfg,
2185 u32 channel)
2186 {
2187 u32 *denali_ctl, *denali_phy;
2188 u32 *denali_phy_params;
2189 u32 speed = 0;
2190 u32 ctl_fn, mr5;
2191
2192 denali_ctl = dram->chan[channel].pctl->denali_ctl;
2193 denali_phy = dram->chan[channel].publ->denali_phy;
2194 denali_phy_params = params_cfg->phy_regs.denali_phy;
2195
2196 /* switch index */
2197 clrsetbits_le32(&denali_phy_params[896], 0x3 << 8,
2198 phy_fn << 8);
2199 writel(denali_phy_params[896], &denali_phy[896]);
2200
2201 /* phy_pll_ctrl_ca, phy_pll_ctrl */
2202 writel(denali_phy_params[911], &denali_phy[911]);
2203
2204 /* phy_low_freq_sel */
2205 clrsetbits_le32(&denali_phy[913], 0x1,
2206 denali_phy_params[913] & 0x1);
2207
2208 /* phy_grp_slave_delay_x, phy_cslvl_dly_step */
2209 writel(denali_phy_params[916], &denali_phy[916]);
2210 writel(denali_phy_params[917], &denali_phy[917]);
2211 writel(denali_phy_params[918], &denali_phy[918]);
2212
2213 /* phy_adrz_sw_wraddr_shift_x */
2214 writel(denali_phy_params[512], &denali_phy[512]);
2215 clrsetbits_le32(&denali_phy[513], 0xffff,
2216 denali_phy_params[513] & 0xffff);
2217 writel(denali_phy_params[640], &denali_phy[640]);
2218 clrsetbits_le32(&denali_phy[641], 0xffff,
2219 denali_phy_params[641] & 0xffff);
2220 writel(denali_phy_params[768], &denali_phy[768]);
2221 clrsetbits_le32(&denali_phy[769], 0xffff,
2222 denali_phy_params[769] & 0xffff);
2223
2224 writel(denali_phy_params[544], &denali_phy[544]);
2225 writel(denali_phy_params[545], &denali_phy[545]);
2226 writel(denali_phy_params[546], &denali_phy[546]);
2227 writel(denali_phy_params[547], &denali_phy[547]);
2228
2229 writel(denali_phy_params[672], &denali_phy[672]);
2230 writel(denali_phy_params[673], &denali_phy[673]);
2231 writel(denali_phy_params[674], &denali_phy[674]);
2232 writel(denali_phy_params[675], &denali_phy[675]);
2233
2234 writel(denali_phy_params[800], &denali_phy[800]);
2235 writel(denali_phy_params[801], &denali_phy[801]);
2236 writel(denali_phy_params[802], &denali_phy[802]);
2237 writel(denali_phy_params[803], &denali_phy[803]);
2238
2239 /*
2240 * phy_adr_master_delay_start_x
2241 * phy_adr_master_delay_step_x
2242 * phy_adr_master_delay_wait_x
2243 */
2244 writel(denali_phy_params[548], &denali_phy[548]);
2245 writel(denali_phy_params[676], &denali_phy[676]);
2246 writel(denali_phy_params[804], &denali_phy[804]);
2247
2248 /* phy_adr_calvl_dly_step_x */
2249 writel(denali_phy_params[549], &denali_phy[549]);
2250 writel(denali_phy_params[677], &denali_phy[677]);
2251 writel(denali_phy_params[805], &denali_phy[805]);
2252
2253 /*
2254 * phy_clk_wrdm_slave_delay_x
2255 * phy_clk_wrdqz_slave_delay_x
2256 * phy_clk_wrdqs_slave_delay_x
2257 */
2258 sdram_copy_to_reg((u32 *)&denali_phy[59],
2259 (u32 *)&denali_phy_params[59], (63 - 58) * 4);
2260 sdram_copy_to_reg((u32 *)&denali_phy[187],
2261 (u32 *)&denali_phy_params[187], (191 - 186) * 4);
2262 sdram_copy_to_reg((u32 *)&denali_phy[315],
2263 (u32 *)&denali_phy_params[315], (319 - 314) * 4);
2264 sdram_copy_to_reg((u32 *)&denali_phy[443],
2265 (u32 *)&denali_phy_params[443], (447 - 442) * 4);
2266
2267 /*
2268 * phy_dqs_tsel_wr_timing_x 8bits denali_phy_84/212/340/468 offset_8
2269 * dqs_tsel_wr_end[7:4] add half cycle
2270 * phy_dq_tsel_wr_timing_x 8bits denali_phy_83/211/339/467 offset_8
2271 * dq_tsel_wr_end[7:4] add half cycle
2272 */
2273 writel(denali_phy_params[83] + (0x10 << 16), &denali_phy[83]);
2274 writel(denali_phy_params[84] + (0x10 << 8), &denali_phy[84]);
2275 writel(denali_phy_params[85], &denali_phy[85]);
2276
2277 writel(denali_phy_params[211] + (0x10 << 16), &denali_phy[211]);
2278 writel(denali_phy_params[212] + (0x10 << 8), &denali_phy[212]);
2279 writel(denali_phy_params[213], &denali_phy[213]);
2280
2281 writel(denali_phy_params[339] + (0x10 << 16), &denali_phy[339]);
2282 writel(denali_phy_params[340] + (0x10 << 8), &denali_phy[340]);
2283 writel(denali_phy_params[341], &denali_phy[341]);
2284
2285 writel(denali_phy_params[467] + (0x10 << 16), &denali_phy[467]);
2286 writel(denali_phy_params[468] + (0x10 << 8), &denali_phy[468]);
2287 writel(denali_phy_params[469], &denali_phy[469]);
2288
2289 /*
2290 * phy_gtlvl_resp_wait_cnt_x
2291 * phy_gtlvl_dly_step_x
2292 * phy_wrlvl_resp_wait_cnt_x
2293 * phy_gtlvl_final_step_x
2294 * phy_gtlvl_back_step_x
2295 * phy_rdlvl_dly_step_x
2296 *
2297 * phy_master_delay_step_x
2298 * phy_master_delay_wait_x
2299 * phy_wrlvl_dly_step_x
2300 * phy_rptr_update_x
2301 * phy_wdqlvl_dly_step_x
2302 */
2303 writel(denali_phy_params[87], &denali_phy[87]);
2304 writel(denali_phy_params[88], &denali_phy[88]);
2305 writel(denali_phy_params[89], &denali_phy[89]);
2306 writel(denali_phy_params[90], &denali_phy[90]);
2307
2308 writel(denali_phy_params[215], &denali_phy[215]);
2309 writel(denali_phy_params[216], &denali_phy[216]);
2310 writel(denali_phy_params[217], &denali_phy[217]);
2311 writel(denali_phy_params[218], &denali_phy[218]);
2312
2313 writel(denali_phy_params[343], &denali_phy[343]);
2314 writel(denali_phy_params[344], &denali_phy[344]);
2315 writel(denali_phy_params[345], &denali_phy[345]);
2316 writel(denali_phy_params[346], &denali_phy[346]);
2317
2318 writel(denali_phy_params[471], &denali_phy[471]);
2319 writel(denali_phy_params[472], &denali_phy[472]);
2320 writel(denali_phy_params[473], &denali_phy[473]);
2321 writel(denali_phy_params[474], &denali_phy[474]);
2322
2323 /*
2324 * phy_gtlvl_lat_adj_start_x
2325 * phy_gtlvl_rddqs_slv_dly_start_x
2326 * phy_rdlvl_rddqs_dq_slv_dly_start_x
2327 * phy_wdqlvl_dqdm_slv_dly_start_x
2328 */
2329 writel(denali_phy_params[80], &denali_phy[80]);
2330 writel(denali_phy_params[81], &denali_phy[81]);
2331
2332 writel(denali_phy_params[208], &denali_phy[208]);
2333 writel(denali_phy_params[209], &denali_phy[209]);
2334
2335 writel(denali_phy_params[336], &denali_phy[336]);
2336 writel(denali_phy_params[337], &denali_phy[337]);
2337
2338 writel(denali_phy_params[464], &denali_phy[464]);
2339 writel(denali_phy_params[465], &denali_phy[465]);
2340
2341 /*
2342 * phy_master_delay_start_x
2343 * phy_sw_master_mode_x
2344 * phy_rddata_en_tsel_dly_x
2345 */
2346 writel(denali_phy_params[86], &denali_phy[86]);
2347 writel(denali_phy_params[214], &denali_phy[214]);
2348 writel(denali_phy_params[342], &denali_phy[342]);
2349 writel(denali_phy_params[470], &denali_phy[470]);
2350
2351 /*
2352 * phy_rddqz_slave_delay_x
2353 * phy_rddqs_dqz_fall_slave_delay_x
2354 * phy_rddqs_dqz_rise_slave_delay_x
2355 * phy_rddqs_dm_fall_slave_delay_x
2356 * phy_rddqs_dm_rise_slave_delay_x
2357 * phy_rddqs_gate_slave_delay_x
2358 * phy_wrlvl_delay_early_threshold_x
2359 * phy_write_path_lat_add_x
2360 * phy_rddqs_latency_adjust_x
2361 * phy_wrlvl_delay_period_threshold_x
2362 * phy_wrlvl_early_force_zero_x
2363 */
2364 sdram_copy_to_reg((u32 *)&denali_phy[64],
2365 (u32 *)&denali_phy_params[64], (67 - 63) * 4);
2366 clrsetbits_le32(&denali_phy[68], 0xfffffc00,
2367 denali_phy_params[68] & 0xfffffc00);
2368 sdram_copy_to_reg((u32 *)&denali_phy[69],
2369 (u32 *)&denali_phy_params[69], (79 - 68) * 4);
2370 sdram_copy_to_reg((u32 *)&denali_phy[192],
2371 (u32 *)&denali_phy_params[192], (195 - 191) * 4);
2372 clrsetbits_le32(&denali_phy[196], 0xfffffc00,
2373 denali_phy_params[196] & 0xfffffc00);
2374 sdram_copy_to_reg((u32 *)&denali_phy[197],
2375 (u32 *)&denali_phy_params[197], (207 - 196) * 4);
2376 sdram_copy_to_reg((u32 *)&denali_phy[320],
2377 (u32 *)&denali_phy_params[320], (323 - 319) * 4);
2378 clrsetbits_le32(&denali_phy[324], 0xfffffc00,
2379 denali_phy_params[324] & 0xfffffc00);
2380 sdram_copy_to_reg((u32 *)&denali_phy[325],
2381 (u32 *)&denali_phy_params[325], (335 - 324) * 4);
2382 sdram_copy_to_reg((u32 *)&denali_phy[448],
2383 (u32 *)&denali_phy_params[448], (451 - 447) * 4);
2384 clrsetbits_le32(&denali_phy[452], 0xfffffc00,
2385 denali_phy_params[452] & 0xfffffc00);
2386 sdram_copy_to_reg((u32 *)&denali_phy[453],
2387 (u32 *)&denali_phy_params[453], (463 - 452) * 4);
2388
2389 /* phy_two_cyc_preamble_x */
2390 clrsetbits_le32(&denali_phy[7], 0x3 << 24,
2391 denali_phy_params[7] & (0x3 << 24));
2392 clrsetbits_le32(&denali_phy[135], 0x3 << 24,
2393 denali_phy_params[135] & (0x3 << 24));
2394 clrsetbits_le32(&denali_phy[263], 0x3 << 24,
2395 denali_phy_params[263] & (0x3 << 24));
2396 clrsetbits_le32(&denali_phy[391], 0x3 << 24,
2397 denali_phy_params[391] & (0x3 << 24));
2398
2399 /* speed */
2400 if (params_cfg->base.ddr_freq < 400)
2401 speed = 0x0;
2402 else if (params_cfg->base.ddr_freq < 800)
2403 speed = 0x1;
2404 else if (params_cfg->base.ddr_freq < 1200)
2405 speed = 0x2;
2406
2407 /* phy_924 phy_pad_fdbk_drive */
2408 clrsetbits_le32(&denali_phy[924], 0x3 << 21, speed << 21);
2409 /* phy_926 phy_pad_data_drive */
2410 clrsetbits_le32(&denali_phy[926], 0x3 << 9, speed << 9);
2411 /* phy_927 phy_pad_dqs_drive */
2412 clrsetbits_le32(&denali_phy[927], 0x3 << 9, speed << 9);
2413 /* phy_928 phy_pad_addr_drive */
2414 clrsetbits_le32(&denali_phy[928], 0x3 << 17, speed << 17);
2415 /* phy_929 phy_pad_clk_drive */
2416 clrsetbits_le32(&denali_phy[929], 0x3 << 17, speed << 17);
2417 /* phy_935 phy_pad_cke_drive */
2418 clrsetbits_le32(&denali_phy[935], 0x3 << 17, speed << 17);
2419 /* phy_937 phy_pad_rst_drive */
2420 clrsetbits_le32(&denali_phy[937], 0x3 << 17, speed << 17);
2421 /* phy_939 phy_pad_cs_drive */
2422 clrsetbits_le32(&denali_phy[939], 0x3 << 17, speed << 17);
2423
2424 if (params_cfg->base.dramtype == LPDDR4) {
2425 read_mr(dram->chan[channel].pctl, 1, 5, &mr5);
2426 set_ds_odt(&dram->chan[channel], params_cfg, true, mr5);
2427
2428 ctl_fn = lpddr4_get_ctl_fn(params_cfg, phy_fn);
2429 set_lpddr4_dq_odt(&dram->chan[channel], params_cfg,
2430 ctl_fn, true, true, mr5);
2431 set_lpddr4_ca_odt(&dram->chan[channel], params_cfg,
2432 ctl_fn, true, true, mr5);
2433 set_lpddr4_MR3(&dram->chan[channel], params_cfg,
2434 ctl_fn, true, mr5);
2435 set_lpddr4_MR12(&dram->chan[channel], params_cfg,
2436 ctl_fn, true, mr5);
2437 set_lpddr4_MR14(&dram->chan[channel], params_cfg,
2438 ctl_fn, true, mr5);
2439
2440 /*
2441 * if phy_sw_master_mode_x not bypass mode,
2442 * clear phy_slice_pwr_rdc_disable.
2443 * note: need use timings, not ddr_publ_regs
2444 */
2445 if (!((denali_phy_params[86] >> 8) & (1 << 2))) {
2446 clrbits_le32(&denali_phy[10], 1 << 16);
2447 clrbits_le32(&denali_phy[138], 1 << 16);
2448 clrbits_le32(&denali_phy[266], 1 << 16);
2449 clrbits_le32(&denali_phy[394], 1 << 16);
2450 }
2451
2452 /*
2453 * when PHY_PER_CS_TRAINING_EN=1, W2W_DIFFCS_DLY_Fx can't
2454 * smaller than 8
2455 * NOTE: need use timings, not ddr_publ_regs
2456 */
2457 if ((denali_phy_params[84] >> 16) & 1) {
2458 if (((readl(&denali_ctl[217 + ctl_fn]) >>
2459 16) & 0x1f) < 8)
2460 clrsetbits_le32(&denali_ctl[217 + ctl_fn],
2461 0x1f << 16,
2462 8 << 16);
2463 }
2464 }
2465 }
2466
lpddr4_set_phy(struct dram_info * dram,struct rk3399_sdram_params * params,u32 phy_fn,struct rk3399_sdram_params * params_cfg)2467 static void lpddr4_set_phy(struct dram_info *dram,
2468 struct rk3399_sdram_params *params, u32 phy_fn,
2469 struct rk3399_sdram_params *params_cfg)
2470 {
2471 u32 channel;
2472
2473 for (channel = 0; channel < 2; channel++)
2474 lpddr4_copy_phy(dram, params, phy_fn, params_cfg,
2475 channel);
2476 }
2477
lpddr4_set_ctl(struct dram_info * dram,struct rk3399_sdram_params * params,u32 fn,u32 hz)2478 static int lpddr4_set_ctl(struct dram_info *dram,
2479 struct rk3399_sdram_params *params,
2480 u32 fn, u32 hz)
2481 {
2482 u32 channel;
2483 int ret_clk, ret;
2484
2485 /* cci idle req stall */
2486 writel(0x70007, &dram->grf->soc_con0);
2487
2488 /* enable all clk */
2489 setbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7));
2490
2491 /* idle */
2492 setbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18));
2493 while ((readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18))
2494 != (0x3 << 18))
2495 ;
2496
2497 /* change freq */
2498 writel((((0x3 << 4) | (1 << 2) | 1) << 16) |
2499 (fn << 4) | (1 << 2) | 1, &dram->cic->cic_ctrl0);
2500 while (!(readl(&dram->cic->cic_status0) & (1 << 2)))
2501 ;
2502
2503 ret_clk = clk_set_rate(&dram->ddr_clk, hz);
2504 if (ret_clk < 0) {
2505 printf("%s clk set failed %d\n", __func__, ret_clk);
2506 return ret_clk;
2507 }
2508
2509 writel(0x20002, &dram->cic->cic_ctrl0);
2510 while (!(readl(&dram->cic->cic_status0) & (1 << 0)))
2511 ;
2512
2513 /* deidle */
2514 clrbits_le32(&dram->pmu->pmu_bus_idle_req, (0x3 << 18));
2515 while (readl(&dram->pmu->pmu_bus_idle_st) & (0x3 << 18))
2516 ;
2517
2518 /* clear enable all clk */
2519 clrbits_le32(&dram->pmu->pmu_noc_auto_ena, (0x3 << 7));
2520
2521 /* lpddr4 ctl2 can not do training, all training will fail */
2522 if (!(params->base.dramtype == LPDDR4 && fn == 2)) {
2523 for (channel = 0; channel < 2; channel++) {
2524 if (!(params->ch[channel].cap_info.col))
2525 continue;
2526 ret = data_training(dram, channel, params,
2527 PI_FULL_TRAINING);
2528 if (ret)
2529 printf("%s: channel %d training failed!\n",
2530 __func__, channel);
2531 else
2532 debug("%s: channel %d training pass\n",
2533 __func__, channel);
2534 }
2535 }
2536
2537 return 0;
2538 }
2539
lpddr4_set_rate(struct dram_info * dram,struct rk3399_sdram_params * params)2540 static int lpddr4_set_rate(struct dram_info *dram,
2541 struct rk3399_sdram_params *params)
2542 {
2543 u32 ctl_fn;
2544 u32 phy_fn;
2545
2546 for (ctl_fn = 0; ctl_fn < 2; ctl_fn++) {
2547 phy_fn = lpddr4_get_phy_fn(params, ctl_fn);
2548
2549 lpddr4_set_phy(dram, params, phy_fn, &dfs_cfgs_lpddr4[ctl_fn]);
2550 lpddr4_set_ctl(dram, params, ctl_fn,
2551 dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq);
2552
2553 printf("%s: change freq to %d mhz %d, %d\n", __func__,
2554 dfs_cfgs_lpddr4[ctl_fn].base.ddr_freq, ctl_fn, phy_fn);
2555 }
2556
2557 return 0;
2558 }
2559 #endif /* CONFIG_RAM_RK3399_LPDDR4 */
2560
2561 /* CS0,n=1
2562 * CS1,n=2
2563 * CS0 & CS1, n=3
2564 * cs0_cap: MB unit
2565 */
dram_set_cs(const struct chan_info * chan,u32 cs_map,u32 cs0_cap,unsigned char dramtype)2566 static void dram_set_cs(const struct chan_info *chan, u32 cs_map, u32 cs0_cap,
2567 unsigned char dramtype)
2568 {
2569 u32 *denali_ctl = chan->pctl->denali_ctl;
2570 u32 *denali_pi = chan->pi->denali_pi;
2571 struct msch_regs *ddr_msch_regs = chan->msch;
2572
2573 clrsetbits_le32(&denali_ctl[196], 0x3, cs_map);
2574 writel((cs0_cap / 32) | (((4096 - cs0_cap) / 32) << 8),
2575 &ddr_msch_regs->ddrsize);
2576 if (dramtype == LPDDR4) {
2577 if (cs_map == 1)
2578 cs_map = 0x5;
2579 else if (cs_map == 2)
2580 cs_map = 0xa;
2581 else
2582 cs_map = 0xF;
2583 }
2584 /*PI_41 PI_CS_MAP:RW:24:4*/
2585 clrsetbits_le32(&denali_pi[41],
2586 0xf << 24, cs_map << 24);
2587 if (cs_map == 1 && dramtype == DDR3)
2588 writel(0x2EC7FFFF, &denali_pi[34]);
2589 }
2590
dram_set_bw(const struct chan_info * chan,u32 bw)2591 static void dram_set_bw(const struct chan_info *chan, u32 bw)
2592 {
2593 u32 *denali_ctl = chan->pctl->denali_ctl;
2594
2595 if (bw == 2)
2596 clrbits_le32(&denali_ctl[196], 1 << 16);
2597 else
2598 setbits_le32(&denali_ctl[196], 1 << 16);
2599 }
2600
dram_set_max_col(const struct chan_info * chan,u32 bw,u32 * pcol)2601 static void dram_set_max_col(const struct chan_info *chan, u32 bw, u32 *pcol)
2602 {
2603 u32 *denali_ctl = chan->pctl->denali_ctl;
2604 struct msch_regs *ddr_msch_regs = chan->msch;
2605 u32 *denali_pi = chan->pi->denali_pi;
2606 u32 ddrconfig;
2607
2608 clrbits_le32(&denali_ctl[191], 0xf);
2609 clrsetbits_le32(&denali_ctl[190],
2610 (7 << 24),
2611 ((16 - ((bw == 2) ? 14 : 15)) << 24));
2612 /*PI_199 PI_COL_DIFF:RW:0:4*/
2613 clrbits_le32(&denali_pi[199], 0xf);
2614 /*PI_155 PI_ROW_DIFF:RW:24:3*/
2615 clrsetbits_le32(&denali_pi[155],
2616 (7 << 24),
2617 ((16 - 12) << 24));
2618 ddrconfig = (bw == 2) ? 3 : 2;
2619 writel(ddrconfig | (ddrconfig << 8), &ddr_msch_regs->ddrconf);
2620 /* set max cs0 size */
2621 writel((4096 / 32) | ((0 / 32) << 8),
2622 &ddr_msch_regs->ddrsize);
2623
2624 *pcol = 12;
2625 }
2626
dram_set_max_bank(const struct chan_info * chan,u32 bw,u32 * pbank,u32 * pcol)2627 static void dram_set_max_bank(const struct chan_info *chan, u32 bw, u32 *pbank,
2628 u32 *pcol)
2629 {
2630 u32 *denali_ctl = chan->pctl->denali_ctl;
2631 u32 *denali_pi = chan->pi->denali_pi;
2632
2633 clrbits_le32(&denali_ctl[191], 0xf);
2634 clrbits_le32(&denali_ctl[190], (3 << 16));
2635 /*PI_199 PI_COL_DIFF:RW:0:4*/
2636 clrbits_le32(&denali_pi[199], 0xf);
2637 /*PI_155 PI_BANK_DIFF:RW:16:2*/
2638 clrbits_le32(&denali_pi[155], (3 << 16));
2639
2640 *pbank = 3;
2641 *pcol = 12;
2642 }
2643
dram_set_max_row(const struct chan_info * chan,u32 bw,u32 * prow,u32 * pbank,u32 * pcol)2644 static void dram_set_max_row(const struct chan_info *chan, u32 bw, u32 *prow,
2645 u32 *pbank, u32 *pcol)
2646 {
2647 u32 *denali_ctl = chan->pctl->denali_ctl;
2648 u32 *denali_pi = chan->pi->denali_pi;
2649 struct msch_regs *ddr_msch_regs = chan->msch;
2650
2651 clrsetbits_le32(&denali_ctl[191], 0xf, 12 - 10);
2652 clrbits_le32(&denali_ctl[190],
2653 (0x3 << 16) | (0x7 << 24));
2654 /*PI_199 PI_COL_DIFF:RW:0:4*/
2655 clrsetbits_le32(&denali_pi[199], 0xf, 12 - 10);
2656 /*PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2*/
2657 clrbits_le32(&denali_pi[155],
2658 (0x3 << 16) | (0x7 << 24));
2659 writel(1 | (1 << 8), &ddr_msch_regs->ddrconf);
2660 /* set max cs0 size */
2661 writel((4096 / 32) | ((0 / 32) << 8),
2662 &ddr_msch_regs->ddrsize);
2663
2664 *prow = 16;
2665 *pbank = 3;
2666 *pcol = (bw == 2) ? 10 : 11;
2667 }
2668
dram_detect_cap(struct dram_info * dram,struct rk3399_sdram_params * params,unsigned char channel)2669 static u64 dram_detect_cap(struct dram_info *dram,
2670 struct rk3399_sdram_params *params,
2671 unsigned char channel)
2672 {
2673 const struct chan_info *chan = &dram->chan[channel];
2674 struct sdram_cap_info *cap_info = ¶ms->ch[channel].cap_info;
2675 u32 bw;
2676 u32 col_tmp;
2677 u32 bk_tmp;
2678 u32 row_tmp;
2679 u32 cs0_cap;
2680 u32 training_flag;
2681 u32 ddrconfig;
2682
2683 /* detect bw */
2684 bw = 2;
2685 if (params->base.dramtype != LPDDR4) {
2686 dram_set_bw(chan, bw);
2687 cap_info->bw = bw;
2688 if (data_training(dram, channel, params,
2689 PI_READ_GATE_TRAINING)) {
2690 bw = 1;
2691 dram_set_bw(chan, 1);
2692 cap_info->bw = bw;
2693 if (data_training(dram, channel, params,
2694 PI_READ_GATE_TRAINING)) {
2695 printf("16bit error!!!\n");
2696 goto error;
2697 }
2698 }
2699 }
2700 /*
2701 * LPDDR3 CA training msut be trigger before other training.
2702 * DDR3 is not have CA training.
2703 */
2704 if (params->base.dramtype == LPDDR3)
2705 training_flag = PI_WRITE_LEVELING;
2706 else
2707 training_flag = PI_FULL_TRAINING;
2708
2709 if (params->base.dramtype != LPDDR4) {
2710 if (data_training(dram, channel, params, training_flag)) {
2711 printf("full training error!!!\n");
2712 goto error;
2713 }
2714 }
2715
2716 /* detect col */
2717 dram_set_max_col(chan, bw, &col_tmp);
2718 if (sdram_detect_col(cap_info, col_tmp) != 0)
2719 goto error;
2720
2721 /* detect bank */
2722 dram_set_max_bank(chan, bw, &bk_tmp, &col_tmp);
2723 sdram_detect_bank(cap_info, col_tmp, bk_tmp);
2724
2725 /* detect row */
2726 dram_set_max_row(chan, bw, &row_tmp, &bk_tmp, &col_tmp);
2727 if (sdram_detect_row(cap_info, col_tmp, bk_tmp, row_tmp) != 0)
2728 goto error;
2729
2730 /* detect row_3_4 */
2731 sdram_detect_row_3_4(cap_info, col_tmp, bk_tmp);
2732
2733 /* set ddrconfig */
2734 cs0_cap = (1 << (cap_info->cs0_row + cap_info->col + cap_info->bk +
2735 cap_info->bw - 20));
2736 if (cap_info->row_3_4)
2737 cs0_cap = cs0_cap * 3 / 4;
2738
2739 cap_info->cs1_row = cap_info->cs0_row;
2740 set_memory_map(chan, channel, params);
2741 ddrconfig = calculate_ddrconfig(params, channel);
2742 if (-1 == ddrconfig)
2743 goto error;
2744 set_ddrconfig(chan, params, channel,
2745 cap_info->ddrconfig);
2746
2747 /* detect cs1 row */
2748 sdram_detect_cs1_row(cap_info, params->base.dramtype);
2749
2750 /* detect die bw */
2751 sdram_detect_dbw(cap_info, params->base.dramtype);
2752
2753 return 0;
2754 error:
2755 return (-1);
2756 }
2757
calculate_stride(struct rk3399_sdram_params * params)2758 static unsigned char calculate_stride(struct rk3399_sdram_params *params)
2759 {
2760 unsigned int gstride_type;
2761 unsigned int channel;
2762 unsigned int chinfo = 0;
2763 unsigned int cap = 0;
2764 unsigned int stride = -1;
2765 unsigned int ch_cap[2] = {0, 0};
2766
2767 gstride_type = STRIDE_256B;
2768
2769 for (channel = 0; channel < 2; channel++) {
2770 unsigned int cs0_cap = 0;
2771 unsigned int cs1_cap = 0;
2772 struct sdram_cap_info *cap_info =
2773 ¶ms->ch[channel].cap_info;
2774
2775 if (cap_info->col == 0)
2776 continue;
2777
2778 cs0_cap = (1 << (cap_info->cs0_row + cap_info->col +
2779 cap_info->bk + cap_info->bw - 20));
2780 if (cap_info->rank > 1)
2781 cs1_cap = cs0_cap >> (cap_info->cs0_row
2782 - cap_info->cs1_row);
2783 if (cap_info->row_3_4) {
2784 cs0_cap = cs0_cap * 3 / 4;
2785 cs1_cap = cs1_cap * 3 / 4;
2786 }
2787 ch_cap[channel] = cs0_cap + cs1_cap;
2788 chinfo |= 1 << channel;
2789 }
2790
2791 cap = ch_cap[0] + ch_cap[1];
2792 if (params->base.num_channels == 1) {
2793 if (chinfo & 1) /* channel a only */
2794 stride = 0x17;
2795 else /* channel b only */
2796 stride = 0x18;
2797 } else {/* 2 channel */
2798 if (ch_cap[0] == ch_cap[1]) {
2799 /* interleaved */
2800 if (gstride_type == PART_STRIDE) {
2801 /*
2802 * first 64MB no interleaved other 256B interleaved
2803 * if 786M+768M.useful space from 0-1280MB and
2804 * 1536MB-1792MB
2805 * if 1.5G+1.5G(continuous).useful space from 0-2560MB
2806 * and 3072MB-3584MB
2807 */
2808 stride = 0x1F;
2809 } else {
2810 switch (cap) {
2811 /* 512MB */
2812 case 512:
2813 stride = 0;
2814 break;
2815 /* 1GB unstride or 256B stride*/
2816 case 1024:
2817 stride = (gstride_type == UN_STRIDE) ?
2818 0x1 : 0x5;
2819 break;
2820 /*
2821 * 768MB + 768MB same as total 2GB memory
2822 * useful space: 0-768MB 1GB-1792MB
2823 */
2824 case 1536:
2825 /* 2GB unstride or 256B or 512B stride */
2826 case 2048:
2827 stride = (gstride_type == UN_STRIDE) ?
2828 0x2 :
2829 ((gstride_type == STRIDE_512B) ?
2830 0xA : 0x9);
2831 break;
2832 /* 1536MB + 1536MB */
2833 case 3072:
2834 stride = (gstride_type == UN_STRIDE) ?
2835 0x3 :
2836 ((gstride_type == STRIDE_512B) ?
2837 0x12 : 0x11);
2838 break;
2839 /* 4GB unstride or 128B,256B,512B,4KB stride */
2840 case 4096:
2841 stride = (gstride_type == UN_STRIDE) ?
2842 0x3 : (0xC + gstride_type);
2843 break;
2844 }
2845 }
2846 }
2847 if (ch_cap[0] == 2048 && ch_cap[1] == 1024) {
2848 /* 2GB + 1GB */
2849 stride = (gstride_type == UN_STRIDE) ? 0x3 : 0x19;
2850 }
2851 /*
2852 * remain two channel capability not equal OR capability
2853 * power function of 2
2854 */
2855 if (stride == (-1)) {
2856 switch ((ch_cap[0] > ch_cap[1]) ?
2857 ch_cap[0] : ch_cap[1]) {
2858 case 256: /* 256MB + 128MB */
2859 stride = 0;
2860 break;
2861 case 512: /* 512MB + 256MB */
2862 stride = 1;
2863 break;
2864 case 1024:/* 1GB + 128MB/256MB/384MB/512MB/768MB */
2865 stride = 2;
2866 break;
2867 case 2048: /* 2GB + 128MB/256MB/384MB/512MB/768MB/1GB */
2868 stride = 3;
2869 break;
2870 default:
2871 break;
2872 }
2873 }
2874 if (stride == (-1))
2875 goto error;
2876 }
2877 switch (stride) {
2878 case 0xc:
2879 printf("128B stride\n");
2880 break;
2881 case 5:
2882 case 9:
2883 case 0xd:
2884 case 0x11:
2885 case 0x19:
2886 printf("256B stride\n");
2887 break;
2888 case 0xa:
2889 case 0xe:
2890 case 0x12:
2891 printf("512B stride\n");
2892 break;
2893 case 0xf:
2894 printf("4K stride\n");
2895 break;
2896 case 0x1f:
2897 printf("32MB + 256B stride\n");
2898 break;
2899 default:
2900 printf("no stride\n");
2901 }
2902
2903 sdram_print_stride(stride);
2904
2905 return stride;
2906 error:
2907 printf("Cap not support!\n");
2908 return (-1);
2909 }
2910
clear_channel_params(struct rk3399_sdram_params * params,u8 channel)2911 static void clear_channel_params(struct rk3399_sdram_params *params, u8 channel)
2912 {
2913 params->ch[channel].cap_info.rank = 0;
2914 params->ch[channel].cap_info.col = 0;
2915 params->ch[channel].cap_info.bk = 0;
2916 params->ch[channel].cap_info.bw = 32;
2917 params->ch[channel].cap_info.dbw = 32;
2918 params->ch[channel].cap_info.row_3_4 = 0;
2919 params->ch[channel].cap_info.cs0_row = 0;
2920 params->ch[channel].cap_info.cs1_row = 0;
2921 params->ch[channel].cap_info.ddrconfig = 0;
2922 }
2923
sdram_init(struct dram_info * dram,struct rk3399_sdram_params * params)2924 static int sdram_init(struct dram_info *dram,
2925 struct rk3399_sdram_params *params)
2926 {
2927 unsigned char dramtype = params->base.dramtype;
2928 unsigned int ddr_freq = params->base.ddr_freq;
2929 int channel, ch, rank;
2930 u32 tmp, ret;
2931
2932 debug("Starting SDRAM initialization...\n");
2933
2934 if ((dramtype == DDR3 && ddr_freq > 933) ||
2935 (dramtype == LPDDR3 && ddr_freq > 933) ||
2936 (dramtype == LPDDR4 && ddr_freq > 800)) {
2937 debug("SDRAM frequency is to high!");
2938 return -E2BIG;
2939 }
2940
2941 /* detect rank */
2942 for (ch = 0; ch < 2; ch++) {
2943 params->ch[ch].cap_info.rank = 2;
2944 for (rank = 2; rank != 0; rank--) {
2945 for (channel = 0; channel < 2; channel++) {
2946 const struct chan_info *chan =
2947 &dram->chan[channel];
2948 struct rk3399_cru *cru = dram->cru;
2949 struct rk3399_ddr_publ_regs *publ = chan->publ;
2950
2951 phy_pctrl_reset(cru, channel);
2952 phy_dll_bypass_set(publ, ddr_freq);
2953 pctl_cfg(dram, chan, channel, params);
2954 }
2955
2956 /* start to trigger initialization */
2957 pctl_start(dram, params, 3);
2958
2959 /* LPDDR2/LPDDR3 need to wait DAI complete, max 10us */
2960 if (dramtype == LPDDR3)
2961 udelay(10);
2962
2963 tmp = (rank == 2) ? 3 : 1;
2964 dram_set_cs(&dram->chan[ch], tmp, 2048,
2965 params->base.dramtype);
2966 params->ch[ch].cap_info.rank = rank;
2967
2968 ret = dram->ops->data_training_first(dram, ch,
2969 rank, params);
2970 if (!ret) {
2971 debug("%s: data trained for rank %d, ch %d\n",
2972 __func__, rank, ch);
2973 break;
2974 }
2975 }
2976 /* Computed rank with associated channel number */
2977 params->ch[ch].cap_info.rank = rank;
2978 }
2979
2980 params->base.num_channels = 0;
2981 for (channel = 0; channel < 2; channel++) {
2982 const struct chan_info *chan = &dram->chan[channel];
2983 struct sdram_cap_info *cap_info =
2984 ¶ms->ch[channel].cap_info;
2985
2986 if (cap_info->rank == 0) {
2987 clear_channel_params(params, 1);
2988 continue;
2989 } else {
2990 params->base.num_channels++;
2991 }
2992
2993 printf("Channel ");
2994 printf(channel ? "1: " : "0: ");
2995
2996 if (channel == 0)
2997 set_ddr_stride(dram->pmusgrf, 0x17);
2998 else
2999 set_ddr_stride(dram->pmusgrf, 0x18);
3000
3001 if (dram_detect_cap(dram, params, channel)) {
3002 printf("Cap error!\n");
3003 continue;
3004 }
3005
3006 sdram_print_ddr_info(cap_info, ¶ms->base);
3007 set_memory_map(chan, channel, params);
3008 cap_info->ddrconfig =
3009 calculate_ddrconfig(params, channel);
3010 if (-1 == cap_info->ddrconfig) {
3011 printf("no ddrconfig find, Cap not support!\n");
3012 continue;
3013 }
3014 set_ddrconfig(chan, params, channel, cap_info->ddrconfig);
3015 set_cap_relate_config(chan, params, channel);
3016 }
3017
3018 if (params->base.num_channels == 0) {
3019 printf("%s: ", __func__);
3020 sdram_print_dram_type(params->base.dramtype);
3021 printf(" - %dMHz failed!\n", params->base.ddr_freq);
3022 return -EINVAL;
3023 }
3024
3025 params->base.stride = calculate_stride(params);
3026 dram_all_config(dram, params);
3027
3028 dram->ops->set_rate_index(dram, params);
3029
3030 debug("Finish SDRAM initialization...\n");
3031 return 0;
3032 }
3033
rk3399_dmc_ofdata_to_platdata(struct udevice * dev)3034 static int rk3399_dmc_ofdata_to_platdata(struct udevice *dev)
3035 {
3036 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
3037 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
3038 int ret;
3039
3040 ret = dev_read_u32_array(dev, "rockchip,sdram-params",
3041 (u32 *)&plat->sdram_params,
3042 sizeof(plat->sdram_params) / sizeof(u32));
3043 if (ret) {
3044 printf("%s: Cannot read rockchip,sdram-params %d\n",
3045 __func__, ret);
3046 return ret;
3047 }
3048 ret = regmap_init_mem(dev_ofnode(dev), &plat->map);
3049 if (ret)
3050 printf("%s: regmap failed %d\n", __func__, ret);
3051
3052 #endif
3053 return 0;
3054 }
3055
3056 #if CONFIG_IS_ENABLED(OF_PLATDATA)
conv_of_platdata(struct udevice * dev)3057 static int conv_of_platdata(struct udevice *dev)
3058 {
3059 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
3060 struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
3061 int ret;
3062
3063 ret = regmap_init_mem_platdata(dev, dtplat->reg,
3064 ARRAY_SIZE(dtplat->reg) / 2,
3065 &plat->map);
3066 if (ret)
3067 return ret;
3068
3069 return 0;
3070 }
3071 #endif
3072
3073 static const struct sdram_rk3399_ops rk3399_ops = {
3074 #if !defined(CONFIG_RAM_RK3399_LPDDR4)
3075 .data_training_first = data_training_first,
3076 .set_rate_index = switch_to_phy_index1,
3077 .modify_param = modify_param,
3078 .get_phy_index_params = get_phy_index_params,
3079 #else
3080 .data_training_first = lpddr4_mr_detect,
3081 .set_rate_index = lpddr4_set_rate,
3082 .modify_param = lpddr4_modify_param,
3083 .get_phy_index_params = lpddr4_get_phy_index_params,
3084 #endif
3085 };
3086
rk3399_dmc_init(struct udevice * dev)3087 static int rk3399_dmc_init(struct udevice *dev)
3088 {
3089 struct dram_info *priv = dev_get_priv(dev);
3090 struct rockchip_dmc_plat *plat = dev_get_platdata(dev);
3091 int ret;
3092 #if !CONFIG_IS_ENABLED(OF_PLATDATA)
3093 struct rk3399_sdram_params *params = &plat->sdram_params;
3094 #else
3095 struct dtd_rockchip_rk3399_dmc *dtplat = &plat->dtplat;
3096 struct rk3399_sdram_params *params =
3097 (void *)dtplat->rockchip_sdram_params;
3098
3099 ret = conv_of_platdata(dev);
3100 if (ret)
3101 return ret;
3102 #endif
3103
3104 priv->ops = &rk3399_ops;
3105 priv->cic = syscon_get_first_range(ROCKCHIP_SYSCON_CIC);
3106 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
3107 priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU);
3108 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
3109 priv->pmusgrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUSGRF);
3110 priv->pmucru = rockchip_get_pmucru();
3111 priv->cru = rockchip_get_cru();
3112 priv->chan[0].pctl = regmap_get_range(plat->map, 0);
3113 priv->chan[0].pi = regmap_get_range(plat->map, 1);
3114 priv->chan[0].publ = regmap_get_range(plat->map, 2);
3115 priv->chan[0].msch = regmap_get_range(plat->map, 3);
3116 priv->chan[1].pctl = regmap_get_range(plat->map, 4);
3117 priv->chan[1].pi = regmap_get_range(plat->map, 5);
3118 priv->chan[1].publ = regmap_get_range(plat->map, 6);
3119 priv->chan[1].msch = regmap_get_range(plat->map, 7);
3120
3121 debug("con reg %p %p %p %p %p %p %p %p\n",
3122 priv->chan[0].pctl, priv->chan[0].pi,
3123 priv->chan[0].publ, priv->chan[0].msch,
3124 priv->chan[1].pctl, priv->chan[1].pi,
3125 priv->chan[1].publ, priv->chan[1].msch);
3126 debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p, pmu %p\n", priv->cru,
3127 priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru, priv->pmu);
3128
3129 #if CONFIG_IS_ENABLED(OF_PLATDATA)
3130 ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk);
3131 #else
3132 ret = clk_get_by_index(dev, 0, &priv->ddr_clk);
3133 #endif
3134 if (ret) {
3135 printf("%s clk get failed %d\n", __func__, ret);
3136 return ret;
3137 }
3138
3139 ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz);
3140 if (ret < 0) {
3141 printf("%s clk set failed %d\n", __func__, ret);
3142 return ret;
3143 }
3144
3145 ret = sdram_init(priv, params);
3146 if (ret < 0) {
3147 printf("%s DRAM init failed %d\n", __func__, ret);
3148 return ret;
3149 }
3150
3151 return 0;
3152 }
3153 #endif
3154
rk3399_dmc_probe(struct udevice * dev)3155 static int rk3399_dmc_probe(struct udevice *dev)
3156 {
3157 #if defined(CONFIG_TPL_BUILD) || \
3158 (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
3159 if (rk3399_dmc_init(dev))
3160 return 0;
3161 #else
3162 struct dram_info *priv = dev_get_priv(dev);
3163
3164 priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
3165 debug("%s: pmugrf = %p\n", __func__, priv->pmugrf);
3166 priv->info.base = CONFIG_SYS_SDRAM_BASE;
3167 priv->info.size =
3168 rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
3169 #endif
3170 return 0;
3171 }
3172
rk3399_dmc_get_info(struct udevice * dev,struct ram_info * info)3173 static int rk3399_dmc_get_info(struct udevice *dev, struct ram_info *info)
3174 {
3175 struct dram_info *priv = dev_get_priv(dev);
3176
3177 *info = priv->info;
3178
3179 return 0;
3180 }
3181
3182 static struct ram_ops rk3399_dmc_ops = {
3183 .get_info = rk3399_dmc_get_info,
3184 };
3185
3186 static const struct udevice_id rk3399_dmc_ids[] = {
3187 { .compatible = "rockchip,rk3399-dmc" },
3188 { }
3189 };
3190
3191 U_BOOT_DRIVER(dmc_rk3399) = {
3192 .name = "rockchip_rk3399_dmc",
3193 .id = UCLASS_RAM,
3194 .of_match = rk3399_dmc_ids,
3195 .ops = &rk3399_dmc_ops,
3196 #if defined(CONFIG_TPL_BUILD) || \
3197 (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
3198 .ofdata_to_platdata = rk3399_dmc_ofdata_to_platdata,
3199 #endif
3200 .probe = rk3399_dmc_probe,
3201 .priv_auto_alloc_size = sizeof(struct dram_info),
3202 #if defined(CONFIG_TPL_BUILD) || \
3203 (!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
3204 .platdata_auto_alloc_size = sizeof(struct rockchip_dmc_plat),
3205 #endif
3206 };
3207