| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516dv300/ |
| D | ddr_training_custom.c | 71 relate_reg->custom.phy0_age_compst_en = ddr_read(DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_training_save_reg_custom()
72 …ddr_write((relate_reg->custom.phy0_age_compst_en & 0x7fffffff), DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSC… in ddr_training_save_reg_custom()
82 ddr_write(relate_reg->custom.phy0_age_compst_en, DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_training_restore_reg_custom()
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| D | ddr_training_custom.h | 108 unsigned int phy0_age_compst_en; member
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516av300/ |
| D | ddr_training_custom.c | 71 relate_reg->custom.phy0_age_compst_en = ddr_read(DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_training_save_reg_custom()
72 …ddr_write((relate_reg->custom.phy0_age_compst_en & 0x7fffffff), DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSC… in ddr_training_save_reg_custom()
82 ddr_write(relate_reg->custom.phy0_age_compst_en, DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_training_restore_reg_custom()
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| D | ddr_training_custom.h | 108 unsigned int phy0_age_compst_en; member
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516cv500/ |
| D | ddr_training_custom.c | 71 relate_reg->custom.phy0_age_compst_en = ddr_read(DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_training_save_reg_custom()
72 …ddr_write((relate_reg->custom.phy0_age_compst_en & 0x7fffffff), DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSC… in ddr_training_save_reg_custom()
82 ddr_write(relate_reg->custom.phy0_age_compst_en, DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_training_restore_reg_custom()
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| D | ddr_training_custom.h | 108 unsigned int phy0_age_compst_en; member
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516dv200/ |
| D | ddr_training_custom.c | 56 reg->custom.phy0_age_compst_en = ddr_read(DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_cmd_site_save()
57 ddr_write((reg->custom.phy0_age_compst_en & 0x7fffffff), DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_cmd_site_save()
77 ddr_write(reg->custom.phy0_age_compst_en, DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_cmd_site_restore()
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| D | ddr_training_custom.h | 111 unsigned int phy0_age_compst_en; member
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516ev200/ |
| D | ddr_training_custom.c | 56 reg->custom.phy0_age_compst_en = ddr_read(DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_cmd_site_save()
57 ddr_write((reg->custom.phy0_age_compst_en & 0x7fffffff), DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_cmd_site_save()
77 ddr_write(reg->custom.phy0_age_compst_en, DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_cmd_site_restore()
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| D | ddr_training_custom.h | 111 unsigned int phy0_age_compst_en; member
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3518ev300/ |
| D | ddr_training_custom.c | 56 reg->custom.phy0_age_compst_en = ddr_read(DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_cmd_site_save()
57 ddr_write((reg->custom.phy0_age_compst_en & 0x7fffffff), DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_cmd_site_save()
77 ddr_write(reg->custom.phy0_age_compst_en, DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_cmd_site_restore()
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| D | ddr_training_custom.h | 111 unsigned int phy0_age_compst_en; member
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3516ev300/ |
| D | ddr_training_custom.c | 56 reg->custom.phy0_age_compst_en = ddr_read(DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_cmd_site_save()
57 ddr_write((reg->custom.phy0_age_compst_en & 0x7fffffff), DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_cmd_site_save()
77 ddr_write(reg->custom.phy0_age_compst_en, DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_cmd_site_restore()
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| D | ddr_training_custom.h | 111 unsigned int phy0_age_compst_en; member
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3535av100/ |
| D | ddr_training_custom.c | 93 relate_reg->custom.phy0_age_compst_en = ddr_read(DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_boot_cmd_save()
94 ddr_write((relate_reg->custom.phy0_age_compst_en & (~(0x1 << PHY_CFG_RX_AGE_COMPST_EN_BIT))), in ddr_boot_cmd_save()
117 ddr_write(relate_reg->custom.phy0_age_compst_en, DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_boot_cmd_restore()
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| D | ddr_training_custom.h | 106 unsigned int phy0_age_compst_en; member
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3520dv500/ |
| D | ddr_training_custom.c | 91 relate_reg->custom.phy0_age_compst_en = ddr_read(DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_boot_cmd_save()
92 ddr_write((relate_reg->custom.phy0_age_compst_en & (~(0x1 << PHY_CFG_RX_AGE_COMPST_EN_BIT))), in ddr_boot_cmd_save()
115 ddr_write(relate_reg->custom.phy0_age_compst_en, DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_boot_cmd_restore()
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| D | ddr_training_custom.h | 104 unsigned int phy0_age_compst_en; member
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3521dv200/ |
| D | ddr_training_custom.c | 91 relate_reg->custom.phy0_age_compst_en = ddr_read(DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_boot_cmd_save()
92 ddr_write((relate_reg->custom.phy0_age_compst_en & (~(0x1 << PHY_CFG_RX_AGE_COMPST_EN_BIT))), in ddr_boot_cmd_save()
115 ddr_write(relate_reg->custom.phy0_age_compst_en, DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_boot_cmd_restore()
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| D | ddr_training_custom.h | 104 unsigned int phy0_age_compst_en; member
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/hisilicon/hi3531dv200/ |
| D | ddr_training_custom.c | 93 relate_reg->custom.phy0_age_compst_en = ddr_read(DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_boot_cmd_save()
94 ddr_write((relate_reg->custom.phy0_age_compst_en & (~(0x1 << PHY_CFG_RX_AGE_COMPST_EN_BIT))), in ddr_boot_cmd_save()
117 ddr_write(relate_reg->custom.phy0_age_compst_en, DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_boot_cmd_restore()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516ev200/ |
| D | lowlevel_init_v300.c | 328 reg->custom.phy0_age_compst_en = readl(DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_boot_prepare()
329 writel((reg->custom.phy0_age_compst_en & 0x7fffffff), in ddr_boot_prepare()
354 writel(reg->custom.phy0_age_compst_en, DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_boot_restore()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516ev300/ |
| D | lowlevel_init_v300.c | 324 reg->custom.phy0_age_compst_en = readl(DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_boot_prepare()
325 writel((reg->custom.phy0_age_compst_en & 0x7fffffff), in ddr_boot_prepare()
350 writel(reg->custom.phy0_age_compst_en, DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_boot_restore()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3516dv200/ |
| D | lowlevel_init_v300.c | 327 reg->custom.phy0_age_compst_en = readl(DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_boot_prepare()
328 writel((reg->custom.phy0_age_compst_en & 0x7fffffff), in ddr_boot_prepare()
353 writel(reg->custom.phy0_age_compst_en, DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_boot_restore()
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| /third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/hi3518ev300/ |
| D | lowlevel_init_v300.c | 329 reg->custom.phy0_age_compst_en = readl(DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_boot_prepare()
330 writel((reg->custom.phy0_age_compst_en & 0x7fffffff), in ddr_boot_prepare()
355 writel(reg->custom.phy0_age_compst_en, DDR_REG_BASE_PHY0 + DDR_PHY_PHYRSCTRL); in ddr_boot_restore()
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