1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms of the GNU General Public License as published by the 6 * Free Software Foundation; either version 2 of the License, or (at your 7 * option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 * 17 */ 18 19 #ifndef DDR_TRAINING_CUSTOM_H 20 #define DDR_TRAINING_CUSTOM_H 21 22 /* config DDRC, PHY, DDRT typte */ 23 #define DDR_DDRC_V520_CONFIG 24 #define DDR_PHY_T28_CONFIG 25 #define DDR_DDRT_T12_V100_CONFIG 26 27 /* config special item */ 28 #define DDR_VREF_TRAINING_CONFIG 29 #define DDR_VREF_WITHOUT_BDL_CONFIG 30 31 #define DDR_WL_TRAINING_DISABLE 32 #define DDR_GATE_TRAINING_DISABLE 33 #define DDR_TRAINING_UART_DISABLE 34 35 /* Disable write dm 36 #define DDR_WRITE_DM_DISABLE */ 37 38 #define DDR_PHY_NUM 1 /* phy number */ 39 40 #define DDR_DMC_PER_PHY_MAX 2 /* dmc number per phy max */ 41 42 #define DDR_AXI_SWITCH_NUM 4 /* ddr training axi switch number */ 43 44 /* config DDRC, PHY, DDRT base address */ 45 /* [CUSTOM] DDR PHY0 base register */ 46 #define DDR_REG_BASE_PHY0 0x1206c000 47 /* [CUSTOM] DDR PHY1 base register 48 #define DDR_REG_BASE_PHY1 0x1206e000 */ 49 /* [CUSTOM] DDR DMC0 base register */ 50 #define DDR_REG_BASE_DMC0 0x12068000 51 /* [CUSTOM] DDR DMC1 base register */ 52 #define DDR_REG_BASE_DMC1 0x12069000 53 54 #ifdef DDR_REG_BASE_PHY1 55 /* [CUSTOM] DDR DMC2 base register */ 56 #define DDR_REG_BASE_DMC2 0x1206a000 57 /* [CUSTOM] DDR DMC3 base register */ 58 #define DDR_REG_BASE_DMC3 0x1206b000 59 #endif 60 61 /* [CUSTOM] DDR DDRT base register */ 62 #define DDR_REG_BASE_DDRT 0x11250000 63 /* [CUSTOM] DDR training item system control */ 64 #define DDR_REG_BASE_SYSCTRL 0x12020000 65 #define DDR_REG_BASE_AXI 0x12060000 66 /* Serial Configuration */ 67 #define DDR_REG_BASE_UART0 0x120A0000 68 69 /* config offset address */ 70 /* Assume sysctrl offset address for DDR training as follows, 71 if not please define. */ 72 /* [CUSTOM] ddrt reversed data */ 73 #define SYSCTRL_DDRT_PATTERN 0xa8 74 /* [CUSTOM] PHY2 ddrt reversed data 75 #define SYSCTRL_DDRT_PATTERN_SEC 0xac */ 76 /* [CUSTOM] ddr training item */ 77 #define SYSCTRL_DDR_TRAINING_CFG 0xa0 78 #define SYSCTRL_DDR_TRAINING_CFG_SEC 0xa4 79 /* [CUSTOM] ddr training version flag */ 80 #define SYSCTRL_DDR_TRAINING_VERSION_FLAG 0xac 81 /* [CUSTOM] ddr training stat */ 82 #define SYSCTRL_DDR_TRAINING_STAT 0x9c 83 84 /* [CUSTOM] ddr hw training item */ 85 #define SYSCTRL_DDR_HW_PHY0_RANK0 0x90 86 #define SYSCTRL_DDR_HW_PHY0_RANK1 0x94 87 #if 0 88 /* PHY1 hw training item */ 89 #define SYSCTRL_DDR_HW_PHY1_RANK0 0x98 90 #define SYSCTRL_DDR_HW_PHY1_RANK1 0x9c 91 #endif 92 93 /* config other special */ 94 /* [CUSTOM] DDR training start address. MEM_BASE_DDR */ 95 #define DDRT_CFG_BASE_ADDR 0x80000000 96 /* [CUSTOM] SRAM start address. 97 NOTE: Makefile will parse it, plase define it as Hex. eg: 0xFFFF0C00 */ 98 #define DDR_TRAINING_RUN_STACK 0x04010c00 99 100 #define DDR_RELATE_REG_DECLARE 101 #define DDR_TRAINING_SAVE_REG_FUNC(relate_reg, mask) \ 102 ddr_training_save_reg_custom(relate_reg, mask) 103 104 #define DDR_TRAINING_RESTORE_REG_FUNC(relate_reg) \ 105 ddr_training_restore_reg_custom(relate_reg) 106 107 struct tr_custom_reg { 108 unsigned int phy0_age_compst_en; 109 unsigned int phy1_age_compst_en; 110 }; 111 void ddr_training_save_reg_custom(void *relate_reg, unsigned int mask); 112 void ddr_training_restore_reg_custom(void *relate_reg); 113 #endif /* DDR_TRAINING_CUSTOM_H */ 114