| /third_party/uboot/u-boot-2020.01/drivers/clk/rockchip/ |
| D | clk_pll.c | 182 void __iomem *base, ulong pll_id, in rk3036_pll_set_rate() argument
250 void __iomem *base, ulong pll_id) in rk3036_pll_get_rate() argument
299 ulong pll_id) in rockchip_pll_get_rate() argument
306 rate = rk3036_pll_get_rate(pll, base, pll_id); in rockchip_pll_get_rate()
310 rate = rk3036_pll_get_rate(pll, base, pll_id); in rockchip_pll_get_rate()
314 __func__, pll_id); in rockchip_pll_get_rate()
320 void __iomem *base, ulong pll_id, in rockchip_pll_set_rate() argument
325 if (rockchip_pll_get_rate(pll, base, pll_id) == drate) in rockchip_pll_set_rate()
331 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); in rockchip_pll_set_rate()
335 ret = rk3036_pll_set_rate(pll, base, pll_id, drate); in rockchip_pll_set_rate()
[all …]
|
| D | clk_px30.c | 90 enum px30_pll_id pll_id);
201 enum px30_pll_id pll_id, in rkclk_set_pll() argument
227 rk_clrsetreg(mode, pll_mode_mask[pll_id], in rkclk_set_pll()
228 PLLMUX_FROM_XIN24M << pll_mode_shift[pll_id]); in rkclk_set_pll()
249 rk_clrsetreg(mode, pll_mode_mask[pll_id], in rkclk_set_pll()
250 PLLMUX_FROM_PLL << pll_mode_shift[pll_id]); in rkclk_set_pll()
256 enum px30_pll_id pll_id) in rkclk_pll_get_rate() argument
262 shift = pll_mode_shift[pll_id]; in rkclk_pll_get_rate()
263 mask = pll_mode_mask[pll_id]; in rkclk_pll_get_rate()
1095 enum px30_pll_id pll_id) in px30_clk_get_pll_rate() argument
[all …]
|
| D | clk_rk3036.c | 47 int pll_id = rk_pll_id(clk_id); in rkclk_set_pll() local
48 struct rk3036_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
174 int pll_id = rk_pll_id(clk_id); in rkclk_pll_get_rate() local
175 struct rk3036_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
|
| D | clk_rk322x.c | 44 int pll_id = rk_pll_id(clk_id); in rkclk_set_pll() local
45 struct rk322x_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
175 int pll_id = rk_pll_id(clk_id); in rkclk_pll_get_rate() local
176 struct rk322x_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
|
| D | clk_rk3128.c | 41 int pll_id = rk_pll_id(clk_id); in rkclk_set_pll() local
42 struct rk3128_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
243 int pll_id = rk_pll_id(clk_id); in rkclk_pll_get_rate() local
244 struct rk3128_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
|
| D | clk_rk3188.c | 88 int pll_id = rk_pll_id(clk_id); in rkclk_set_pll() local
89 struct rk3188_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
230 int pll_id = rk_pll_id(clk_id); in rkclk_pll_get_rate() local
231 struct rk3188_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
|
| D | clk_rk3368.c | 62 enum rk3368_pll_id pll_id) in rkclk_pll_get_rate() argument
66 struct rk3368_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
88 static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id, in rkclk_set_pll() argument
91 struct rk3368_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
|
| D | clk_rv1108.c | 68 int pll_id = rv1108_pll_id(clk_id); in rkclk_set_pll() local
69 struct rv1108_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
122 int pll_id = rv1108_pll_id(clk_id); in rkclk_pll_get_rate() local
123 struct rv1108_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
|
| D | clk_rk3288.c | 147 int pll_id = rk_pll_id(clk_id); in rkclk_set_pll() local
148 struct rk3288_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
542 int pll_id = rk_pll_id(clk_id); in rkclk_pll_get_rate() local
543 struct rk3288_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
|
| /third_party/uboot/u-boot-2020.01/drivers/clk/ |
| D | clk_stm32mp1.c | 855 int pll_id) in pll_get_fref_ck() argument
863 selr = readl(priv->base + pll[pll_id].rckxselr); in pll_get_fref_ck()
866 refclk = stm32mp1_clk_get_fixed(priv, pll[pll_id].refclk[src]); in pll_get_fref_ck()
878 int pll_id) in pll_get_fvco() argument
885 cfgr1 = readl(priv->base + pll[pll_id].pllxcfgr1); in pll_get_fvco()
886 fracr = readl(priv->base + pll[pll_id].pllxfracr); in pll_get_fvco()
891 refclk = pll_get_fref_ck(priv, pll_id); in pll_get_fvco()
912 int pll_id, int div_id) in stm32mp1_read_pll_freq() argument
922 cfgr2 = readl(priv->base + pll[pll_id].pllxcfgr2); in stm32mp1_read_pll_freq()
925 dfout = pll_get_fvco(priv, pll_id) / (divy + 1); in stm32mp1_read_pll_freq()
[all …]
|
| /third_party/uboot/u-boot-2020.01/arch/arm/include/asm/arch-rockchip/ |
| D | sdram_px30.h | 71 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) argument
|
| D | sdram_rk3328.h | 51 #define CRU_PLL_CON(pll_id, n) ((pll_id) * 0x20 + (n) * 4) argument
|