1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * (C) Copyright 2017 Rockchip Electronics Co., Ltd
4 */
5
6 #include <common.h>
7 #include <clk-uclass.h>
8 #include <dm.h>
9 #include <errno.h>
10 #include <syscon.h>
11 #include <asm/io.h>
12 #include <asm/arch-rockchip/clock.h>
13 #include <asm/arch-rockchip/cru_rk322x.h>
14 #include <asm/arch-rockchip/hardware.h>
15 #include <dm/lists.h>
16 #include <dt-bindings/clock/rk3228-cru.h>
17 #include <linux/log2.h>
18
19 enum {
20 VCO_MAX_HZ = 3200U * 1000000,
21 VCO_MIN_HZ = 800 * 1000000,
22 OUTPUT_MAX_HZ = 3200U * 1000000,
23 OUTPUT_MIN_HZ = 24 * 1000000,
24 };
25
26 #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1))
27
28 #define PLL_DIVISORS(hz, _refdiv, _postdiv1, _postdiv2) {\
29 .refdiv = _refdiv,\
30 .fbdiv = (u32)((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ), \
31 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
32 _Static_assert(((u64)hz * _refdiv * _postdiv1 * _postdiv2 / OSC_HZ) * \
33 OSC_HZ / (_refdiv * _postdiv1 * _postdiv2) == hz, \
34 #hz "Hz cannot be hit with PLL "\
35 "divisors on line " __stringify(__LINE__));
36
37 /* use integer mode*/
38 static const struct pll_div apll_init_cfg = PLL_DIVISORS(APLL_HZ, 1, 3, 1);
39 static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2, 1);
40
rkclk_set_pll(struct rk322x_cru * cru,enum rk_clk_id clk_id,const struct pll_div * div)41 static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id,
42 const struct pll_div *div)
43 {
44 int pll_id = rk_pll_id(clk_id);
45 struct rk322x_pll *pll = &cru->pll[pll_id];
46
47 /* All PLLs have same VCO and output frequency range restrictions. */
48 uint vco_hz = OSC_HZ / 1000 * div->fbdiv / div->refdiv * 1000;
49 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2;
50
51 debug("PLL at %p: fb=%d, ref=%d, pst1=%d, pst2=%d, vco=%u Hz, output=%u Hz\n",
52 pll, div->fbdiv, div->refdiv, div->postdiv1,
53 div->postdiv2, vco_hz, output_hz);
54 assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ &&
55 output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ);
56
57 /* use integer mode */
58 rk_setreg(&pll->con1, 1 << PLL_DSMPD_SHIFT);
59 /* Power down */
60 rk_setreg(&pll->con1, 1 << PLL_PD_SHIFT);
61
62 rk_clrsetreg(&pll->con0,
63 PLL_POSTDIV1_MASK | PLL_FBDIV_MASK,
64 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv);
65 rk_clrsetreg(&pll->con1, PLL_POSTDIV2_MASK | PLL_REFDIV_MASK,
66 (div->postdiv2 << PLL_POSTDIV2_SHIFT |
67 div->refdiv << PLL_REFDIV_SHIFT));
68
69 /* Power Up */
70 rk_clrreg(&pll->con1, 1 << PLL_PD_SHIFT);
71
72 /* waiting for pll lock */
73 while (readl(&pll->con1) & (1 << PLL_LOCK_STATUS_SHIFT))
74 udelay(1);
75
76 return 0;
77 }
78
rkclk_init(struct rk322x_cru * cru)79 static void rkclk_init(struct rk322x_cru *cru)
80 {
81 u32 aclk_div;
82 u32 hclk_div;
83 u32 pclk_div;
84
85 /* pll enter slow-mode */
86 rk_clrsetreg(&cru->cru_mode_con,
87 GPLL_MODE_MASK | APLL_MODE_MASK,
88 GPLL_MODE_SLOW << GPLL_MODE_SHIFT |
89 APLL_MODE_SLOW << APLL_MODE_SHIFT);
90
91 /* init pll */
92 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg);
93 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg);
94
95 /*
96 * select apll as cpu/core clock pll source and
97 * set up dependent divisors for PERI and ACLK clocks.
98 * core hz : apll = 1:1
99 */
100 aclk_div = APLL_HZ / CORE_ACLK_HZ - 1;
101 assert((aclk_div + 1) * CORE_ACLK_HZ == APLL_HZ && aclk_div < 0x7);
102
103 pclk_div = APLL_HZ / CORE_PERI_HZ - 1;
104 assert((pclk_div + 1) * CORE_PERI_HZ == APLL_HZ && pclk_div < 0xf);
105
106 rk_clrsetreg(&cru->cru_clksel_con[0],
107 CORE_CLK_PLL_SEL_MASK | CORE_DIV_CON_MASK,
108 CORE_CLK_PLL_SEL_APLL << CORE_CLK_PLL_SEL_SHIFT |
109 0 << CORE_DIV_CON_SHIFT);
110
111 rk_clrsetreg(&cru->cru_clksel_con[1],
112 CORE_ACLK_DIV_MASK | CORE_PERI_DIV_MASK,
113 aclk_div << CORE_ACLK_DIV_SHIFT |
114 pclk_div << CORE_PERI_DIV_SHIFT);
115
116 /*
117 * select gpll as pd_bus bus clock source and
118 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
119 */
120 aclk_div = GPLL_HZ / BUS_ACLK_HZ - 1;
121 assert((aclk_div + 1) * BUS_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f);
122
123 pclk_div = BUS_ACLK_HZ / BUS_PCLK_HZ - 1;
124 assert((pclk_div + 1) * BUS_PCLK_HZ == BUS_ACLK_HZ && pclk_div <= 0x7);
125
126 hclk_div = BUS_ACLK_HZ / BUS_HCLK_HZ - 1;
127 assert((hclk_div + 1) * BUS_HCLK_HZ == BUS_ACLK_HZ && hclk_div <= 0x3);
128
129 rk_clrsetreg(&cru->cru_clksel_con[0],
130 BUS_ACLK_PLL_SEL_MASK | BUS_ACLK_DIV_MASK,
131 BUS_ACLK_PLL_SEL_GPLL << BUS_ACLK_PLL_SEL_SHIFT |
132 aclk_div << BUS_ACLK_DIV_SHIFT);
133
134 rk_clrsetreg(&cru->cru_clksel_con[1],
135 BUS_PCLK_DIV_MASK | BUS_HCLK_DIV_MASK,
136 pclk_div << BUS_PCLK_DIV_SHIFT |
137 hclk_div << BUS_HCLK_DIV_SHIFT);
138
139 /*
140 * select gpll as pd_peri bus clock source and
141 * set up dependent divisors for PCLK/HCLK and ACLK clocks.
142 */
143 aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1;
144 assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f);
145
146 hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ);
147 assert((1 << hclk_div) * PERI_HCLK_HZ ==
148 PERI_ACLK_HZ && (hclk_div < 0x4));
149
150 pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ);
151 assert((1 << pclk_div) * PERI_PCLK_HZ ==
152 PERI_ACLK_HZ && pclk_div < 0x8);
153
154 rk_clrsetreg(&cru->cru_clksel_con[10],
155 PERI_PLL_SEL_MASK | PERI_PCLK_DIV_MASK |
156 PERI_HCLK_DIV_MASK | PERI_ACLK_DIV_MASK,
157 PERI_PLL_GPLL << PERI_PLL_SEL_SHIFT |
158 pclk_div << PERI_PCLK_DIV_SHIFT |
159 hclk_div << PERI_HCLK_DIV_SHIFT |
160 aclk_div << PERI_ACLK_DIV_SHIFT);
161
162 /* PLL enter normal-mode */
163 rk_clrsetreg(&cru->cru_mode_con,
164 GPLL_MODE_MASK | APLL_MODE_MASK,
165 GPLL_MODE_NORM << GPLL_MODE_SHIFT |
166 APLL_MODE_NORM << APLL_MODE_SHIFT);
167 }
168
169 /* Get pll rate by id */
rkclk_pll_get_rate(struct rk322x_cru * cru,enum rk_clk_id clk_id)170 static uint32_t rkclk_pll_get_rate(struct rk322x_cru *cru,
171 enum rk_clk_id clk_id)
172 {
173 uint32_t refdiv, fbdiv, postdiv1, postdiv2;
174 uint32_t con;
175 int pll_id = rk_pll_id(clk_id);
176 struct rk322x_pll *pll = &cru->pll[pll_id];
177 static u8 clk_shift[CLK_COUNT] = {
178 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, 0xff,
179 GPLL_MODE_SHIFT, 0xff
180 };
181 static u32 clk_mask[CLK_COUNT] = {
182 0xff, APLL_MODE_MASK, DPLL_MODE_MASK, 0xff,
183 GPLL_MODE_MASK, 0xff
184 };
185 uint shift;
186 uint mask;
187
188 con = readl(&cru->cru_mode_con);
189 shift = clk_shift[clk_id];
190 mask = clk_mask[clk_id];
191
192 switch ((con & mask) >> shift) {
193 case GPLL_MODE_SLOW:
194 return OSC_HZ;
195 case GPLL_MODE_NORM:
196
197 /* normal mode */
198 con = readl(&pll->con0);
199 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT;
200 fbdiv = (con & PLL_FBDIV_MASK) >> PLL_FBDIV_SHIFT;
201 con = readl(&pll->con1);
202 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT;
203 refdiv = (con & PLL_REFDIV_MASK) >> PLL_REFDIV_SHIFT;
204 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000;
205 default:
206 return 32768;
207 }
208 }
209
rockchip_mmc_get_clk(struct rk322x_cru * cru,uint clk_general_rate,int periph)210 static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate,
211 int periph)
212 {
213 uint src_rate;
214 uint div, mux;
215 u32 con;
216
217 switch (periph) {
218 case HCLK_EMMC:
219 case SCLK_EMMC:
220 case SCLK_EMMC_SAMPLE:
221 con = readl(&cru->cru_clksel_con[11]);
222 mux = (con & EMMC_PLL_MASK) >> EMMC_PLL_SHIFT;
223 con = readl(&cru->cru_clksel_con[12]);
224 div = (con & EMMC_DIV_MASK) >> EMMC_DIV_SHIFT;
225 break;
226 case HCLK_SDMMC:
227 case SCLK_SDMMC:
228 con = readl(&cru->cru_clksel_con[11]);
229 mux = (con & MMC0_PLL_MASK) >> MMC0_PLL_SHIFT;
230 div = (con & MMC0_DIV_MASK) >> MMC0_DIV_SHIFT;
231 break;
232 default:
233 return -EINVAL;
234 }
235
236 src_rate = mux == EMMC_SEL_24M ? OSC_HZ : clk_general_rate;
237 return DIV_TO_RATE(src_rate, div) / 2;
238 }
239
rk322x_mac_set_clk(struct rk322x_cru * cru,uint freq)240 static ulong rk322x_mac_set_clk(struct rk322x_cru *cru, uint freq)
241 {
242 ulong ret;
243
244 /*
245 * The gmac clock can be derived either from an external clock
246 * or can be generated from internally by a divider from SCLK_MAC.
247 */
248 if (readl(&cru->cru_clksel_con[5]) & BIT(5)) {
249 /* An external clock will always generate the right rate... */
250 ret = freq;
251 } else {
252 u32 con = readl(&cru->cru_clksel_con[5]);
253 ulong pll_rate;
254 u8 div;
255
256 if ((con >> MAC_PLL_SEL_SHIFT) & MAC_PLL_SEL_MASK)
257 pll_rate = GPLL_HZ;
258 else
259 /* CPLL is not set */
260 return -EPERM;
261
262 div = DIV_ROUND_UP(pll_rate, freq) - 1;
263 if (div <= 0x1f)
264 rk_clrsetreg(&cru->cru_clksel_con[5], CLK_MAC_DIV_MASK,
265 div << CLK_MAC_DIV_SHIFT);
266 else
267 debug("Unsupported div for gmac:%d\n", div);
268
269 return DIV_TO_RATE(pll_rate, div);
270 }
271
272 return ret;
273 }
274
rockchip_mmc_set_clk(struct rk322x_cru * cru,uint clk_general_rate,int periph,uint freq)275 static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate,
276 int periph, uint freq)
277 {
278 int src_clk_div;
279 int mux;
280
281 debug("%s: clk_general_rate=%u\n", __func__, clk_general_rate);
282
283 /* mmc clock defaulg div 2 internal, need provide double in cru */
284 src_clk_div = DIV_ROUND_UP(clk_general_rate / 2, freq);
285
286 if (src_clk_div > 128) {
287 src_clk_div = DIV_ROUND_UP(OSC_HZ / 2, freq);
288 assert(src_clk_div - 1 < 128);
289 mux = EMMC_SEL_24M;
290 } else {
291 mux = EMMC_SEL_GPLL;
292 }
293
294 switch (periph) {
295 case HCLK_EMMC:
296 case SCLK_EMMC:
297 case SCLK_EMMC_SAMPLE:
298 rk_clrsetreg(&cru->cru_clksel_con[11],
299 EMMC_PLL_MASK,
300 mux << EMMC_PLL_SHIFT);
301 rk_clrsetreg(&cru->cru_clksel_con[12],
302 EMMC_DIV_MASK,
303 (src_clk_div - 1) << EMMC_DIV_SHIFT);
304 break;
305 case HCLK_SDMMC:
306 case SCLK_SDMMC:
307 rk_clrsetreg(&cru->cru_clksel_con[11],
308 MMC0_PLL_MASK | MMC0_DIV_MASK,
309 mux << MMC0_PLL_SHIFT |
310 (src_clk_div - 1) << MMC0_DIV_SHIFT);
311 break;
312 default:
313 return -EINVAL;
314 }
315
316 return rockchip_mmc_get_clk(cru, clk_general_rate, periph);
317 }
318
rk322x_ddr_set_clk(struct rk322x_cru * cru,unsigned int set_rate)319 static int rk322x_ddr_set_clk(struct rk322x_cru *cru, unsigned int set_rate)
320 {
321 struct pll_div dpll_cfg;
322
323 /* clk_ddrc == DPLL = 24MHz / refdiv * fbdiv / postdiv1 / postdiv2 */
324 switch (set_rate) {
325 case 400*MHz:
326 dpll_cfg = (struct pll_div)
327 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1};
328 break;
329 case 600*MHz:
330 dpll_cfg = (struct pll_div)
331 {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1};
332 break;
333 case 800*MHz:
334 dpll_cfg = (struct pll_div)
335 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1};
336 break;
337 }
338
339 /* pll enter slow-mode */
340 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
341 DPLL_MODE_SLOW << DPLL_MODE_SHIFT);
342 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg);
343 /* PLL enter normal-mode */
344 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK,
345 DPLL_MODE_NORM << DPLL_MODE_SHIFT);
346
347 return set_rate;
348 }
rk322x_clk_get_rate(struct clk * clk)349 static ulong rk322x_clk_get_rate(struct clk *clk)
350 {
351 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
352 ulong rate, gclk_rate;
353
354 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
355 switch (clk->id) {
356 case 0 ... 63:
357 rate = rkclk_pll_get_rate(priv->cru, clk->id);
358 break;
359 case HCLK_EMMC:
360 case SCLK_EMMC:
361 case HCLK_SDMMC:
362 case SCLK_SDMMC:
363 rate = rockchip_mmc_get_clk(priv->cru, gclk_rate, clk->id);
364 break;
365 default:
366 return -ENOENT;
367 }
368
369 return rate;
370 }
371
rk322x_clk_set_rate(struct clk * clk,ulong rate)372 static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate)
373 {
374 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
375 ulong new_rate, gclk_rate;
376
377 gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL);
378 switch (clk->id) {
379 case HCLK_EMMC:
380 case SCLK_EMMC:
381 case HCLK_SDMMC:
382 case SCLK_SDMMC:
383 new_rate = rockchip_mmc_set_clk(priv->cru, gclk_rate,
384 clk->id, rate);
385 break;
386 case CLK_DDR:
387 new_rate = rk322x_ddr_set_clk(priv->cru, rate);
388 break;
389 case SCLK_MAC:
390 new_rate = rk322x_mac_set_clk(priv->cru, rate);
391 break;
392 case PLL_GPLL:
393 return 0;
394 default:
395 return -ENOENT;
396 }
397
398 return new_rate;
399 }
400
rk322x_gmac_set_parent(struct clk * clk,struct clk * parent)401 static int rk322x_gmac_set_parent(struct clk *clk, struct clk *parent)
402 {
403 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
404 struct rk322x_cru *cru = priv->cru;
405
406 /*
407 * If the requested parent is in the same clock-controller and the id
408 * is SCLK_MAC_SRC ("sclk_gmac_src"), switch to the internal clock.
409 */
410 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_SRC)) {
411 debug("%s: switching RGMII to SCLK_MAC_SRC\n", __func__);
412 rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), 0);
413 return 0;
414 }
415
416 /*
417 * If the requested parent is in the same clock-controller and the id
418 * is SCLK_MAC_EXTCLK (sclk_mac_extclk), switch to the external clock.
419 */
420 if ((parent->dev == clk->dev) && (parent->id == SCLK_MAC_EXTCLK)) {
421 debug("%s: switching RGMII to SCLK_MAC_EXTCLK\n", __func__);
422 rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), BIT(5));
423 return 0;
424 }
425
426 return -EINVAL;
427 }
428
rk322x_gmac_extclk_set_parent(struct clk * clk,struct clk * parent)429 static int rk322x_gmac_extclk_set_parent(struct clk *clk, struct clk *parent)
430 {
431 struct rk322x_clk_priv *priv = dev_get_priv(clk->dev);
432 const char *clock_output_name;
433 struct rk322x_cru *cru = priv->cru;
434 int ret;
435
436 ret = dev_read_string_index(parent->dev, "clock-output-names",
437 parent->id, &clock_output_name);
438 if (ret < 0)
439 return -ENODATA;
440
441 if (!strcmp(clock_output_name, "ext_gmac")) {
442 debug("%s: switching gmac extclk to ext_gmac\n", __func__);
443 rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), 0);
444 return 0;
445 } else if (!strcmp(clock_output_name, "phy_50m_out")) {
446 debug("%s: switching gmac extclk to phy_50m_out\n", __func__);
447 rk_clrsetreg(&cru->cru_clksel_con[29], BIT(10), BIT(10));
448 return 0;
449 }
450
451 return -EINVAL;
452 }
453
rk322x_clk_set_parent(struct clk * clk,struct clk * parent)454 static int rk322x_clk_set_parent(struct clk *clk, struct clk *parent)
455 {
456 switch (clk->id) {
457 case SCLK_MAC:
458 return rk322x_gmac_set_parent(clk, parent);
459 case SCLK_MAC_EXTCLK:
460 return rk322x_gmac_extclk_set_parent(clk, parent);
461 }
462
463 debug("%s: unsupported clk %ld\n", __func__, clk->id);
464 return -ENOENT;
465 }
466
467 static struct clk_ops rk322x_clk_ops = {
468 .get_rate = rk322x_clk_get_rate,
469 .set_rate = rk322x_clk_set_rate,
470 .set_parent = rk322x_clk_set_parent,
471 };
472
rk322x_clk_ofdata_to_platdata(struct udevice * dev)473 static int rk322x_clk_ofdata_to_platdata(struct udevice *dev)
474 {
475 struct rk322x_clk_priv *priv = dev_get_priv(dev);
476
477 priv->cru = dev_read_addr_ptr(dev);
478
479 return 0;
480 }
481
rk322x_clk_probe(struct udevice * dev)482 static int rk322x_clk_probe(struct udevice *dev)
483 {
484 struct rk322x_clk_priv *priv = dev_get_priv(dev);
485
486 rkclk_init(priv->cru);
487
488 return 0;
489 }
490
rk322x_clk_bind(struct udevice * dev)491 static int rk322x_clk_bind(struct udevice *dev)
492 {
493 int ret;
494 struct udevice *sys_child;
495 struct sysreset_reg *priv;
496
497 /* The reset driver does not have a device node, so bind it here */
498 ret = device_bind_driver(dev, "rockchip_sysreset", "sysreset",
499 &sys_child);
500 if (ret) {
501 debug("Warning: No sysreset driver: ret=%d\n", ret);
502 } else {
503 priv = malloc(sizeof(struct sysreset_reg));
504 priv->glb_srst_fst_value = offsetof(struct rk322x_cru,
505 cru_glb_srst_fst_value);
506 priv->glb_srst_snd_value = offsetof(struct rk322x_cru,
507 cru_glb_srst_snd_value);
508 sys_child->priv = priv;
509 }
510
511 #if CONFIG_IS_ENABLED(RESET_ROCKCHIP)
512 ret = offsetof(struct rk322x_cru, cru_softrst_con[0]);
513 ret = rockchip_reset_bind(dev, ret, 9);
514 if (ret)
515 debug("Warning: software reset driver bind faile\n");
516 #endif
517
518 return 0;
519 }
520
521 static const struct udevice_id rk322x_clk_ids[] = {
522 { .compatible = "rockchip,rk3228-cru" },
523 { }
524 };
525
526 U_BOOT_DRIVER(rockchip_rk322x_cru) = {
527 .name = "clk_rk322x",
528 .id = UCLASS_CLK,
529 .of_match = rk322x_clk_ids,
530 .priv_auto_alloc_size = sizeof(struct rk322x_clk_priv),
531 .ofdata_to_platdata = rk322x_clk_ofdata_to_platdata,
532 .ops = &rk322x_clk_ops,
533 .bind = rk322x_clk_bind,
534 .probe = rk322x_clk_probe,
535 };
536