| /third_party/uboot/u-boot-2020.01/arch/arm/mach-tegra/ |
| D | clock.c | 26 static unsigned pll_rate[CLOCK_ID_COUNT]; variable
275 div = clk_get_divider(8, pll_rate[clkid], rate); in clock_set_pllout()
314 unsigned parent_rate = pll_rate[parent]; in clock_get_periph_rate()
452 divider = find_best_divider(divider_bits, pll_rate[parent], in clock_adjust_periph_pll_div()
691 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL); in clock_init()
692 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY); in clock_init()
693 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH); in clock_init()
694 pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB); in clock_init()
695 pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY); in clock_init()
696 pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU); in clock_init()
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| /third_party/uboot/u-boot-2020.01/drivers/clk/ |
| D | clk-hsdk-cgu.c | 136 const u32 pll_rate[MAX_TUN_CLOCKS]; member
156 const u32 pll_rate[MAX_AXI_CLOCKS]; member
538 ulong pll_rate; in axi_clk_set() local
542 pll_rate = pll_get(sclk); in axi_clk_set()
557 if (axi_clk_cfg.pll_rate[freq_idx] < pll_rate) in axi_clk_set()
558 ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]); in axi_clk_set()
567 if (axi_clk_cfg.pll_rate[freq_idx] >= pll_rate) in axi_clk_set()
568 ret = pll_set(sclk, axi_clk_cfg.pll_rate[freq_idx]); in axi_clk_set()
576 ulong pll_rate; in tun_clk_set() local
580 pll_rate = pll_get(sclk); in tun_clk_set()
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| D | clk_zynq.c | 288 ulong pll_rate, in zynq_clk_calc_peripheral_two_divs() argument
298 DIV_ROUND_CLOSEST(pll_rate, d0), d1); in zynq_clk_calc_peripheral_two_divs()
319 ulong pll_rate, new_rate; in zynq_clk_set_peripheral_rate() local
326 pll_rate = zynq_clk_get_pll_rate(priv, pll); in zynq_clk_set_peripheral_rate()
330 new_rate = zynq_clk_calc_peripheral_two_divs(rate, pll_rate, in zynq_clk_set_peripheral_rate()
334 div0 = DIV_ROUND_CLOSEST(pll_rate, rate); in zynq_clk_set_peripheral_rate()
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| D | clk_zynqmp.c | 494 ulong pll_rate, in zynqmp_clk_calc_peripheral_two_divs() argument
504 DIV_ROUND_CLOSEST(pll_rate, d0), d1); in zynqmp_clk_calc_peripheral_two_divs()
525 ulong pll_rate, new_rate; in zynqmp_clk_set_peripheral_rate() local
538 pll_rate = zynqmp_clk_get_pll_rate(priv, pll); in zynqmp_clk_set_peripheral_rate()
539 if (IS_ERR_VALUE(pll_rate)) in zynqmp_clk_set_peripheral_rate()
540 return pll_rate; in zynqmp_clk_set_peripheral_rate()
545 new_rate = zynqmp_clk_calc_peripheral_two_divs(rate, pll_rate, in zynqmp_clk_set_peripheral_rate()
549 div0 = DIV_ROUND_CLOSEST(pll_rate, rate); in zynqmp_clk_set_peripheral_rate()
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| /third_party/uboot/u-boot-2020.01/drivers/clk/rockchip/ |
| D | clk_rv1108.c | 146 ulong pll_rate; in rv1108_mac_set_clk() local
150 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_mac_set_clk()
152 pll_rate = rkclk_pll_get_rate(cru, CLK_ARM); in rv1108_mac_set_clk()
158 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rv1108_mac_set_clk()
165 return DIV_TO_RATE(pll_rate, div); in rv1108_mac_set_clk()
171 u32 pll_rate; in rv1108_sfc_set_clk() local
175 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_sfc_set_clk()
177 pll_rate = rkclk_pll_get_rate(cru, CLK_DDR); in rv1108_sfc_set_clk()
179 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rv1108_sfc_set_clk()
186 return DIV_TO_RATE(pll_rate, div); in rv1108_sfc_set_clk()
[all …]
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| D | clk_rk3368.c | 160 u32 pll_rate; in rk3368_mmc_get_clk() local
179 pll_rate = rkclk_pll_get_rate(cru, GPLL); in rk3368_mmc_get_clk()
182 pll_rate = OSC_HZ; in rk3368_mmc_get_clk()
185 pll_rate = rkclk_pll_get_rate(cru, CPLL); in rk3368_mmc_get_clk()
192 rate = DIV_TO_RATE(pll_rate, div); in rk3368_mmc_get_clk()
325 ulong pll_rate; in rk3368_gmac_set_clk() local
330 pll_rate = GPLL_HZ; in rk3368_gmac_set_clk()
333 pll_rate = CPLL_HZ; in rk3368_gmac_set_clk()
338 div = DIV_ROUND_UP(pll_rate, set_rate) - 1; in rk3368_gmac_set_clk()
345 return DIV_TO_RATE(pll_rate, div); in rk3368_gmac_set_clk()
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| D | clk_rk3308.c | 192 ulong pll_rate; in rk3308_mac_set_clk() local
196 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL0], in rk3308_mac_set_clk()
199 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[VPLL1], in rk3308_mac_set_clk()
202 pll_rate = rockchip_pll_get_rate(&rk3308_pll_clks[DPLL], in rk3308_mac_set_clk()
209 div = DIV_ROUND_UP(pll_rate, hz) - 1; in rk3308_mac_set_clk()
214 return DIV_TO_RATE(pll_rate, div); in rk3308_mac_set_clk()
489 ulong pll_rate, now, best_rate = 0; in rk3308_vop_set_clk() local
495 pll_rate = priv->dpll_hz; in rk3308_vop_set_clk()
498 pll_rate = priv->vpll0_hz; in rk3308_vop_set_clk()
501 pll_rate = priv->vpll1_hz; in rk3308_vop_set_clk()
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| D | clk_rk3328.c | 421 ulong pll_rate; in rk3328_gmac2io_set_clk() local
425 pll_rate = GPLL_HZ; in rk3328_gmac2io_set_clk()
427 pll_rate = CPLL_HZ; in rk3328_gmac2io_set_clk()
429 div = DIV_ROUND_UP(pll_rate, rate) - 1; in rk3328_gmac2io_set_clk()
436 return DIV_TO_RATE(pll_rate, div); in rk3328_gmac2io_set_clk()
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| D | clk_rk322x.c | 253 ulong pll_rate; in rk322x_mac_set_clk() local
257 pll_rate = GPLL_HZ; in rk322x_mac_set_clk()
262 div = DIV_ROUND_UP(pll_rate, freq) - 1; in rk322x_mac_set_clk()
269 return DIV_TO_RATE(pll_rate, div); in rk322x_mac_set_clk()
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| D | clk_rk3288.c | 311 ulong pll_rate; in rockchip_mac_set_clk() local
316 pll_rate = GPLL_HZ; in rockchip_mac_set_clk()
319 pll_rate = CPLL_HZ; in rockchip_mac_set_clk()
321 pll_rate = NPLL_HZ; in rockchip_mac_set_clk()
323 div = DIV_ROUND_UP(pll_rate, freq) - 1; in rockchip_mac_set_clk()
330 return DIV_TO_RATE(pll_rate, div); in rockchip_mac_set_clk()
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| D | clk_px30.c | 1055 ulong pll_rate; in px30_mac_set_clk() local
1059 pll_rate = px30_clk_get_pll_rate(priv, CPLL); in px30_mac_set_clk()
1061 pll_rate = px30_clk_get_pll_rate(priv, NPLL); in px30_mac_set_clk()
1063 pll_rate = priv->gpll_hz; in px30_mac_set_clk()
1069 div = DIV_ROUND_UP(pll_rate, hz) - 1; in px30_mac_set_clk()
1074 return DIV_TO_RATE(pll_rate, div); in px30_mac_set_clk()
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