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Searched refs:readl (Results 1 – 25 of 1226) sorted by relevance

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/third_party/uboot/u-boot-2020.01/drivers/phy/hibvt/
Dphy_usb_hi3531dv200.c54 reg = readl(USB2_CTRL1_CFG); in usb2_crg_config()
60 reg = readl(USB2_PHY1_CFG); in usb2_crg_config()
66 reg = readl(USB2_PHY1_CFG); in usb2_crg_config()
72 reg = readl(USB2_PHY1_CFG); in usb2_crg_config()
78 reg = readl(USB2_CTRL1_CFG); in usb2_crg_config()
86 reg = readl(USB2_CTRL1_CFG); in usb2_crg_config()
98 reg = readl(USB2_PHY1_BASE + PHY_PLL_OFFSET); in usb2_phy_config()
104 reg = readl(USB2_PHY1_BASE + U2_ANA_CFG0); in usb2_phy_config()
111 reg = readl(USB2_PHY1_BASE + U2_ANA_CFG2); in usb2_phy_config()
119 trim_val = readl(USB_SYS_CTRL_BASE); in usb2_phy_config()
[all …]
Dphy_usb_hi3521dv200.c50 reg = readl(USB2_PHY0_BASE + PHY_PLL_OFFSET); in usb2_phy0_config()
56 trim_val = readl(USB_SYS_CTRL_BASE); in usb2_phy0_config()
59 reg = readl(USB2_PHY0_BASE + U2_ANA_CFG2); in usb2_phy0_config()
67 reg = readl(USB2_PHY0_BASE + RG_HSTX_MBIAS); in usb2_phy0_config()
74 reg = readl(USB2_PHY0_BASE + TX_TEST_BIT); in usb2_phy0_config()
80 reg = readl(USB2_PHY0_BASE + DISC_REF_VOL_SEL); in usb2_phy0_config()
87 reg = readl(USB2_PHY0_BASE + SLEW_RATE_OPTION); in usb2_phy0_config()
94 reg = readl(USB2_PHY0_BASE + TX_REF_VOL_SEL); in usb2_phy0_config()
101 reg = readl(USB2_PHY0_BASE + RG_FL_EDGE_MODE); in usb2_phy0_config()
113 reg = readl(USB2_PHY1_BASE + PHY_PLL_OFFSET); in usb2_phy1_config()
[all …]
Dphy-usb-hi3519av100.c113 reg = readl(MISC_REG_BASE + USB2_PHY0); in hisi_usb_eye_config()
123 reg = readl(MISC_REG_BASE + USB2_PHY1); in hisi_usb_eye_config()
132 reg = readl(USB3_CTRL_REG_BASE + REG_GUSB3PIPECTL0); in hisi_usb_eye_config()
143 reg = readl(USB3_CTRL_CFG); in hisi_usb_config()
150 reg = readl(USB3_CTRL_CFG); in hisi_usb_config()
156 reg = readl(USB2_PHY_CFG); in hisi_usb_config()
162 reg = readl(USB3_CTRL_CFG); in hisi_usb_config()
168 reg = readl(USB2_PHY_CFG); in hisi_usb_config()
174 reg = readl(USB2_PHY_CFG); in hisi_usb_config()
180 reg = readl(USB3_CTRL_CFG); in hisi_usb_config()
[all …]
Dphy-usb-hi3556av100.c113 reg = readl(MISC_REG_BASE + USB2_PHY0); in hisi_usb_eye_config()
123 reg = readl(MISC_REG_BASE + USB2_PHY1); in hisi_usb_eye_config()
132 reg = readl(USB3_CTRL_REG_BASE + REG_GUSB3PIPECTL0); in hisi_usb_eye_config()
143 reg = readl(USB3_CTRL_CFG); in hisi_usb_config()
150 reg = readl(USB3_CTRL_CFG); in hisi_usb_config()
156 reg = readl(USB2_PHY_CFG); in hisi_usb_config()
162 reg = readl(USB3_CTRL_CFG); in hisi_usb_config()
168 reg = readl(USB2_PHY_CFG); in hisi_usb_config()
174 reg = readl(USB2_PHY_CFG); in hisi_usb_config()
180 reg = readl(USB3_CTRL_CFG); in hisi_usb_config()
[all …]
Dphy-hi3516dv200-usb.c126 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_0_OFFSET); in usb2_eye_config()
132 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET); in usb2_eye_config()
137 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET); in usb2_eye_config()
143 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_4_OFFSET); in usb2_eye_config()
149 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_4_OFFSET); in usb2_eye_config()
161 ret = readl(USB_TRIM_BASE_REG); in usb2_trim_config()
163 reg = readl(USB2_PHY_BASE_REG + USB2_TRIM_OFFSET); in usb2_trim_config()
180 ret = readl(USB_SVB_BASE_REG); in usb2_svb_config()
181 reg = readl(USB2_PHY_BASE_REG + USB_SVB_OFFSET); in usb2_svb_config()
208 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
[all …]
Dphy-hi3518ev300-usb.c127 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_0_OFFSET); in usb2_eye_config()
133 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET); in usb2_eye_config()
138 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET); in usb2_eye_config()
144 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_4_OFFSET); in usb2_eye_config()
150 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_4_OFFSET); in usb2_eye_config()
162 ret = readl(USB_TRIM_BASE_REG); in usb2_trim_config()
164 reg = readl(USB2_PHY_BASE_REG + USB2_TRIM_OFFSET); in usb2_trim_config()
180 ret = readl(USB_SVB_BASE_REG); in usb2_svb_config()
181 reg = readl(USB2_PHY_BASE_REG + USB_SVB_OFFSET); in usb2_svb_config()
208 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
[all …]
Dphy-hi3516ev300-usb.c128 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_0_OFFSET); in usb2_eye_config()
134 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET); in usb2_eye_config()
139 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET); in usb2_eye_config()
145 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_4_OFFSET); in usb2_eye_config()
151 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_4_OFFSET); in usb2_eye_config()
163 ret = readl(USB_TRIM_BASE_REG); in usb2_trim_config()
165 reg = readl(USB2_PHY_BASE_REG + USB2_TRIM_OFFSET); in usb2_trim_config()
181 ret = readl(USB_SVB_BASE_REG); in usb2_svb_config()
182 reg = readl(USB2_PHY_BASE_REG + USB_SVB_OFFSET); in usb2_svb_config()
207 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
[all …]
Dphy-hi3516ev200-usb.c126 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_0_OFFSET); in usb2_eye_config()
132 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET); in usb2_eye_config()
137 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_2_OFFSET); in usb2_eye_config()
143 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_4_OFFSET); in usb2_eye_config()
149 reg = readl(USB2_PHY_BASE_REG + HIXVP_PHY_ANA_CFG_4_OFFSET); in usb2_eye_config()
161 ret = readl(USB_TRIM_BASE_REG); in usb2_trim_config()
163 reg = readl(USB2_PHY_BASE_REG + USB2_TRIM_OFFSET); in usb2_trim_config()
179 ret = readl(USB_SVB_BASE_REG); in usb2_svb_config()
180 reg = readl(USB2_PHY_BASE_REG + USB_SVB_OFFSET); in usb2_svb_config()
207 reg = readl(CRG_REG_BASE + USB2_CTRL); in phy_hiusb_init_crg_clk()
[all …]
Dphy-usb-hi3516dv300.c105 reg = readl(USB2_INNO_PHY_BASE_REG + HS_HIGH_HEIGHT_TUNING_OFFSET); in usb2_eye_config()
111 reg = readl(USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_TUNING_OFFSET); in usb2_eye_config()
117 reg = readl(USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_STRENGTH_OFFSET); in usb2_eye_config()
123 reg = readl(USB2_INNO_PHY_BASE_REG + HS_SLEW_RATE_TUNING_OFFSET); in usb2_eye_config()
129 reg = readl(USB2_INNO_PHY_BASE_REG + DISCONNECT_TRIGGER_OFFSET); in usb2_eye_config()
144 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
150 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
156 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
162 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
168 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
[all …]
Dphy-usb-hi3556v200.c105 reg = readl(USB2_INNO_PHY_BASE_REG + HS_HIGH_HEIGHT_TUNING_OFFSET); in usb2_eye_config()
111 reg = readl(USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_TUNING_OFFSET); in usb2_eye_config()
117 reg = readl(USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_STRENGTH_OFFSET); in usb2_eye_config()
123 reg = readl(USB2_INNO_PHY_BASE_REG + HS_SLEW_RATE_TUNING_OFFSET); in usb2_eye_config()
129 reg = readl(USB2_INNO_PHY_BASE_REG + DISCONNECT_TRIGGER_OFFSET); in usb2_eye_config()
145 reg = readl(CRG_REG_BASE + REG_CRG80); in hisi_usb_init_clk()
151 reg = readl(CRG_REG_BASE + REG_CRG80); in hisi_usb_init_clk()
157 reg = readl(CRG_REG_BASE + REG_CRG80); in hisi_usb_init_clk()
163 reg = readl(CRG_REG_BASE + REG_CRG80); in hisi_usb_init_clk()
169 reg = readl(CRG_REG_BASE + REG_CRG80); in hisi_usb_init_clk()
[all …]
Dphy-usb-hi3559v200.c105 reg = readl(USB2_INNO_PHY_BASE_REG + HS_HIGH_HEIGHT_TUNING_OFFSET); in usb2_eye_config()
111 reg = readl(USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_TUNING_OFFSET); in usb2_eye_config()
117 reg = readl(USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_STRENGTH_OFFSET); in usb2_eye_config()
123 reg = readl(USB2_INNO_PHY_BASE_REG + HS_SLEW_RATE_TUNING_OFFSET); in usb2_eye_config()
129 reg = readl(USB2_INNO_PHY_BASE_REG + DISCONNECT_TRIGGER_OFFSET); in usb2_eye_config()
145 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
151 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
157 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
163 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
169 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
[all …]
Dphy-usb-hi3516cv500.c105 reg = readl(USB2_INNO_PHY_BASE_REG + HS_HIGH_HEIGHT_TUNING_OFFSET); in usb2_eye_config()
111 reg = readl(USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_TUNING_OFFSET); in usb2_eye_config()
117 reg = readl(USB2_INNO_PHY_BASE_REG + PRE_EMPHASIS_STRENGTH_OFFSET); in usb2_eye_config()
123 reg = readl(USB2_INNO_PHY_BASE_REG + HS_SLEW_RATE_TUNING_OFFSET); in usb2_eye_config()
129 reg = readl(USB2_INNO_PHY_BASE_REG + DISCONNECT_TRIGGER_OFFSET); in usb2_eye_config()
145 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
151 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
157 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
163 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
169 reg = readl(CRG_REG_BASE + REG_CRG80); in phy_hiusb_init_clk()
[all …]
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/pxa/
Dusb.c20 writel(readl(CKENA) | CKENA_2_USBHOST | CKENA_20_UDC, CKENA); in usb_cpu_init()
25 writel(readl(CKEN) | CKEN10_USBHOST, CKEN); in usb_cpu_init()
33 writel(readl(UHCHR) | UHCHR_FHR, UHCHR); in usb_cpu_init()
35 writel(readl(UHCHR) & ~UHCHR_FHR, UHCHR); in usb_cpu_init()
37 writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); in usb_cpu_init()
38 while (readl(UHCHR) & UHCHR_FSBIR) in usb_cpu_init()
42 writel(readl(UHCHR) & ~UHCHR_SSEP0, UHCHR); in usb_cpu_init()
45 writel(readl(UHCHR) & ~UHCHR_SSEP2, UHCHR); in usb_cpu_init()
47 writel(readl(UHCHR) & ~(UHCHR_SSEP1 | UHCHR_SSE), UHCHR); in usb_cpu_init()
54 writel(readl(UHCHR) | UHCHR_FHR, UHCHR); in usb_cpu_stop()
[all …]
/third_party/uboot/u-boot-2020.01/arch/arm/mach-uniphier/clk/
Dpll-ld4.c19 tmp = readl(sg_base + SG_PINMON0); in upll_init()
24 tmp = readl(sc_base + SC_UPLLCTRL); in upll_init()
59 tmp = readl(sg_base + SG_PINMON0); in vpll_init()
63 tmp = readl(sc_base + SC_VPLL27ACTRL); in vpll_init()
66 tmp = readl(sc_base + SC_VPLL27BCTRL); in vpll_init()
71 tmp = readl(sc_base + SC_VPLL27ACTRL3); in vpll_init()
74 tmp = readl(sc_base + SC_VPLL27BCTRL3); in vpll_init()
79 tmp = readl(sc_base + SC_VPLL27ACTRL2); in vpll_init()
82 tmp = readl(sc_base + SC_VPLL27BCTRL2); in vpll_init()
87 tmp = readl(sc_base + SC_VPLL27ACTRL2); in vpll_init()
[all …]
Dpll-pro4.c20 tmp = readl(sg_base + SG_PINMON0); in vpll_init()
29 tmp = readl(sc_base + SC_VPLL27ACTRL); in vpll_init()
32 tmp = readl(sc_base + SC_VPLL27BCTRL); in vpll_init()
37 tmp = readl(sc_base + SC_VPLL27ACTRL3); in vpll_init()
40 tmp = readl(sc_base + SC_VPLL27BCTRL3); in vpll_init()
45 tmp = readl(sc_base + SC_VPLL27ACTRL2); in vpll_init()
49 tmp = readl(sc_base + SC_VPLL27BCTRL2); in vpll_init()
57 tmp = readl(sc_base + SC_VPLL27ACTRL3); in vpll_init()
61 tmp = readl(sc_base + SC_VPLL27BCTRL3); in vpll_init()
67 tmp = readl(sc_base + SC_VPLL27ACTRL3); in vpll_init()
[all …]
/third_party/uboot/u-boot-2020.01/board/synopsys/iot_devkit/
Diot_devkit.c48 writel(readl(PLLCON) & PLL_MASK_0, PLLCON); in set_cpu_freq()
50 writel((readl(PLLCON) & PLL_MASK_1) | 0x300191, PLLCON); in set_cpu_freq()
52 writel((readl(PLLCON) & PLL_MASK_2) | 0x300191, PLLCON); in set_cpu_freq()
56 writel(readl(PLLCON) & PLL_MASK_0, PLLCON); in set_cpu_freq()
58 writel((readl(PLLCON) & PLL_MASK_1) | 0x200121, PLLCON); in set_cpu_freq()
60 writel((readl(PLLCON) & PLL_MASK_2) | 0x200121, PLLCON); in set_cpu_freq()
64 writel(readl(PLLCON) & PLL_MASK_0, PLLCON); in set_cpu_freq()
66 writel((readl(PLLCON) & PLL_MASK_1) | 0x200191, PLLCON); in set_cpu_freq()
68 writel((readl(PLLCON) & PLL_MASK_2) | 0x200191, PLLCON); in set_cpu_freq()
72 writel(readl(PLLCON) & PLL_MASK_0, PLLCON); in set_cpu_freq()
[all …]
/third_party/uboot/u-boot-2020.01/arch/arm/mach-exynos/
Dclock.c193 r = readl(&clk->apll_con0); in exynos4_get_pll_clk()
196 r = readl(&clk->mpll_con0); in exynos4_get_pll_clk()
199 r = readl(&clk->epll_con0); in exynos4_get_pll_clk()
200 k = readl(&clk->epll_con1); in exynos4_get_pll_clk()
203 r = readl(&clk->vpll_con0); in exynos4_get_pll_clk()
204 k = readl(&clk->vpll_con1); in exynos4_get_pll_clk()
223 r = readl(&clk->apll_con0); in exynos4x12_get_pll_clk()
226 r = readl(&clk->mpll_con0); in exynos4x12_get_pll_clk()
229 r = readl(&clk->epll_con0); in exynos4x12_get_pll_clk()
230 k = readl(&clk->epll_con1); in exynos4x12_get_pll_clk()
[all …]
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/arm926ejs/mx27/
Dgeneric.c49 if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) { in clk_in_26m()
60 ulong cscr = readl(&pll->cscr); in imx_get_mpllclk()
68 return imx_decode_pll(readl(&pll->mpctl0), fref); in imx_get_mpllclk()
74 ulong cscr = readl(&pll->cscr); in imx_get_armclk()
89 ulong cscr = readl(&pll->cscr); in imx_get_ahbclk()
101 ulong cscr = readl(&pll->cscr); in imx_get_spllclk()
109 return imx_decode_pll(readl(&pll->spctl0), fref); in imx_get_spllclk()
121 return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1); in imx_get_perclk1()
128 return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1); in imx_get_perclk2()
135 return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1); in imx_get_perclk3()
[all …]
/third_party/uboot/u-boot-2020.01/arch/arm/mach-omap2/am33xx/
Dclock_ti816x.c141 while (((readl(&cmdef->dmmclkctrl) >> 17) & 0x3) != 0) in enable_dmm_clocks()
153 while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300) in enable_emif_clocks()
156 while (((readl(&cmdef->emif0clkctrl) >> 17) & 0x3) != 0) in enable_emif_clocks()
159 while (((readl(&cmdef->emif1clkctrl) >> 17) & 0x3) != 0) in enable_emif_clocks()
175 readl(CONTROL_STATUS); in ddr_delay()
183 main_pll_ctrl = readl(&cmpll->mainpll_ctrl); in main_pll_init_ti816x()
189 main_pll_ctrl = readl(&cmpll->mainpll_ctrl); in main_pll_init_ti816x()
195 main_pll_ctrl = readl(&cmpll->mainpll_ctrl); in main_pll_init_ti816x()
229 while ((readl(&cmpll->mainpll_ctrl) & BIT(7)) != BIT(7)) in main_pll_init_ti816x()
233 main_pll_ctrl = readl(&cmpll->mainpll_ctrl); in main_pll_init_ti816x()
[all …]
/third_party/uboot/u-boot-2020.01/drivers/watchdog/
Domap_wdt.c64 if ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WTGR) in hw_watchdog_reset()
86 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR) in omap_wdt_set_timeout()
90 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WLDR) in omap_wdt_set_timeout()
104 while (readl(&wdt->wdtwwps) != 0x0) in hw_watchdog_disable()
107 while (readl(&wdt->wdtwwps) != 0x0) in hw_watchdog_disable()
123 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR) in hw_watchdog_init()
127 while (readl(&wdt->wdtwwps) & WDT_WWPS_PEND_WCLR) in hw_watchdog_init()
134 while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR) in hw_watchdog_init()
138 while ((readl(&wdt->wdtwwps)) & WDT_WWPS_PEND_WSPR) in hw_watchdog_init()
158 if ((readl(&priv->regs->wdtwwps)) & WDT_WWPS_PEND_WTGR) in omap3_wdt_reset()
[all …]
/third_party/uboot/u-boot-2020.01/arch/arm/cpu/armv7/stv0991/
Dpinmux.c20 writel((readl(&stv0991_creg->mux12) & GPIOC_31_MUX_MASK) | in stv0991_pinmux_config()
23 writel((readl(&stv0991_creg->mux12) & GPIOC_30_MUX_MASK) | in stv0991_pinmux_config()
27 writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_31_MODE_MASK) | in stv0991_pinmux_config()
30 writel((readl(&stv0991_creg->cfg_pad6) & GPIOC_30_MODE_MASK) | in stv0991_pinmux_config()
36 writel((readl(&stv0991_creg->mux7) & GPIOB_17_MUX_MASK) | in stv0991_pinmux_config()
39 writel((readl(&stv0991_creg->mux7) & GPIOB_16_MUX_MASK) | in stv0991_pinmux_config()
44 writel(readl(&stv0991_creg->mux6) & 0x000000FF, in stv0991_pinmux_config()
48 writel(readl(&stv0991_creg->mux9) & 0xFFF00000, in stv0991_pinmux_config()
51 writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | in stv0991_pinmux_config()
53 writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | in stv0991_pinmux_config()
[all …]
/third_party/uboot/u-boot-2020.01/board/toradex/colibri_pxa270/
Dcolibri_pxa270.c66 writel((readl(UHCHR) | UHCHR_PCPL | UHCHR_PSPL) & in board_usb_init()
70 writel(readl(UHCHR) | UHCHR_FSBIR, UHCHR); in board_usb_init()
75 writel(readl(UHCHR) & ~UHCHR_SSE, UHCHR); in board_usb_init()
79 if (readl(PSSR) & PSSR_OTGPH) in board_usb_init()
80 writel(readl(PSSR) | PSSR_OTGPH, PSSR); in board_usb_init()
82 writel(readl(UHCRHDA) & ~(0x200), UHCRHDA); in board_usb_init()
83 writel(readl(UHCRHDA) | 0x100, UHCRHDA); in board_usb_init()
86 writel(readl(UHCRHDB) | (0x7<<17), UHCRHDB); in board_usb_init()
89 writel(readl(UP2OCR) | UP2OCR_HXOE | UP2OCR_HXS | in board_usb_init()
102 writel(readl(UHCHR) | UHCHR_FHR, UHCHR); in usb_board_stop()
[all …]
/third_party/uboot/u-boot-2020.01/arch/arm/mach-omap2/omap5/
Dhwinit.c104 io_settings = (readl((*ctrl)->control_port_emif1_sdram_config) in io_settings_ddr3()
109 io_settings = (readl((*ctrl)->control_port_emif2_sdram_config) in io_settings_ddr3()
130 io_settings = readl((*ctrl)->control_smart1io_padconf_0) & in do_io_settings()
138 io_settings = readl((*ctrl)->control_smart1io_padconf_1) & in do_io_settings()
145 io_settings = readl((*ctrl)->control_smart1io_padconf_2) & in do_io_settings()
152 io_settings = readl((*ctrl)->control_smart2io_padconf_0) & in do_io_settings()
159 io_settings = readl((*ctrl)->control_smart2io_padconf_1) & in do_io_settings()
166 io_settings = readl((*ctrl)->control_smart2io_padconf_2) & in do_io_settings()
174 io_settings = readl((*ctrl)->control_smart3io_padconf_1) & in do_io_settings()
210 srcomp_value = readl((*ctrl)->control_srcomp_north_side + i*4); in srcomp_enable()
[all …]
/third_party/uboot/u-boot-2020.01/drivers/usb/gadget/
Ddesignware_udc.c147 writel(readl(&inep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL, in udc_stall_ep()
150 writel(readl(&outep_regs_p[ep_num].endp_cntl) | ENDP_CNTL_STALL, in udc_stall_ep()
160 fifo_ptr += readl(&inep_regs_p[1].endp_bsorfn); in get_fifo()
164 fifo_ptr += readl(&inep_regs_p[0].endp_bsorfn); in get_fifo()
171 readl(&outep_regs_p[2].endp_maxpacksize) >> 16; in get_fifo()
178 fifo_ptr += readl(&outep_regs_p[0].endp_maxpacksize) >> 16; in get_fifo()
193 if (readl(&udc_regs_p->dev_stat) & DEV_STAT_RXFIFO_EMPTY) in usbgetpckfromfifo()
206 writel(readl(fifo_ptr), wrdp); in usbgetpckfromfifo()
216 readl(&outep_regs_p[epNum].write_done); in usbgetpckfromfifo()
385 u32 len = (readl(&outep_regs_p[0].endp_status) >> 11) & 0xfff; in dw_udc_ep0_rx()
[all …]
/third_party/uboot/u-boot-2020.01/arch/arm/mach-imx/mx7ulp/
Dscg.c22 reg = readl(&scg1_regs->sosccsr); in scg_src_get_rate()
28 reg = readl(&scg1_regs->firccsr); in scg_src_get_rate()
34 reg = readl(&scg1_regs->sirccsr); in scg_src_get_rate()
40 reg = readl(&scg1_regs->rtccsr); in scg_src_get_rate()
74 reg = readl(&scg1_regs->sirccsr); in scg_sircdiv_get_rate()
78 reg = readl(&scg1_regs->sircdiv); in scg_sircdiv_get_rate()
112 reg = readl(&scg1_regs->firccsr); in scg_fircdiv_get_rate()
116 reg = readl(&scg1_regs->fircdiv); in scg_fircdiv_get_rate()
150 reg = readl(&scg1_regs->sosccsr); in scg_soscdiv_get_rate()
154 reg = readl(&scg1_regs->soscdiv); in scg_soscdiv_get_rate()
[all …]

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