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Searched refs:sysmgr_regs (Results 1 – 16 of 16) sorted by relevance

/third_party/uboot/u-boot-2020.01/arch/arm/mach-socfpga/
Dsystem_manager_gen5.c11 static struct socfpga_system_manager *sysmgr_regs = variable
24 writel(0, &sysmgr_regs->iswgrp_handoff[2]); in populate_sysmgr_fpgaintf_module()
27 if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
29 if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
31 if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
33 if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
35 if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
37 if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
42 setbits_le32(&sysmgr_regs->iswgrp_handoff[2], handoff_val); in populate_sysmgr_fpgaintf_module()
44 handoff_val = readl(&sysmgr_regs->iswgrp_handoff[2]); in populate_sysmgr_fpgaintf_module()
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Dsystem_manager_s10.c13 static struct socfpga_system_manager *sysmgr_regs = variable
35 if (readl(&sysmgr_regs->nandusefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
37 if (readl(&sysmgr_regs->sdmmcusefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
39 if (readl(&sysmgr_regs->spim0usefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
41 if (readl(&sysmgr_regs->spim1usefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
43 writel(handoff_val, &sysmgr_regs->fpgaintf_en_2); in populate_sysmgr_fpgaintf_module()
46 if (readl(&sysmgr_regs->rgmii0usefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
48 if (readl(&sysmgr_regs->rgmii1usefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
50 if (readl(&sysmgr_regs->rgmii2usefpga) == SYSMGR_FPGAINTF_USEFPGA) in populate_sysmgr_fpgaintf_module()
52 writel(handoff_val, &sysmgr_regs->fpgaintf_en_3); in populate_sysmgr_fpgaintf_module()
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Dreset_manager_arria10.c20 static const struct socfpga_system_manager *sysmgr_regs = variable
103 setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc); in socfpga_reset_deassert_bridges_handoff()
109 return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc, in socfpga_reset_deassert_bridges_handoff()
197 &sysmgr_regs->noc_idlereq_set); in socfpga_bridges_reset()
200 writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK, &sysmgr_regs->noc_timeout); in socfpga_bridges_reset()
203 ret = wait_for_bit_le32(&sysmgr_regs->noc_idleack, in socfpga_bridges_reset()
215 ret = wait_for_bit_le32(&sysmgr_regs->noc_idlestatus, in socfpga_bridges_reset()
236 writel(0, &sysmgr_regs->noc_timeout); in socfpga_bridges_reset()
Dmisc_gen5.c31 static struct socfpga_system_manager *sysmgr_regs = variable
124 SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo)); in print_cpuinfo()
137 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7; in arch_misc_init()
195 writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable); in arch_early_init_r()
198 iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]); in arch_early_init_r()
226 readl(&sysmgr_regs->iswgrp_handoff[i]); in do_bridge_reset()
229 writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module); in do_bridge_reset()
237 writel(0, &sysmgr_regs->fpgaintfgrp_module); in do_bridge_reset()
Dwrap_pll_config_s10.c13 static const struct socfpga_system_manager *sysmgr_regs = variable
41 writel(clock, &sysmgr_regs->boot_scratch_cold1); in cm_get_osc_clk_hz()
43 return readl(&sysmgr_regs->boot_scratch_cold1); in cm_get_osc_clk_hz()
56 writel(clock, &sysmgr_regs->boot_scratch_cold2); in cm_get_fpga_clk_hz()
58 return readl(&sysmgr_regs->boot_scratch_cold2); in cm_get_fpga_clk_hz()
Dspl_gen5.c27 static const struct socfpga_system_manager *sysmgr_regs = variable
32 const u32 bsel = readl(&sysmgr_regs->bootinfo); in spl_boot_device()
74 reg = readl(&sysmgr_regs->eccgrp_ocram); in board_init_f()
77 &sysmgr_regs->eccgrp_ocram); in board_init_f()
80 &sysmgr_regs->eccgrp_ocram); in board_init_f()
Dmisc_arria10.c31 static struct socfpga_system_manager *sysmgr_regs = variable
84 writel(0x0007FFFF, &sysmgr_regs->ecc_intmask_set); in socfpga_init_security_policies()
109 SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo)); in print_cpuinfo()
Dspl_s10.c24 static struct socfpga_system_manager *sysmgr_regs = variable
125 writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg); in board_init_f()
158 writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma); in board_init_f()
159 writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph); in board_init_f()
Dreset_manager_gen5.c15 static const struct socfpga_system_manager *sysmgr_regs = variable
86 writel(brgmask, &sysmgr_regs->iswgrp_handoff[0]); in socfpga_bridges_set_handoff_regs()
87 writel(l3rmask, &sysmgr_regs->iswgrp_handoff[1]); in socfpga_bridges_set_handoff_regs()
Dspl_a10.c35 static const struct socfpga_system_manager *sysmgr_regs = variable
40 const u32 bsel = readl(&sysmgr_regs->bootinfo); in spl_boot_device()
Dmisc_s10.c26 static struct socfpga_system_manager *sysmgr_regs = variable
71 clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index, in socfpga_phymode_setup()
Dmailbox_s10.c290 static const struct socfpga_system_manager *sysmgr_regs = in mbox_qspi_open() local
321 writel(resp_buf[0], &sysmgr_regs->boot_scratch_cold0); in mbox_qspi_open()
Dclock_manager_s10.c17 static const struct socfpga_system_manager *sysmgr_regs = variable
354 return readl(&sysmgr_regs->boot_scratch_cold0); in cm_get_qspi_controller_clk_hz()
/third_party/uboot/u-boot-2020.01/drivers/fpga/
Dsocfpga_gen5.c18 static struct socfpga_system_manager *sysmgr_regs = variable
217 writel(0, &sysmgr_regs->fpgaintfgrp_module); in socfpga_load()
/third_party/uboot/u-boot-2020.01/drivers/ddr/altera/
Dsdram_gen5.c43 static struct socfpga_system_manager *sysmgr_regs = variable
458 writel(rows, &sysmgr_regs->iswgrp_handoff[4]); in sdram_mmr_init_full()
463 writel(cfg->fpgaport_rst, &sysmgr_regs->iswgrp_handoff[3]); in sdram_mmr_init_full()
519 row = readl(&sysmgr_regs->iswgrp_handoff[4]); in sdram_calculate_size()
Dsdram_s10.c36 static const struct socfpga_system_manager *sysmgr_regs = variable
154 return wait_for_bit_le32(&sysmgr_regs->hmc_clk, in poll_hmc_clock_status()