1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2012-2017 Altera Corporation <www.altera.com>
4 */
5
6 #include <common.h>
7 #include <asm/io.h>
8 #include <env.h>
9 #include <errno.h>
10 #include <fdtdec.h>
11 #include <linux/libfdt.h>
12 #include <altera.h>
13 #include <miiphy.h>
14 #include <netdev.h>
15 #include <watchdog.h>
16 #include <asm/arch/misc.h>
17 #include <asm/arch/reset_manager.h>
18 #include <asm/arch/scan_manager.h>
19 #include <asm/arch/sdram.h>
20 #include <asm/arch/system_manager.h>
21 #include <asm/arch/nic301.h>
22 #include <asm/arch/scu.h>
23 #include <asm/pl310.h>
24
25 #include <dt-bindings/reset/altr,rst-mgr.h>
26
27 DECLARE_GLOBAL_DATA_PTR;
28
29 static struct pl310_regs *const pl310 =
30 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
31 static struct socfpga_system_manager *sysmgr_regs =
32 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
33 static struct nic301_registers *nic301_regs =
34 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
35 static struct scu_registers *scu_regs =
36 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
37
38 /*
39 * FPGA programming support for SoC FPGA Cyclone V
40 */
41 static Altera_desc altera_fpga[] = {
42 {
43 /* Family */
44 Altera_SoCFPGA,
45 /* Interface type */
46 fast_passive_parallel,
47 /* No limitation as additional data will be ignored */
48 -1,
49 /* No device function table */
50 NULL,
51 /* Base interface address specified in driver */
52 NULL,
53 /* No cookie implementation */
54 0
55 },
56 };
57
58 static const struct {
59 const u16 pn;
60 const char *name;
61 const char *var;
62 } socfpga_fpga_model[] = {
63 /* Cyclone V E */
64 { 0x2b15, "Cyclone V, E/A2", "cv_e_a2" },
65 { 0x2b05, "Cyclone V, E/A4", "cv_e_a4" },
66 { 0x2b22, "Cyclone V, E/A5", "cv_e_a5" },
67 { 0x2b13, "Cyclone V, E/A7", "cv_e_a7" },
68 { 0x2b14, "Cyclone V, E/A9", "cv_e_a9" },
69 /* Cyclone V GX/GT */
70 { 0x2b01, "Cyclone V, GX/C3", "cv_gx_c3" },
71 { 0x2b12, "Cyclone V, GX/C4", "cv_gx_c4" },
72 { 0x2b02, "Cyclone V, GX/C5 or GT/D5", "cv_gx_c5" },
73 { 0x2b03, "Cyclone V, GX/C7 or GT/D7", "cv_gx_c7" },
74 { 0x2b04, "Cyclone V, GX/C9 or GT/D9", "cv_gx_c9" },
75 /* Cyclone V SE/SX/ST */
76 { 0x2d11, "Cyclone V, SE/A2 or SX/C2", "cv_se_a2" },
77 { 0x2d01, "Cyclone V, SE/A4 or SX/C4", "cv_se_a4" },
78 { 0x2d12, "Cyclone V, SE/A5 or SX/C5 or ST/D5", "cv_se_a5" },
79 { 0x2d02, "Cyclone V, SE/A6 or SX/C6 or ST/D6", "cv_se_a6" },
80 /* Arria V */
81 { 0x2d03, "Arria V, D5", "av_d5" },
82 /* Arria V ST/SX */
83 { 0x2d13, "Arria V, ST/D3 or SX/B3", "av_st_d3" },
84 };
85
socfpga_fpga_id(const bool print_id)86 static int socfpga_fpga_id(const bool print_id)
87 {
88 const u32 altera_mi = 0x6e;
89 const u32 id = scan_mgr_get_fpga_id();
90
91 const u32 lsb = id & 0x00000001;
92 const u32 mi = (id >> 1) & 0x000007ff;
93 const u32 pn = (id >> 12) & 0x0000ffff;
94 const u32 version = (id >> 28) & 0x0000000f;
95 int i;
96
97 if ((mi != altera_mi) || (lsb != 1)) {
98 printf("FPGA: Not Altera chip ID\n");
99 return -EINVAL;
100 }
101
102 for (i = 0; i < ARRAY_SIZE(socfpga_fpga_model); i++)
103 if (pn == socfpga_fpga_model[i].pn)
104 break;
105
106 if (i == ARRAY_SIZE(socfpga_fpga_model)) {
107 printf("FPGA: Unknown Altera chip, ID 0x%08x\n", id);
108 return -EINVAL;
109 }
110
111 if (print_id)
112 printf("FPGA: Altera %s, version 0x%01x\n",
113 socfpga_fpga_model[i].name, version);
114 return i;
115 }
116
117 /*
118 * Print CPU information
119 */
120 #if defined(CONFIG_DISPLAY_CPUINFO)
print_cpuinfo(void)121 int print_cpuinfo(void)
122 {
123 const u32 bsel =
124 SYSMGR_GET_BOOTINFO_BSEL(readl(&sysmgr_regs->bootinfo));
125
126 puts("CPU: Altera SoCFPGA Platform\n");
127 socfpga_fpga_id(1);
128
129 printf("BOOT: %s\n", bsel_str[bsel].name);
130 return 0;
131 }
132 #endif
133
134 #ifdef CONFIG_ARCH_MISC_INIT
arch_misc_init(void)135 int arch_misc_init(void)
136 {
137 const u32 bsel = readl(&sysmgr_regs->bootinfo) & 0x7;
138 const int fpga_id = socfpga_fpga_id(0);
139 env_set("bootmode", bsel_str[bsel].mode);
140 if (fpga_id >= 0)
141 env_set("fpgatype", socfpga_fpga_model[fpga_id].var);
142 return 0;
143 }
144 #endif
145
146 /*
147 * Convert all NIC-301 AMBA slaves from secure to non-secure
148 */
socfpga_nic301_slave_ns(void)149 static void socfpga_nic301_slave_ns(void)
150 {
151 writel(0x1, &nic301_regs->lwhps2fpgaregs);
152 writel(0x1, &nic301_regs->hps2fpgaregs);
153 writel(0x1, &nic301_regs->acp);
154 writel(0x1, &nic301_regs->rom);
155 writel(0x1, &nic301_regs->ocram);
156 writel(0x1, &nic301_regs->sdrdata);
157 }
158
socfpga_sdram_remap_zero(void)159 void socfpga_sdram_remap_zero(void)
160 {
161 u32 remap;
162
163 socfpga_nic301_slave_ns();
164
165 /*
166 * Private components security:
167 * U-Boot : configure private timer, global timer and cpu component
168 * access as non secure for kernel stage (as required by Linux)
169 */
170 setbits_le32(&scu_regs->sacr, 0xfff);
171
172 /* Configure the L2 controller to make SDRAM start at 0 */
173 remap = 0x1; /* remap.mpuzero */
174 /* Keep fpga bridge enabled when running from FPGA onchip RAM */
175 if (socfpga_is_booting_from_fpga())
176 remap |= 0x8; /* remap.hps2fpga */
177 writel(remap, &nic301_regs->remap);
178
179 writel(0x1, &pl310->pl310_addr_filter_start);
180 }
181
182 static u32 iswgrp_handoff[8];
183
arch_early_init_r(void)184 int arch_early_init_r(void)
185 {
186 int i;
187
188 /*
189 * Write magic value into magic register to unlock support for
190 * issuing warm reset. The ancient kernel code expects this
191 * value to be written into the register by the bootloader, so
192 * to support that old code, we write it here instead of in the
193 * reset_cpu() function just before resetting the CPU.
194 */
195 writel(0xae9efebc, &sysmgr_regs->romcodegrp_warmramgrp_enable);
196
197 for (i = 0; i < 8; i++) /* Cache initial SW setting regs */
198 iswgrp_handoff[i] = readl(&sysmgr_regs->iswgrp_handoff[i]);
199
200 socfpga_bridges_reset(1);
201
202 socfpga_sdram_remap_zero();
203
204 /* Add device descriptor to FPGA device table */
205 socfpga_fpga_add(&altera_fpga[0]);
206
207 return 0;
208 }
209
210 #ifndef CONFIG_SPL_BUILD
211 static struct socfpga_reset_manager *reset_manager_base =
212 (struct socfpga_reset_manager *)SOCFPGA_RSTMGR_ADDRESS;
213 static struct socfpga_sdr_ctrl *sdr_ctrl =
214 (struct socfpga_sdr_ctrl *)SDR_CTRLGRP_ADDRESS;
215
do_bridge_reset(int enable,unsigned int mask)216 void do_bridge_reset(int enable, unsigned int mask)
217 {
218 int i;
219
220 if (enable) {
221 socfpga_bridges_set_handoff_regs(!(mask & BIT(0)),
222 !(mask & BIT(1)),
223 !(mask & BIT(2)));
224 for (i = 0; i < 2; i++) { /* Reload SW setting cache */
225 iswgrp_handoff[i] =
226 readl(&sysmgr_regs->iswgrp_handoff[i]);
227 }
228
229 writel(iswgrp_handoff[2], &sysmgr_regs->fpgaintfgrp_module);
230 writel(iswgrp_handoff[3], &sdr_ctrl->fpgaport_rst);
231 writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
232 writel(iswgrp_handoff[1], &nic301_regs->remap);
233
234 writel(0x7, &reset_manager_base->brg_mod_reset);
235 writel(iswgrp_handoff[0], &reset_manager_base->brg_mod_reset);
236 } else {
237 writel(0, &sysmgr_regs->fpgaintfgrp_module);
238 writel(0, &sdr_ctrl->fpgaport_rst);
239 writel(0x7, &reset_manager_base->brg_mod_reset);
240 writel(1, &nic301_regs->remap);
241 }
242 }
243 #endif
244