Searched refs:timing_cfg_5 (Results 1 – 21 of 21) sorted by relevance
| /third_party/uboot/u-boot-2020.01/board/freescale/corenet_ds/ |
| D | p4080ds_ddr.c | 102 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
134 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
166 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
198 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
230 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
262 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
294 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
326 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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| /third_party/uboot/u-boot-2020.01/board/freescale/bsc9132qds/ |
| D | spl_minimal.c | 39 __raw_writel(CONFIG_SYS_DDR_TIMING_5_800, &ddr->timing_cfg_5); in sdram_init()
59 __raw_writel(CONFIG_SYS_DDR_TIMING_5_1333, &ddr->timing_cfg_5); in sdram_init()
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| D | ddr.c | 37 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
64 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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| /third_party/uboot/u-boot-2020.01/board/freescale/p1010rdb/ |
| D | ddr.c | 40 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
67 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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| /third_party/uboot/u-boot-2020.01/board/freescale/p1_twr/ |
| D | ddr.c | 46 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, in fixed_sdram()
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| /third_party/uboot/u-boot-2020.01/board/freescale/ls1043ardb/ |
| D | ddr.h | 88 .timing_cfg_5 = 0x03401400,
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| /third_party/uboot/u-boot-2020.01/drivers/ddr/fsl/ |
| D | arm_ddr_gen3.c | 108 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); in fsl_ddr_set_memctl_regs()
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| D | mpc85xx_ddr_gen3.c | 131 out_be32(&ddr->timing_cfg_5, regs->timing_cfg_5); in fsl_ddr_set_memctl_regs()
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| D | fsl_ddr_gen4.c | 161 ddr_out32(&ddr->timing_cfg_5, regs->timing_cfg_5); in fsl_ddr_set_memctl_regs()
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| D | ctrl_regs.c | 1967 ddr->timing_cfg_5 = (0 in set_timing_cfg_5()
1973 debug("FSLDDR: timing_cfg_5 = 0x%08x\n", ddr->timing_cfg_5); in set_timing_cfg_5()
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| D | interactive.c | 660 CFG_REGS(timing_cfg_5), in print_fsl_memctl_config_regs()
751 CFG_REGS(timing_cfg_5), in fsl_ddr_regs_edit()
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| /third_party/uboot/u-boot-2020.01/board/freescale/bsc9131rdb/ |
| D | spl_minimal.c | 46 __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); in sdram_init()
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| D | ddr.c | 38 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
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| /third_party/uboot/u-boot-2020.01/board/Arcturus/ucp1020/ |
| D | ddr.c | 106 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, in fixed_sdram()
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| /third_party/uboot/u-boot-2020.01/board/freescale/ls1021atsn/ |
| D | ls1021atsn.c | 39 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); in ddrmc_init()
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| /third_party/uboot/u-boot-2020.01/board/freescale/ls1021aiot/ |
| D | ls1021aiot.c | 61 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); in ddrmc_init()
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| /third_party/uboot/u-boot-2020.01/board/freescale/p1_p2_rdb_pc/ |
| D | ddr.c | 238 .timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5, in fixed_sdram()
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| /third_party/uboot/u-boot-2020.01/include/ |
| D | fsl_immap.h | 51 u32 timing_cfg_5; /* SDRAM Timing Configuration 5 */ member
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| D | fsl_ddr_sdram.h | 278 unsigned int timing_cfg_5; member
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| /third_party/uboot/u-boot-2020.01/board/freescale/mpc8569mds/ |
| D | mpc8569mds.c | 253 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); in fixed_sdram()
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| /third_party/uboot/u-boot-2020.01/board/freescale/ls1021atwr/ |
| D | ls1021atwr.c | 153 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5); in ddrmc_init()
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