1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2016-2019 NXP Semiconductors
3 */
4 #include <common.h>
5 #include <init.h>
6 #include <asm/arch-ls102xa/ls102xa_soc.h>
7 #include <asm/arch/ls102xa_devdis.h>
8 #include <asm/arch/immap_ls102xa.h>
9 #include <asm/arch/ls102xa_soc.h>
10 #include <asm/arch/fsl_serdes.h>
11 #include "../common/sleep.h"
12 #include <fsl_validate.h>
13 #include <fsl_immap.h>
14 #include <fsl_csu.h>
15 #include <netdev.h>
16 #include <spl.h>
17 #ifdef CONFIG_U_QE
18 #include <fsl_qe.h>
19 #endif
20
21 DECLARE_GLOBAL_DATA_PTR;
22
ddrmc_init(void)23 static void ddrmc_init(void)
24 {
25 #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
26 struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR;
27 u32 temp_sdram_cfg, tmp;
28
29 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
30
31 out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
32 out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
33
34 out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
35 out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
36 out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
37 out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
38 out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
39 out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
40
41 #ifdef CONFIG_DEEP_SLEEP
42 if (is_warm_boot()) {
43 out_be32(&ddr->sdram_cfg_2,
44 DDR_SDRAM_CFG_2 & ~SDRAM_CFG2_D_INIT);
45 out_be32(&ddr->init_addr, CONFIG_SYS_SDRAM_BASE);
46 out_be32(&ddr->init_ext_addr, (1 << 31));
47
48 /* DRAM VRef will not be trained */
49 out_be32(&ddr->ddr_cdr2,
50 DDR_DDR_CDR2 & ~DDR_CDR2_VREF_TRAIN_EN);
51 } else
52 #endif
53 {
54 out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
55 out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
56 }
57
58 out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
59 out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
60
61 out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
62
63 out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
64
65 out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
66 out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
67
68 out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
69
70 out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
71 out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
72
73 out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
74
75 /* DDR erratum A-009942 */
76 tmp = in_be32(&ddr->debug[28]);
77 out_be32(&ddr->debug[28], tmp | 0x0070006f);
78
79 udelay(1);
80
81 #ifdef CONFIG_DEEP_SLEEP
82 if (is_warm_boot()) {
83 /* enter self-refresh */
84 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
85 temp_sdram_cfg |= SDRAM_CFG2_FRC_SR;
86 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
87
88 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN | SDRAM_CFG_BI);
89 } else
90 #endif
91 temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
92
93 out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
94
95 #ifdef CONFIG_DEEP_SLEEP
96 if (is_warm_boot()) {
97 /* exit self-refresh */
98 temp_sdram_cfg = in_be32(&ddr->sdram_cfg_2);
99 temp_sdram_cfg &= ~SDRAM_CFG2_FRC_SR;
100 out_be32(&ddr->sdram_cfg_2, temp_sdram_cfg);
101 }
102 #endif
103 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
104 }
105
dram_init(void)106 int dram_init(void)
107 {
108 ddrmc_init();
109
110 erratum_a008850_post();
111
112 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
113
114 #if defined(CONFIG_DEEP_SLEEP) && !defined(CONFIG_SPL_BUILD)
115 fsl_dp_resume();
116 #endif
117
118 return 0;
119 }
120
board_eth_init(bd_t * bis)121 int board_eth_init(bd_t *bis)
122 {
123 return pci_eth_init(bis);
124 }
125
board_early_init_f(void)126 int board_early_init_f(void)
127 {
128 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
129
130 #ifdef CONFIG_TSEC_ENET
131 /*
132 * Clear BD & FR bits for big endian BD's and frame data (aka set
133 * correct eTSEC endianness). This is crucial in ensuring that it does
134 * not report Data Parity Errors in its RX/TX FIFOs when attempting to
135 * send traffic.
136 */
137 clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
138 /* EC3_GTX_CLK125 (of enet2) used for all RGMII interfaces */
139 out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
140 #endif
141
142 arch_soc_init();
143
144 #if defined(CONFIG_DEEP_SLEEP)
145 if (is_warm_boot()) {
146 timer_init();
147 dram_init();
148 }
149 #endif
150
151 return 0;
152 }
153
154 #ifdef CONFIG_SPL_BUILD
board_init_f(ulong dummy)155 void board_init_f(ulong dummy)
156 {
157 void (*second_uboot)(void);
158
159 /* Clear the BSS */
160 memset(__bss_start, 0, __bss_end - __bss_start);
161
162 get_clocks();
163
164 #if defined(CONFIG_DEEP_SLEEP)
165 if (is_warm_boot())
166 fsl_dp_disable_console();
167 #endif
168
169 preloader_console_init();
170
171 dram_init();
172
173 /* Allow OCRAM access permission as R/W */
174 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
175 enable_layerscape_ns_access();
176 enable_layerscape_ns_access();
177 #endif
178
179 /*
180 * if it is woken up from deep sleep, then jump to second
181 * stage U-Boot and continue executing without recopying
182 * it from SD since it has already been reserved in memory
183 * in last boot.
184 */
185 if (is_warm_boot()) {
186 second_uboot = (void (*)(void))CONFIG_SYS_TEXT_BASE;
187 second_uboot();
188 }
189
190 board_init_r(NULL, 0);
191 }
192 #endif
193
board_init(void)194 int board_init(void)
195 {
196 #ifndef CONFIG_SYS_FSL_NO_SERDES
197 fsl_serdes_init();
198 #endif
199 ls102xa_smmu_stream_id_init();
200
201 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
202 enable_layerscape_ns_access();
203 #endif
204
205 #ifdef CONFIG_U_QE
206 u_qe_init();
207 #endif
208
209 return 0;
210 }
211
212 #if defined(CONFIG_SPL_BUILD)
spl_board_init(void)213 void spl_board_init(void)
214 {
215 ls102xa_smmu_stream_id_init();
216 }
217 #endif
218
219 #ifdef CONFIG_BOARD_LATE_INIT
board_late_init(void)220 int board_late_init(void)
221 {
222 #ifdef CONFIG_CHAIN_OF_TRUST
223 fsl_setenv_chain_of_trust();
224 #endif
225
226 return 0;
227 }
228 #endif
229
230 #if defined(CONFIG_MISC_INIT_R)
misc_init_r(void)231 int misc_init_r(void)
232 {
233 #ifdef CONFIG_FSL_DEVICE_DISABLE
234 device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
235 #endif
236
237 #ifdef CONFIG_FSL_CAAM
238 return sec_init();
239 #endif
240 }
241 #endif
242
243 #if defined(CONFIG_DEEP_SLEEP)
board_sleep_prepare(void)244 void board_sleep_prepare(void)
245 {
246 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
247 enable_layerscape_ns_access();
248 #endif
249 }
250 #endif
251
ft_board_setup(void * blob,bd_t * bd)252 int ft_board_setup(void *blob, bd_t *bd)
253 {
254 ft_cpu_setup(blob, bd);
255
256 #ifdef CONFIG_PCI
257 ft_pci_setup(blob, bd);
258 #endif
259
260 return 0;
261 }
262