1 /* 2 * Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef _TARGET_CONFIG_H 17 #define _TARGET_CONFIG_H 18 19 20 #ifdef __cplusplus 21 #if __cplusplus 22 extern "C" { 23 #endif /* __cplusplus */ 24 #endif /* __cplusplus */ 25 26 #define OS_SYS_CLOCK 50000000 27 #define SYS_CTRL_REG_BASE IO_DEVICE_ADDR(0x12020000) 28 #define REG_SC_CTRL 0 29 30 /* memory */ 31 #define CACHE_ALIGNED_SIZE 64 32 33 /* physical memory base and size */ 34 #define DDR_MEM_ADDR 0x40000000 35 #define DDR_MEM_SIZE 0x04000000 36 37 /* Peripheral register address base and size */ 38 #define PERIPH_PMM_BASE 0x10000000 39 #define PERIPH_PMM_SIZE 0x10000000 40 41 #define SYS_MEM_SIZE_DEFAULT 0x2000000 42 43 44 /* hwi */ 45 /** 46 * Maximum number of supported hardware devices that generate hardware interrupts. 47 * The maximum number of hardware devices that generate hardware interrupts is 128. 48 */ 49 #define OS_HWI_MAX_NUM 96 50 51 /** 52 * Maximum interrupt number. 53 */ 54 #define OS_HWI_MAX ((OS_HWI_MAX_NUM) - 1) 55 56 /** 57 * Minimum interrupt number. 58 */ 59 #define OS_HWI_MIN 0 60 /** 61 * Maximum usable interrupt number. 62 */ 63 #define OS_USER_HWI_MAX OS_HWI_MAX 64 /** 65 * Minimum usable interrupt number. 66 */ 67 #define OS_USER_HWI_MIN OS_HWI_MIN 68 69 #define NUM_HAL_INTERRUPT_CNTPSIRQ 29 70 #define NUM_HAL_INTERRUPT_CNTPNSIRQ 30 71 #define OS_TICK_INT_NUM NUM_HAL_INTERRUPT_CNTPSIRQ // use secure physical timer for now 72 #define NUM_HAL_INTERRUPT_TIMER0 37 73 #define NUM_HAL_INTERRUPT_TIMER3 38 74 #define NUM_HAL_INTERRUPT_UART0 39 75 76 /* gic config */ 77 #define GIC_BASE_ADDR IO_DEVICE_ADDR(0x10300000) 78 #define GICD_OFFSET 0x1000 /* interrupt distributor offset */ 79 #define GICC_OFFSET 0x2000 /* CPU interface register offset */ 80 81 /* timer config */ 82 #define BIT(n) (1U << (n)) 83 #define TIMER0_ENABLE BIT(16) 84 #define TIMER1_ENABLE BIT(17) 85 #define TIMER2_ENABLE BIT(18) 86 #define TIMER3_ENABLE BIT(19) 87 88 #define TIMER0_REG_BASE IO_DEVICE_ADDR(0x12000000) 89 #define TIMER1_REG_BASE IO_DEVICE_ADDR(0x12000020) 90 #define TIMER2_REG_BASE IO_DEVICE_ADDR(0x12001000) 91 #define TIMER3_REG_BASE IO_DEVICE_ADDR(0x12001020) 92 93 #define TIMER_TICK_REG_BASE TIMER0_REG_BASE /* timer for tick */ 94 #define TIMER_TICK_ENABLE TIMER0_ENABLE 95 #define TIMER_TIME_REG_BASE TIMER1_REG_BASE /* timer for time */ 96 #define TIMER_TIME_ENABLE TIMER1_ENABLE 97 #define HRTIMER_TIMER_REG_BASE TIMER3_REG_BASE /* timer for hrtimer */ 98 #define HRTIMER_TIMER_ENABLE TIMER3_ENABLE 99 100 #define NUM_HAL_INTERRUPT_TIMER NUM_HAL_INTERRUPT_TIMER0 101 #define NUM_HAL_INTERRUPT_HRTIMER NUM_HAL_INTERRUPT_TIMER3 102 103 #define TIMER_LOAD 0x0 104 #define TIMER_VALUE 0x4 105 #define TIMER_CONTROL 0x8 106 #define TIMER_INT_CLR 0xc 107 #define TIMER_RIS 0x10 108 #define TIMER_MIS 0x14 109 #define TIMER_BGLOAD 0x18 110 111 /* uart config */ 112 #define UART0_REG_BASE IO_DEVICE_ADDR(0x12040000) 113 #define TTY_DEVICE "/dev/uartdev-0" 114 #define UART_REG_BASE UART0_REG_BASE 115 #define NUM_HAL_INTERRUPT_UART NUM_HAL_INTERRUPT_UART0 116 117 #ifdef __cplusplus 118 #if __cplusplus 119 } 120 #endif /* __cplusplus */ 121 #endif /* __cplusplus */ 122 123 #endif 124