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1// SPDX-License-Identifier: GPL-2.0
2
3// Copyright (c) 2020 HiSilicon (Shanghai) Technologies CO., LIMITED.
4
5#include <platform.h>
6
7/*
8 *************************************************************************
9 *
10 * Jump vector table as in table 3.1 in [1]
11 *
12 *************************************************************************
13 */
14
15.globl _start
16_start:
17	b       reset
18	ldr     pc, _undefined_instruction
19	ldr     pc, _software_interrupt
20	ldr     pc, _prefetch_abort
21	ldr     pc, _data_abort
22	ldr     pc, _not_used
23	ldr     pc, _irq
24	ldr     pc, _fiq
25
26_undefined_instruction: .word undefined_instruction
27_software_interrupt:    .word software_interrupt
28_prefetch_abort:        .word prefetch_abort
29_data_abort:            .word data_abort
30_not_used:              .word not_used
31_irq:                   .word irq
32_fiq:                   .word fiq
33_pad:                   .word 0x12345678 /* now 16*4=64 */
34__blank_zone_start:
35.fill 1024*8,1,0
36__blank_zone_end:
37
38.globl _blank_zone_start
39_blank_zone_start:
40.word __blank_zone_start
41
42
43.globl _blank_zone_end
44_blank_zone_end:
45.word __blank_zone_end
46
47.balignl 16,0xdeadbeef
48
49
50_TEXT_BASE:
51        .word   TEXT_BASE
52
53
54	/*
55	 * the actual reset code
56	 */
57
58reset:
59
60    /*
61     * disable interrupts (FIQ and IRQ), also set the cpu to SVC32 mode,
62     * except if in HYP mode already
63     */
64    mrs r0, cpsr
65    and r1, r0, #0x1f       @ mask mode bits
66    teq r1, #0x1a       @ test for HYP mode
67    bicne   r0, r0, #0x1f       @ clear all mode bits
68    orrne   r0, r0, #0x13       @ set SVC mode
69    orr r0, r0, #0xc0       @ disable FIQ and IRQ
70    msr cpsr,r0
71
72/*************************************************************************
73 *
74 * Setup CP15 registers (cache, MMU, TLBs). The I-cache is turned on unless
75 * CONFIG_SYS_ICACHE_OFF is defined.
76 *
77 *************************************************************************/
78    /*
79     * Invalidate L1 I/D
80     */
81    mov r0, #0          @ set up for MCR
82    mcr p15, 0, r0, c8, c7, 0   @ invalidate TLBs
83    mcr p15, 0, r0, c7, c5, 0   @ invalidate icache
84    mcr p15, 0, r0, c7, c5, 6   @ invalidate BP array
85    mcr     p15, 0, r0, c7, c10, 4  @ DSB
86    mcr     p15, 0, r0, c7, c5, 4   @ ISB
87
88    /*
89     * disable MMU stuff and caches
90     */
91    mrc p15, 0, r0, c1, c0, 0
92    bic r0, r0, #0x00002000 @ clear bits 13 (--V-)
93    bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM)
94    orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align
95    orr r0, r0, #0x00000800 @ set bit 11 (Z---) BTB
96#ifdef CONFIG_SYS_ICACHE_OFF
97    bic r0, r0, #0x00001000 @ clear bit 12 (I) I-cache
98#else
99    orr r0, r0, #0x00001000 @ set bit 12 (I) I-cache
100#endif
101    mcr p15, 0, r0, c1, c0, 0
102
103	/*
104	 *  read system register REG_SC_GEN2
105         *  check if ziju flag
106	 */
107	ldr	r0, =SYS_CTRL_REG_BASE
108	mov	r1, sp                   /* save sp */
109	str	r1, [r0, #REG_SC_GEN2]  /* clear ziju flag */
110
111	/* init PLL/DDRC/pin mux/... */
112	ldr	r0, _blank_zone_start
113	ldr	r1, _TEXT_BASE
114	sub	r0, r0, r1
115
116	@ldr	r1, =RAM_START_ADRS
117	ldr	sp, =STACK_TRAINING
118
119	adrl	r1, _start
120	add	r0, r0, r1
121	mov	r1, #0x0                 /* flags: 0->normal 1->pm */
122	bl	init_registers           /* init PLL/DDRC/... */
123
124	/* after ziju, we need ddr traning */
125	ldr	r0, =REG_BASE_SCTL
126	bl	start_ddr_training       /* DDR training */
127
128	ldr	r0, =SYS_CTRL_REG_BASE
129	ldr	r1, [r0, #REG_SC_GEN2]
130	mov	sp, r1		        /* restore sp */
131	ldr	r1, [r0, #REG_SC_GEN3]
132	mov	pc, r1				/* return to bootrom */
133	nop
134	nop
135	nop
136	nop
137	nop
138	nop
139	nop
140	nop
141	b	.                        /* bug here */
142
143.global reset_cpu
144reset_cpu:
145    ldr r1, rstctl          @ get addr for global reset
146                        @ reg
147    mov r3, #0x2            @ full reset pll + mpu
148    str r3, [r1]            @ force reset
149    mov r0, r0
150
151_loop_forever:
152    b   _loop_forever
153rstctl:
154    .word  0x12020004
155
156@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
157@
158@       void memcpy(r1, r0, r2);
159@
160.align  2
161memcpy:
162	add     r2, r0, r2
163memcpy_loop:
164	ldmia   r0!, {r3 - r10}
165	stmia   r1!, {r3 - r10}
166	cmp     r0, r2
167	ble     memcpy_loop
168	mov     pc, lr
169
170@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
171
172.align  2
173msg_main_cpu_startup:
174	mov     r5, lr
175	add     r0, pc, #4
176	bl      uart_early_puts
177	mov     pc, r5
178L10:
179#ifndef CONFIG_SUPPORT_CA_RELEASE
180	.ascii "\r\n\r\nSystem startup\r\n\0"
181#else
182	.ascii "\r\n\r\n\r\n\0"
183#endif
184
185/*
186 * exception handlers
187 */
188	.align	5
189undefined_instruction:
190software_interrupt:
191prefetch_abort:
192data_abort:
193not_used:
194irq:
195fiq:
196	/* reset */
197	ldr	r1, =REG_BASE_SCTL
198	ldr     r0, =1
199	str     r0, [r1, #REG_SC_SYSRES]
200	b       .
201
202/*#include "lowlevel_init.S"*/
203