1 /* 2 * Copyright (C) 2016 Rockchip Electronics Co., Ltd. 3 * Authors: 4 * Zhiqin Wei <wzq@rock-chips.com> 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 */ 18 19 #ifndef _RGA_DRIVER_H_ 20 #define _RGA_DRIVER_H_ 21 22 #include <stdint.h> 23 #ifdef __cplusplus 24 extern "C" 25 { 26 #endif 27 28 #define RGA_BLIT_SYNC 0x5017 29 #define RGA_BLIT_ASYNC 0x5018 30 #define RGA_FLUSH 0x5019 31 #define RGA_GET_RESULT 0x501a 32 #define RGA_GET_VERSION 0x501b 33 34 #define RGA2_BLIT_SYNC 0x6017 35 #define RGA2_BLIT_ASYNC 0x6018 36 #define RGA2_FLUSH 0x6019 37 #define RGA2_GET_RESULT 0x601a 38 #define RGA2_GET_VERSION 0x601b 39 #define RGA2_GET_VERSION 0x601b 40 41 #define RGA_REG_CTRL_LEN 0x8 /* 8 */ 42 #define RGA_REG_CMD_LEN 0x1c /* 28 */ 43 #define RGA_CMD_BUF_SIZE 0x700 /* 16*28*4 */ 44 45 46 47 #ifndef ENABLE 48 #define ENABLE 1 49 #endif 50 51 52 #ifndef DISABLE 53 #define DISABLE 0 54 #endif 55 56 57 58 /* RGA process mode enum */ 59 enum { 60 bitblt_mode = 0x0, 61 color_palette_mode = 0x1, 62 color_fill_mode = 0x2, 63 line_point_drawing_mode = 0x3, 64 blur_sharp_filter_mode = 0x4, 65 pre_scaling_mode = 0x5, 66 update_palette_table_mode = 0x6, 67 update_patten_buff_mode = 0x7, 68 }; 69 70 71 enum { 72 rop_enable_mask = 0x2, 73 dither_enable_mask = 0x8, 74 fading_enable_mask = 0x10, 75 PD_enbale_mask = 0x20, 76 }; 77 78 enum { 79 yuv2rgb_mode0 = 0x0, /* BT.601 MPEG */ 80 yuv2rgb_mode1 = 0x1, /* BT.601 JPEG */ 81 yuv2rgb_mode2 = 0x2, /* BT.709 */ 82 83 rgb2yuv_601_full = 0x1 << 8, 84 rgb2yuv_709_full = 0x2 << 8, 85 yuv2yuv_601_limit_2_709_limit = 0x3 << 8, 86 yuv2yuv_601_limit_2_709_full = 0x4 << 8, 87 yuv2yuv_709_limit_2_601_limit = 0x5 << 8, 88 yuv2yuv_709_limit_2_601_full = 0x6 << 8, // not support 89 yuv2yuv_601_full_2_709_limit = 0x7 << 8, 90 yuv2yuv_601_full_2_709_full = 0x8 << 8, // not support 91 yuv2yuv_709_full_2_601_limit = 0x9 << 8, // not support 92 yuv2yuv_709_full_2_601_full = 0xa << 8, // not support 93 full_csc_mask = 0xf00, 94 }; 95 96 /* RGA rotate mode */ 97 enum { 98 rotate_mode0 = 0x0, /* no rotate */ 99 rotate_mode1 = 0x1, /* rotate */ 100 rotate_mode2 = 0x2, /* x_mirror */ 101 rotate_mode3 = 0x3, /* y_mirror */ 102 }; 103 104 enum { 105 color_palette_mode0 = 0x0, /* 1K */ 106 color_palette_mode1 = 0x1, /* 2K */ 107 color_palette_mode2 = 0x2, /* 4K */ 108 color_palette_mode3 = 0x3, /* 8K */ 109 }; 110 111 enum { 112 BB_BYPASS = 0x0, /* no rotate */ 113 BB_ROTATE = 0x1, /* rotate */ 114 BB_X_MIRROR = 0x2, /* x_mirror */ 115 BB_Y_MIRROR = 0x3 /* y_mirror */ 116 }; 117 118 enum { 119 nearby = 0x0, /* no rotate */ 120 bilinear = 0x1, /* rotate */ 121 bicubic = 0x2, /* x_mirror */ 122 }; 123 124 125 126 127 128 /* 129 // Alpha Red Green Blue 130 { 4, 32, {{32,24, 8, 0, 16, 8, 24,16 }}, GGL_RGBA }, // RK_FORMAT_RGBA_8888 131 { 4, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGBX_8888 132 { 3, 24, {{ 0, 0, 8, 0, 16, 8, 24,16 }}, GGL_RGB }, // RK_FORMAT_RGB_888 133 { 4, 32, {{32,24, 24,16, 16, 8, 8, 0 }}, GGL_BGRA }, // RK_FORMAT_BGRA_8888 134 { 2, 16, {{ 0, 0, 16,11, 11, 5, 5, 0 }}, GGL_RGB }, // RK_FORMAT_RGB_565 135 { 2, 16, {{ 1, 0, 16,11, 11, 6, 6, 1 }}, GGL_RGBA }, // RK_FORMAT_RGBA_5551 136 { 2, 16, {{ 4, 0, 16,12, 12, 8, 8, 4 }}, GGL_RGBA }, // RK_FORMAT_RGBA_4444 137 { 3, 24, {{ 0, 0, 24,16, 16, 8, 8, 0 }}, GGL_BGR }, // RK_FORMAT_BGB_888 138 139 */ 140 /* In order to be compatible with RK_FORMAT_XX and HAL_PIXEL_FORMAT_XX, 141 * RK_FORMAT_XX is shifted to the left by 8 bits to distinguish. */ 142 typedef enum _Rga_SURF_FORMAT { 143 RK_FORMAT_RGBA_8888 = 0x0 << 8, 144 RK_FORMAT_RGBX_8888 = 0x1 << 8, 145 RK_FORMAT_RGB_888 = 0x2 << 8, 146 RK_FORMAT_BGRA_8888 = 0x3 << 8, 147 RK_FORMAT_RGB_565 = 0x4 << 8, 148 RK_FORMAT_RGBA_5551 = 0x5 << 8, 149 RK_FORMAT_RGBA_4444 = 0x6 << 8, 150 RK_FORMAT_BGR_888 = 0x7 << 8, 151 152 RK_FORMAT_YCbCr_422_SP = 0x8 << 8, 153 RK_FORMAT_YCbCr_422_P = 0x9 << 8, 154 RK_FORMAT_YCbCr_420_SP = 0xa << 8, 155 RK_FORMAT_YCbCr_420_P = 0xb << 8, 156 157 RK_FORMAT_YCrCb_422_SP = 0xc << 8, 158 RK_FORMAT_YCrCb_422_P = 0xd << 8, 159 RK_FORMAT_YCrCb_420_SP = 0xe << 8, 160 RK_FORMAT_YCrCb_420_P = 0xf << 8, 161 162 RK_FORMAT_BPP1 = 0x10 << 8, 163 RK_FORMAT_BPP2 = 0x11 << 8, 164 RK_FORMAT_BPP4 = 0x12 << 8, 165 RK_FORMAT_BPP8 = 0x13 << 8, 166 167 RK_FORMAT_Y4 = 0x14 << 8, 168 RK_FORMAT_YCbCr_400 = 0x15 << 8, 169 170 RK_FORMAT_BGRX_8888 = 0x16 << 8, 171 172 RK_FORMAT_YVYU_422 = 0x18 << 8, 173 RK_FORMAT_YVYU_420 = 0x19 << 8, 174 RK_FORMAT_VYUY_422 = 0x1a << 8, 175 RK_FORMAT_VYUY_420 = 0x1b << 8, 176 RK_FORMAT_YUYV_422 = 0x1c << 8, 177 RK_FORMAT_YUYV_420 = 0x1d << 8, 178 RK_FORMAT_UYVY_422 = 0x1e << 8, 179 RK_FORMAT_UYVY_420 = 0x1f << 8, 180 181 RK_FORMAT_YCbCr_420_SP_10B = 0x20 << 8, 182 RK_FORMAT_YCrCb_420_SP_10B = 0x21 << 8, 183 RK_FORMAT_YCbCr_422_10b_SP = 0x22 << 8, 184 RK_FORMAT_YCrCb_422_10b_SP = 0x23 << 8, 185 186 RK_FORMAT_BGR_565 = 0x24 << 8, 187 RK_FORMAT_BGRA_5551 = 0x25 << 8, 188 RK_FORMAT_BGRA_4444 = 0x26 << 8, 189 RK_FORMAT_UNKNOWN = 0x100 << 8, 190 } RgaSURF_FORMAT; 191 192 193 typedef struct rga_img_info_t { 194 #if defined(__arm64__) || defined(__aarch64__) 195 unsigned long yrgb_addr; /* yrgb mem addr */ 196 unsigned long uv_addr; /* cb/cr mem addr */ 197 unsigned long v_addr; /* cr mem addr */ 198 #else 199 unsigned int yrgb_addr; /* yrgb mem addr */ 200 unsigned int uv_addr; /* cb/cr mem addr */ 201 unsigned int v_addr; /* cr mem addr */ 202 #endif 203 unsigned int format; // definition by RK_FORMAT 204 unsigned short act_w; 205 unsigned short act_h; 206 unsigned short x_offset; 207 unsigned short y_offset; 208 209 unsigned short vir_w; 210 unsigned short vir_h; 211 212 unsigned short endian_mode; // for BPP 213 unsigned short alpha_swap; 214 } 215 rga_img_info_t; 216 217 218 typedef struct mdp_img_act { 219 unsigned short w; // width 220 unsigned short h; // height 221 short x_off; // x offset for the vir 222 short y_off; // y offset for the vir 223 } 224 mdp_img_act; 225 226 227 228 typedef struct RANGE { 229 unsigned short min; 230 unsigned short max; 231 } 232 RANGE; 233 234 typedef struct POINT { 235 unsigned short x; 236 unsigned short y; 237 } 238 POINT; 239 240 typedef struct RECT { 241 unsigned short xmin; 242 unsigned short xmax; // width - 1 243 unsigned short ymin; 244 unsigned short ymax; // height - 1 245 } RECT; 246 247 typedef struct RGB { 248 unsigned char r; 249 unsigned char g; 250 unsigned char b; 251 unsigned char res; 252 }RGB; 253 254 255 typedef struct MMU { 256 unsigned char mmu_en; 257 #if defined(__arm64__) || defined(__aarch64__) 258 unsigned long base_addr; 259 #else 260 unsigned int base_addr; 261 #endif 262 unsigned int mmu_flag; /* [0] mmu enable [1] src_flush [2] dst_flush [3] CMD_flush [4~5] page size */ 263 } MMU; 264 265 typedef struct COLOR_FILL { 266 short gr_x_a; 267 short gr_y_a; 268 short gr_x_b; 269 short gr_y_b; 270 short gr_x_g; 271 short gr_y_g; 272 short gr_x_r; 273 short gr_y_r; 274 } 275 COLOR_FILL; 276 277 typedef struct FADING { 278 unsigned char b; 279 unsigned char g; 280 unsigned char r; 281 unsigned char res; 282 } 283 FADING; 284 285 286 typedef struct line_draw_t { 287 POINT start_point; /* LineDraw_start_point */ 288 POINT end_point; /* LineDraw_end_point */ 289 unsigned int color; /* LineDraw_color */ 290 unsigned int flag; /* (enum) LineDrawing mode sel */ 291 unsigned int line_width; /* range 1~16 */ 292 } 293 line_draw_t; 294 295 /* color space convert coefficient. */ 296 typedef struct csc_coe_t { 297 int16_t r_v; 298 int16_t g_y; 299 int16_t b_u; 300 int32_t off; 301 } csc_coe_t; 302 303 typedef struct full_csc_t { 304 unsigned char flag; 305 csc_coe_t coe_y; 306 csc_coe_t coe_u; 307 csc_coe_t coe_v; 308 } full_csc_t; 309 310 struct rga_req { 311 unsigned char render_mode; /* (enum) process mode sel */ 312 313 rga_img_info_t src; /* src image info */ 314 rga_img_info_t dst; /* dst image info */ 315 rga_img_info_t pat; /* patten image info */ 316 317 #if defined(__arm64__) || defined(__aarch64__) 318 unsigned long rop_mask_addr; /* rop4 mask addr */ 319 unsigned long LUT_addr; /* LUT addr */ 320 #else 321 unsigned int rop_mask_addr; /* rop4 mask addr */ 322 unsigned int LUT_addr; /* LUT addr */ 323 #endif 324 325 RECT clip; /* dst clip window default value is dst_vir */ 326 /* value from [0, w-1] / [0, h-1] */ 327 328 int sina; /* dst angle default value 0 16.16 scan from table */ 329 int cosa; /* dst angle default value 0 16.16 scan from table */ 330 331 unsigned short alpha_rop_flag; /* alpha rop process flag */ 332 /* ([0] = 1 alpha_rop_enable) */ 333 /* ([1] = 1 rop enable) */ 334 /* ([2] = 1 fading_enable) */ 335 /* ([3] = 1 PD_enable) */ 336 /* ([4] = 1 alpha cal_mode_sel) */ 337 /* ([5] = 1 dither_enable) */ 338 /* ([6] = 1 gradient fill mode sel) */ 339 /* ([7] = 1 AA_enable) */ 340 /* ([8] = 1 nn_quantize) */ 341 /* ([9] = 1 Real color mode) */ 342 343 unsigned char scale_mode; /* 0 nearst / 1 bilnear / 2 bicubic */ 344 345 unsigned int color_key_max; /* color key max */ 346 unsigned int color_key_min; /* color key min */ 347 348 unsigned int fg_color; /* foreground color */ 349 unsigned int bg_color; /* background color */ 350 351 COLOR_FILL gr_color; /* color fill use gradient */ 352 353 line_draw_t line_draw_info; 354 355 FADING fading; 356 357 unsigned char PD_mode; /* porter duff alpha mode sel */ 358 359 unsigned char alpha_global_value; /* global alpha value */ 360 361 unsigned short rop_code; /* rop2/3/4 code scan from rop code table */ 362 363 unsigned char bsfilter_flag; /* [2] 0 blur 1 sharp / [1:0] filter_type */ 364 365 unsigned char palette_mode; /* (enum) color palatte 0/1bpp, 1/2bpp 2/4bpp 3/8bpp */ 366 367 unsigned char yuv2rgb_mode; /* (enum) BT.601 MPEG / BT.601 JPEG / BT.709 */ 368 369 unsigned char endian_mode; /* 0/big endian 1/little endian */ 370 371 unsigned char rotate_mode; /* (enum) rotate mode */ 372 /* 0x0, no rotate */ 373 /* 0x1, rotate */ 374 /* 0x2, x_mirror */ 375 /* 0x3, y_mirror */ 376 377 unsigned char color_fill_mode; /* 0 solid color / 1 patten color */ 378 379 MMU mmu_info; /* mmu information */ 380 381 unsigned char alpha_rop_mode; /* ([0~1] alpha mode) */ 382 /* ([2~3] rop mode) */ 383 /* ([4] zero mode en) */ 384 /* ([5] dst alpha mode) (RGA1) */ 385 386 unsigned char src_trans_mode; 387 388 unsigned char dither_mode; 389 390 full_csc_t full_csc; /* full color space convert */ 391 392 unsigned char CMD_fin_int_enable; 393 394 /* completion is reported through a callback */ 395 void (*complete)(int retval); 396 }; 397 398 int RGA_set_src_act_info( 399 struct rga_req *req, 400 unsigned int width, /* act width */ 401 unsigned int height, /* act height */ 402 unsigned int x_off, /* x_off */ 403 unsigned int y_off /* y_off */ 404 ); 405 406 #if defined(__arm64__) || defined(__aarch64__) 407 int RGA_set_src_vir_info( 408 struct rga_req *req, 409 unsigned long yrgb_addr, /* yrgb_addr */ 410 unsigned long uv_addr, /* uv_addr */ 411 unsigned long v_addr, /* v_addr */ 412 unsigned int vir_w, /* vir width */ 413 unsigned int vir_h, /* vir height */ 414 unsigned char format, /* format */ 415 unsigned char a_swap_en /* only for 32bit RGB888 format */ 416 ); 417 #else 418 int RGA_set_src_vir_info( 419 struct rga_req *req, 420 unsigned int yrgb_addr, /* yrgb_addr */ 421 unsigned int uv_addr, /* uv_addr */ 422 unsigned int v_addr, /* v_addr */ 423 unsigned int vir_w, /* vir width */ 424 unsigned int vir_h, /* vir height */ 425 unsigned char format, /* format */ 426 unsigned char a_swap_en /* only for 32bit RGB888 format */ 427 ); 428 #endif 429 430 int RGA_set_dst_act_info( 431 struct rga_req *req, 432 unsigned int width, /* act width */ 433 unsigned int height, /* act height */ 434 unsigned int x_off, /* x_off */ 435 unsigned int y_off /* y_off */ 436 ); 437 438 #if defined(__arm64__) || defined(__aarch64__) 439 int RGA_set_dst_vir_info( 440 struct rga_req *msg, 441 unsigned long yrgb_addr, /* yrgb_addr */ 442 unsigned long uv_addr, /* uv_addr */ 443 unsigned long v_addr, /* v_addr */ 444 unsigned int vir_w, /* vir width */ 445 unsigned int vir_h, /* vir height */ 446 RECT *clip, /* clip window */ 447 unsigned char format, /* format */ 448 unsigned char a_swap_en 449 ); 450 #else 451 int RGA_set_dst_vir_info( 452 struct rga_req *msg, 453 unsigned int yrgb_addr, /* yrgb_addr */ 454 unsigned int uv_addr, /* uv_addr */ 455 unsigned int v_addr, /* v_addr */ 456 unsigned int vir_w, /* vir width */ 457 unsigned int vir_h, /* vir height */ 458 RECT *clip, /* clip window */ 459 unsigned char format, /* format */ 460 unsigned char a_swap_en 461 ); 462 #endif 463 464 int RGA_set_pat_info( 465 struct rga_req *msg, 466 unsigned int width, 467 unsigned int height, 468 unsigned int x_off, 469 unsigned int y_off, 470 unsigned int pat_format 471 ); 472 473 #if defined(__arm64__) || defined(__aarch64__) 474 int RGA_set_rop_mask_info( 475 struct rga_req *msg, 476 unsigned long rop_mask_addr, 477 unsigned int rop_mask_endian_mode 478 ); 479 #else 480 int RGA_set_rop_mask_info( 481 struct rga_req *msg, 482 unsigned int rop_mask_addr, 483 unsigned int rop_mask_endian_mode 484 ); 485 #endif 486 487 int RGA_set_alpha_en_info( 488 struct rga_req *msg, 489 unsigned int alpha_cal_mode, /* 0:alpha' = alpha + (alpha>>7) | alpha' = alpha */ 490 unsigned int alpha_mode, /* 0 global alpha / 1 per pixel alpha / 2 mix mode */ 491 unsigned int global_a_value, 492 unsigned int PD_en, /* porter duff alpha mode en */ 493 unsigned int PD_mode, 494 unsigned int dst_alpha_en ); /* use dst alpha */ 495 496 int RGA_set_rop_en_info( 497 struct rga_req *msg, 498 unsigned int ROP_mode, 499 unsigned int ROP_code, 500 unsigned int color_mode, 501 unsigned int solid_color 502 ); 503 504 505 int RGA_set_fading_en_info( 506 struct rga_req *msg, 507 unsigned char r, 508 unsigned char g, 509 unsigned char b 510 ); 511 512 int RGA_set_src_trans_mode_info( 513 struct rga_req *msg, 514 unsigned char trans_mode, 515 unsigned char a_en, 516 unsigned char b_en, 517 unsigned char g_en, 518 unsigned char r_en, 519 unsigned char color_key_min, 520 unsigned char color_key_max, 521 unsigned char zero_mode_en 522 ); 523 524 525 int RGA_set_bitblt_mode( 526 struct rga_req *msg, 527 unsigned char scale_mode, // 0/near 1/bilnear 2/bicubic 528 unsigned char rotate_mode, // 0/copy 1/rotate_scale 2/x_mirror 3/y_mirror 529 unsigned int angle, // rotate angle 530 unsigned int dither_en, // dither en flag 531 unsigned int AA_en, // AA flag 532 unsigned int yuv2rgb_mode 533 ); 534 535 536 int RGA_set_color_palette_mode( 537 struct rga_req *msg, 538 unsigned char palette_mode, /* 1bpp/2bpp/4bpp/8bpp */ 539 unsigned char endian_mode, /* src endian mode sel */ 540 unsigned int bpp1_0_color, /* BPP1 = 0 */ 541 unsigned int bpp1_1_color /* BPP1 = 1 */ 542 ); 543 544 545 int RGA_set_color_fill_mode( 546 struct rga_req *msg, 547 COLOR_FILL *gr_color, /* gradient color part */ 548 unsigned char gr_satur_mode, /* saturation mode */ 549 unsigned char cf_mode, /* patten fill or solid fill */ 550 unsigned int color, /* solid color */ 551 unsigned short pat_width, /* pattern width */ 552 unsigned short pat_height, /* pattern height */ 553 unsigned char pat_x_off, /* pattern x offset */ 554 unsigned char pat_y_off, /* pattern y offset */ 555 unsigned char aa_en /* alpha en */ 556 ); 557 558 559 int RGA_set_line_point_drawing_mode( 560 struct rga_req *msg, 561 POINT sp, /* start point */ 562 POINT ep, /* end point */ 563 unsigned int color, /* line point drawing color */ 564 unsigned int line_width, /* line width */ 565 unsigned char AA_en, /* AA en */ 566 unsigned char last_point_en /* last point en */ 567 ); 568 569 570 int RGA_set_blur_sharp_filter_mode( 571 struct rga_req *msg, 572 unsigned char filter_mode, /* blur/sharpness */ 573 unsigned char filter_type, /* filter intensity */ 574 unsigned char dither_en /* dither_en flag */ 575 ); 576 577 int RGA_set_pre_scaling_mode( 578 struct rga_req *msg, 579 unsigned char dither_en 580 ); 581 582 #if defined(__arm64__) || defined(__aarch64__) 583 int RGA_update_palette_table_mode( 584 struct rga_req *msg, 585 unsigned long LUT_addr, /* LUT table addr */ 586 unsigned int palette_mode /* 1bpp/2bpp/4bpp/8bpp */ 587 ); 588 #else 589 int RGA_update_palette_table_mode( 590 struct rga_req *msg, 591 unsigned int LUT_addr, /* LUT table addr */ 592 unsigned int palette_mode /* 1bpp/2bpp/4bpp/8bpp */ 593 ); 594 #endif 595 596 int RGA_set_update_patten_buff_mode( 597 struct rga_req *msg, 598 unsigned int pat_addr, /* patten addr */ 599 unsigned int w, /* patten width */ 600 unsigned int h, /* patten height */ 601 unsigned int format /* patten format */ 602 ); 603 604 #if defined(__arm64__) || defined(__aarch64__) 605 int RGA_set_mmu_info( 606 struct rga_req *msg, 607 unsigned char mmu_en, 608 unsigned char src_flush, 609 unsigned char dst_flush, 610 unsigned char cmd_flush, 611 unsigned long base_addr, 612 unsigned char page_size 613 ); 614 #else 615 int RGA_set_mmu_info( 616 struct rga_req *msg, 617 unsigned char mmu_en, 618 unsigned char src_flush, 619 unsigned char dst_flush, 620 unsigned char cmd_flush, 621 unsigned int base_addr, 622 unsigned char page_size 623 ); 624 #endif 625 626 void rga_set_fds_offsets( 627 struct rga_req *rga_request, 628 unsigned short src_fd, 629 unsigned short dst_fd, 630 unsigned int src_offset, 631 unsigned int dst_offset); 632 633 int RGA_set_src_fence_flag( 634 struct rga_req *msg, 635 int acq_fence, 636 int src_flag 637 ); 638 639 640 int RGA_set_dst_fence_flag( 641 struct rga_req *msg, 642 int dst_flag 643 ); 644 645 int RGA_get_dst_fence( 646 struct rga_req *msg 647 ); 648 #ifdef __cplusplus 649 } 650 #endif 651 652 #endif /*_RK29_IPP_DRIVER_H_*/ 653