1 /* 2 * Copyright (c) 2021 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef I2S_HI35XX_H 17 #define I2S_HI35XX_H 18 19 #include "i2s_if.h" 20 #include "los_vm_zone.h" 21 #include "hdf_base.h" 22 23 #ifdef __cplusplus 24 #if __cplusplus 25 extern "C" { 26 #endif /* __cplusplus */ 27 #endif /* __cplusplus */ 28 29 #ifdef I2S_PRINTK_OPEN 30 #define I2S_PRINT_LOG_DBG(fmt, arg...) printk("[HDF]-[I2S]:" fmt "\r\n", ##arg) 31 #define I2S_PRINT_LOG_ERR(fmt, arg...) printk("[HDF]-[I2S]:" fmt "\r\n", ##arg) 32 #else 33 #define I2S_PRINT_LOG_DBG(fmt, arg...) HDF_LOGD_WRAPPER("[HDF]-[I2S]:" fmt "\r\n", ##arg) 34 #define I2S_PRINT_LOG_ERR(fmt, arg...) HDF_LOGE_WRAPPER("[HDF]-[I2S]:" fmt "\r\n", ##arg) 35 #endif 36 37 #define I2S_PRINT_DATA_LOG_DBG(fmt, arg...) HDF_LOGD_WRAPPER(fmt, ##arg) 38 39 #define I2S_AIAO_BUSNUM 0 40 #define I2S_AUDIO_CODEC_BUSNUM 1 41 42 #define I2S_AIAO_SAMPLE_PRECISION_24 24 43 #define I2S_AIAO_SAMPLE_PRECISION_16 16 44 45 #define AUDIO_CODEC_BASE_ADDR 0x113C0000 46 #define ACODEC_MAX_REG_SIZE 0x1000 47 48 #define CRG_BASE_ADDR 0x12010000 49 #define PERI_CRG103 (CRG_BASE_ADDR + 0x019c) 50 #define AIAO_PLL_CKEN (0x1 << 3) 51 #define AIAO_PLL_CKEN_SHIFT 3 52 #define AIAO_CKEN (0x1 << 1) 53 #define AIAO_CKEN_SHIFT 1 54 55 typedef enum { 56 ACODEC_ADC_MODESEL_6144 = 0x0, 57 ACODEC_ADC_MODESEL_4096 = 0x1, 58 ACODEC_ADC_MODESEL_BUTT = 0xff, 59 } AcodecAdcModeSel; 60 61 enum I2sHi35xxAiaoFsclkDiv { 62 AIAO_FSCLK_DIV_16 = 16, /* aiao_fsclk_div [6:4] 000 */ 63 AIAO_FSCLK_DIV_32 = 32, /* aiao_fsclk_div [6:4] 001 */ 64 AIAO_FSCLK_DIV_48 = 48, /* aiao_fsclk_div [6:4] 010 */ 65 AIAO_FSCLK_DIV_64 = 64, /* aiao_fsclk_div [6:4] 011 */ 66 AIAO_FSCLK_DIV_128 = 128, /* aiao_fsclk_div [6:4] 100 */ 67 AIAO_FSCLK_DIV_256 = 256, /* aiao_fsclk_div [6:4] 101 */ 68 AIAO_FSCLK_DIV_8 = 8, /* aiao_fsclk_div [6:4] 110 */ 69 }; 70 71 enum I2sHi35xxAiaoBclkDiv { 72 AIAO_BCLK_DIV_4 = 4, /* aiao_bclk_div [3:0] 0011 */ 73 AIAO_BCLK_DIV_8 = 8, /* aiao_bclk_div [3:0] 0101 */ 74 }; 75 76 /**< REG I2S_CFG_CFG1_00 CFG*/ 77 struct I2sCfgCfg100 { 78 uint8_t aiaoSrstReq; /**< bit 9, aiao_srst_req RX0 channel reset */ 79 uint8_t aiaoCken; /**< bit 8, aiao_cken MCLK/BCLK/WS clk gate */ 80 uint8_t aiaoFsclkDiv; /**< bit [6:4] aiao_fsclk_div, fs=xxx*BCLK */ 81 uint8_t aiaoBclkDiv; /**< bit [3:0], aiao_bclk_div,MCLK=xxx*BCLK */ 82 }; 83 84 /**< REG RX_IF_ATTR1 CFG*/ 85 struct RxIfAttr1Info { 86 uint32_t rxSdSourceSel; /**< bit [23:20], rx_sd_source_sel, normal work val = 0x1000 */ 87 uint8_t rxTrackmode; /**< bit [18:16], rx_trackmode, if mode=I2S, channel control */ 88 uint8_t rxSdOffset; /**< bit [15:8], rx_sd_offset, 0x1 STD/ 0x0LSB */ 89 uint8_t rxChNum; /**< bit [6:4], rx_ch_num, rx channel num */ 90 uint8_t rxI2sPrecision; /**< bit [3:2], rx_i2s_precision, date sample precision config bit */ 91 uint8_t rxMode; /**< bit [1:0], rx_mode, 00--I2S 01--PCM */ 92 }; 93 94 struct RxBuffInfo { 95 uint32_t saddr; /**< REG RX_BUFF_SADDR CFG*/ 96 uint32_t size; /**< REG RX_BUFF_SIZE CFG*/ 97 uint32_t wptrAddr; /**< REG RX_BUFF_WPTR CFG*/ 98 uint32_t rptrAddr; /**< REG RX_BUFF_RPTR CFG*/ 99 uint32_t intEna; /**< REG RX_INT_ENA CFG*/ 100 uint32_t dspCtrl; /**< REG RX_DSP_CTRL CFG*/ 101 uint32_t transSize; /**< REG RX_TRANS_SIZE CFG*/ 102 }; 103 104 struct I2sConfigInfo { 105 uint8_t i2sPadEnable; 106 uint8_t audioEnable; 107 uint32_t PERICRG103; 108 uint32_t I2sCfgCfg000; 109 uint32_t mclk; /**< KHZ */ 110 uint32_t bclk; /**< KHZ */ 111 struct I2sCfgCfg100 regCfg100; 112 struct RxIfAttr1Info regRxIfAttr1; 113 volatile unsigned char *phyBase; 114 volatile unsigned char *regBase; 115 enum I2sWriteChannel writeChannel; 116 enum I2sSampleRate sampleRate; 117 enum I2sWordWidth width; 118 enum I2sChannelIfMode channelIfMode; 119 enum I2sChannelMode channelMode; 120 enum I2sProtocolType type; 121 uint8_t samplePrecision; 122 uint16_t i2slFsSel; 123 DMA_ADDR_T rxData; 124 uint8_t *rxVirData; 125 uint32_t rxWptr; 126 uint32_t rxRptr; 127 uint32_t rxSize; 128 uint32_t rxTransSize; 129 DMA_ADDR_T txData; 130 uint8_t *txVirData; 131 uint32_t txWptr; 132 uint32_t txRptr; 133 uint32_t txSize; 134 uint32_t txTransSize; 135 volatile unsigned char *codecAddr; 136 volatile unsigned char *crg103Addr; 137 bool isplay; 138 bool txEn; 139 }; 140 141 int32_t Hi35xxI2sRegWrite(uint32_t value, volatile unsigned char *addr); 142 uint32_t Hi35xxI2sRegRead(volatile unsigned char *addr); 143 144 #ifdef __cplusplus 145 #if __cplusplus 146 } 147 #endif /* __cplusplus */ 148 #endif /* __cplusplus */ 149 #endif /* I2S_HI35XX_H */ 150