1 /* 2 * Copyright (c) 2022 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * Licensed under the Apache License, Version 2.0 (the "License"); 4 * you may not use this file except in compliance with the License. 5 * You may obtain a copy of the License at 6 * 7 * http://www.apache.org/licenses/LICENSE-2.0 8 * 9 * Unless required by applicable law or agreed to in writing, software 10 * distributed under the License is distributed on an "AS IS" BASIS, 11 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 12 * See the License for the specific language governing permissions and 13 * limitations under the License. 14 */ 15 16 #ifndef TIMER_HI35XX_H 17 #define TIMER_HI35XX_H 18 19 #include "los_vm_zone.h" 20 #include "hdf_base.h" 21 #include "timer_core.h" 22 23 #ifdef __cplusplus 24 #if __cplusplus 25 extern "C" { 26 #endif /* __cplusplus */ 27 #endif /* __cplusplus */ 28 29 #define TIMER_MAX_REG_SIZE (64 * 1024) 30 31 struct TimerHi35xxInfo { 32 uint32_t number; 33 uint32_t busClock; 34 uint32_t mode; 35 uint32_t initCountVal; 36 uint32_t irq; 37 bool isIrqReg; 38 bool isPeriod; 39 volatile uint8_t *regBase; 40 TimerHandleCb cb; 41 }; 42 43 #define HI35XX_SC_CTRL_REG (0x12020000 + 0x0000) 44 #define HI35XX_SC_CTRL_TIMEREN0OV (0x1 << 16) 45 #define HI35XX_SC_CTRL_TIMEREN0OV_SHIFT 16 46 #define HI35XX_SC_CTRL_TIMEREN1OV (0x1 << 17) 47 #define HI35XX_SC_CTRL_TIMEREN1OV_SHIFT 17 48 #define HI35XX_SC_CTRL_TIMEREN2OV (0x1 << 18) 49 #define HI35XX_SC_CTRL_TIMEREN2OV_SHIFT 18 50 #define HI35XX_SC_CTRL_TIMEREN3OV (0x1 << 19) 51 #define HI35XX_SC_CTRL_TIMEREN3OV_SHIFT 19 52 #define HI35XX_SC_CTRL_TIMEREN4OV (0x1 << 20) 53 #define HI35XX_SC_CTRL_TIMEREN4OV_SHIFT 20 54 #define HI35XX_SC_CTRL_TIMEREN5OV (0x1 << 21) 55 #define HI35XX_SC_CTRL_TIMEREN5OV_SHIFT 21 56 #define HI35XX_SC_CTRL_TIMEREN6OV (0x1 << 22) 57 #define HI35XX_SC_CTRL_TIMEREN6OV_SHIFT 22 58 #define HI35XX_SC_CTRL_TIMEREN7OV (0x1 << 23) 59 #define HI35XX_SC_CTRL_TIMEREN7OV_SHIFT 23 60 61 62 #define HI35XX_TIMERx_LOAD 0x000 63 #define HI35XX_TIMERx_VALUE 0x004 64 #define HI35XX_TIMERx_CONTROL 0x008 65 #define HI35XX_TIMERx_INTCLR 0x00C 66 #define HI35XX_TIMERx_RIS 0x010 67 #define HI35XX_TIMERx_MIS 0x014 68 #define HI35XX_TIMERx_BGLOAD 0x018 69 70 #define HI35XX_TIMERx_CLOCK_HZ (3 * 1000 * 1000) 71 #define HI35XX_TIMERx_LOAD_INIT_VAL 0x1000 72 #define HI35XX_TIMERx_US_TRANS_S 1000 73 74 75 #define HI35XX_TIMER0_1_INT_NUM 33 76 #define HI35XX_TIMER2_3_INT_NUM 34 77 #define HI35XX_TIMER4_5_INT_NUM 35 78 #define HI35XX_TIMER6_7_INT_NUM 36 79 80 // HI35XX_TIMERx_CONTROL reg control info 81 #define TIMERx_CONTROL_TIMEREN (0x1 << 7) 82 #define TIMERx_CONTROL_TIMEREN_SHIFT 7 83 #define TIMERx_CONTROL_TIMERMODE (0x1 << 6) 84 #define TIMERx_CONTROL_TIMERMODE_SHIFT 6 85 #define TIMERx_CONTROL_INTENABLE (0x1 << 5) 86 #define TIMERx_CONTROL_INTENABLE_SHIFT 5 87 #define TIMERx_CONTROL_TIMERPRE (0x3 << 2) 88 #define TIMERx_CONTROL_TIMERPRE_SHIFT 2 89 #define TIMERx_CONTROL_TIMERSIZE (0x1 << 1) 90 #define TIMERx_CONTROL_TIMERSIZE_SHIFT 1 91 #define TIMERx_CONTROL_ONESHOT (0x1 << 0) 92 #define TIMERx_CONTROL_ONESHOT_SHIFT 0 93 94 #define TIMERx_CONTROL_TIMERMODE_FREE 0x0 95 #define TIMERx_CONTROL_TIMERMODE_PERIOD 0x1 96 #define TIMERx_CONTROL_TIMERMODE_ONESHOT 0x2 97 98 99 #define TIMERx_CONTROL_TIMERMODE_ONESHOT_PERIOD 0x0 100 #define TIMERx_CONTROL_TIMERMODE_ONESHOT_ONE 0x1 101 102 #define TIMERx_CONTROL_TIMERPRE_NOT 0x0 103 #define TIMERx_CONTROL_TIMERPRE_4_LEVEL 0x01 104 #define TIMERx_CONTROL_TIMERPRE_8_LEVEL 0x10 105 #define TIMERx_CONTROL_TIMERPRE_UNDEFINE 0x11 106 107 #ifdef __cplusplus 108 #if __cplusplus 109 } 110 #endif /* __cplusplus */ 111 #endif /* __cplusplus */ 112 #endif /* TIMER_HI35XX_H */ 113