1 /* 2 * Copyright (C) 2022 HiSilicon (Shanghai) Technologies CO., LIMITED. 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License 6 * as published by the Free Software Foundation; either version 2 7 * of the License, or (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program; if not, write to the Free Software 16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 17 */ 18 19 #ifndef __HI_COMM_IRQ_H__ 20 #define __HI_COMM_IRQ_H__ 21 22 /* For IRQ */ 23 #define HI_MAX_STATE_NUM 2 24 25 #define VI_MAX_DEV_NUM 1 26 #define VI_MAX_PHY_PIPE_NUM 1 27 #define VI_MAX_ISP_FE_NUM 1 28 29 #define AIO_TX_MAX_NUM 8 30 #define AIO_RX_MAX_NUM 8 31 #define AIO_SPDIFTX_MAX_NUM 4 32 33 typedef enum { 34 HI_INT_NORMAL = 0, 35 HI_INT_VICAP = 1, 36 HI_INT_SCD = 2, 37 HI_INT_VDH = 3, 38 HI_INT_NNIE = 4, 39 HI_INT_AIO = 5, 40 HI_INT_BUTT, 41 } hi_int_type; 42 43 typedef struct { 44 volatile hi_u32 state_num; /* Number of interrupt states */ 45 volatile hi_u32 raw_state[HI_MAX_STATE_NUM]; /* raw interrupt states */ 46 volatile hi_u32 mask_state[HI_MAX_STATE_NUM]; /* interrupt states after mask */ 47 } hi_normal_int_state; 48 49 typedef struct { 50 volatile unsigned int cap_state; 51 volatile unsigned int pt_state[VI_MAX_DEV_NUM]; 52 volatile unsigned int ch_state[VI_MAX_PHY_PIPE_NUM]; 53 volatile unsigned int isp_fe_state[VI_MAX_ISP_FE_NUM]; 54 } hi_vicap_int_state; 55 56 typedef struct { 57 unsigned int aio_int_status_state; 58 unsigned int aio_int_raw_state; 59 unsigned int tx_raw_state[AIO_TX_MAX_NUM]; 60 unsigned int tx_stat_state[AIO_TX_MAX_NUM]; 61 unsigned int rx_raw_state[AIO_RX_MAX_NUM]; 62 unsigned int rx_stat_state[AIO_RX_MAX_NUM]; 63 unsigned int spdiftx_raw_state[AIO_SPDIFTX_MAX_NUM]; 64 unsigned int spdiftx_stat_state[AIO_SPDIFTX_MAX_NUM]; 65 } hi_aio_int_state; 66 67 typedef struct { 68 hi_int_type type; 69 union { 70 hi_normal_int_state normal; 71 hi_vicap_int_state vicap; 72 hi_aio_int_state aio; 73 }; 74 } hi_int_state_info; 75 76 typedef struct { 77 hi_void *dev; 78 hi_int_state_info int_info; 79 } hi_irq_arg; 80 81 82 typedef struct { 83 unsigned int cap_reg; 84 unsigned int pt_reg[VI_MAX_DEV_NUM]; 85 unsigned int ch_reg[VI_MAX_PHY_PIPE_NUM]; 86 unsigned int isp_fe_reg[VI_MAX_ISP_FE_NUM]; 87 } hi_vicap_int_reg; 88 89 typedef struct { 90 unsigned int aio_int_status_reg; 91 unsigned int aio_int_raw_reg; 92 unsigned int tx_clr_reg[AIO_TX_MAX_NUM]; 93 unsigned int tx_raw_reg[AIO_TX_MAX_NUM]; 94 unsigned int tx_stat_reg[AIO_TX_MAX_NUM]; 95 unsigned int rx_clr_reg[AIO_RX_MAX_NUM]; 96 unsigned int rx_raw_reg[AIO_RX_MAX_NUM]; 97 unsigned int rx_stat_reg[AIO_RX_MAX_NUM]; 98 unsigned int spdiftx_clr_reg[AIO_SPDIFTX_MAX_NUM]; 99 unsigned int spdiftx_raw_reg[AIO_SPDIFTX_MAX_NUM]; 100 unsigned int spdiftx_stat_reg[AIO_SPDIFTX_MAX_NUM]; 101 } hi_aio_int_reg; 102 103 104 typedef struct { 105 unsigned int reg_num; 106 unsigned int raw_int_reg[HI_MAX_STATE_NUM]; /* raw int state */ 107 unsigned int mask_int_reg[HI_MAX_STATE_NUM]; /* int state after mask */ 108 unsigned int clr_int_reg[HI_MAX_STATE_NUM]; 109 unsigned int clr_or_mask[HI_MAX_STATE_NUM]; 110 } hi_normal_int_reg; 111 112 typedef struct { 113 hi_int_type type; 114 union { 115 hi_normal_int_reg normal; 116 hi_vicap_int_reg vicap; 117 hi_aio_int_reg aio; 118 }; 119 } hi_int_reg_info; 120 121 #endif /* end of #ifndef __HI_COMM_IRQ_H__ */ 122 123