1 /* 2 * Copyright (c) 2021 Huawei Device Co., Ltd. 3 * 4 * HDF is dual licensed: you can use it either under the terms of 5 * the GPL, or the BSD license, at your option. 6 * See the LICENSE file in the root of this repository for complete details. 7 */ 8 9 #ifndef MTD_SPI_COMMON_H 10 #define MTD_SPI_COMMON_H 11 12 #include "mtd_core.h" 13 14 #ifdef __cplusplus 15 #if __cplusplus 16 extern "C" { 17 #endif 18 #endif /* __cplusplus */ 19 20 struct SpiFlash; 21 22 /** 23 * @Defines the spi configuration of a specific operation 24 * 25 */ 26 struct MtdSpiConfig { 27 /** spi interface type */ 28 uint8_t ifType; 29 /** the operation command */ 30 uint8_t cmd; 31 /** dummy cycles */ 32 uint8_t dummy; 33 /** not used now */ 34 uint32_t size; 35 /** system clock used */ 36 uint32_t clock; 37 }; 38 39 /** 40 * @brief Enumerates the type of spi interface. 41 * 42 */ 43 enum SpiIfType { 44 MTD_SPI_IF_STD = 0, 45 MTD_SPI_IF_DUAL = 1, 46 MTD_SPI_IF_DIO = 2, 47 MTD_SPI_IF_QUAD = 3, 48 MTD_SPI_IF_QIO = 4, 49 }; 50 51 /** 52 * @Defines the spi oepration set of a mtd device. 53 * 54 */ 55 struct MtdSpiOps { 56 int32_t (*waitReady)(struct SpiFlash *spi); 57 int32_t (*writeEnable)(struct SpiFlash *spi); 58 int32_t (*qeEnable)(struct SpiFlash *spi); 59 int32_t (*entry4Addr)(struct SpiFlash *spi, int enable); 60 }; 61 62 /** 63 * @Defines the info structure which contains vendor id and spi operations 64 * 65 */ 66 struct SpiOpsInfo { 67 uint8_t id[MTD_FLASH_ID_LEN_MAX]; 68 uint8_t idLen; 69 struct MtdSpiOps spiOps; 70 }; 71 72 /** 73 * @Defines the structure used to identify a physical spi flash. 74 * 75 */ 76 struct SpiFlash { 77 /** The parent device */ 78 struct MtdDevice mtd; 79 /** chip select number */ 80 uint8_t cs; 81 /** address cycle */ 82 uint32_t addrCycle; 83 /** spi configuration of erase */ 84 struct MtdSpiConfig eraseCfg; 85 /** spi configuration of write */ 86 struct MtdSpiConfig writeCfg; 87 /** spi configuration of read */ 88 struct MtdSpiConfig readCfg; 89 /** spi operation set of the device */ 90 struct MtdSpiOps spiOps; 91 }; 92 93 /** 94 * @brief Wait for a spi flash to be ready. 95 * 96 * @param spi Indicates the pointer to the spi flash. 97 * 98 * @return Returns 0 on success; returns a negative value otherwise. 99 */ 100 int32_t SpiFlashWaitReady(struct SpiFlash *spi); 101 102 /** 103 * @brief Enable write operation to a spi falsh. 104 * 105 * @param spi Indicates the pointer to the spi flash. 106 * 107 * @return Returns 0 on success; returns a negative value otherwise. 108 */ 109 int32_t SpiFlashWriteEnable(struct SpiFlash *spi); 110 111 /** 112 * @brief Enable QUAD I/O mode of a spi falsh if it supports. 113 * 114 * @param spi Indicates the pointer to the spi flash. 115 * 116 * @return Returns 0 on success; returns a negative value otherwise. 117 */ 118 int32_t SpiFlashQeEnable(struct SpiFlash *spi); 119 120 /** 121 * @brief Enable 4 byte address mode of a spi falsh if it supports. 122 * 123 * @param spi Indicates the pointer to the spi flash. 124 * 125 * @return Returns 0 on success; returns a negative value otherwise. 126 */ 127 int32_t SpiFlashEntry4Addr(struct SpiFlash *spi, int enable); 128 129 /** 130 * @brief Add a spi flash device. 131 * 132 * do not call in irq context cause it may sleep 133 * 134 * @param spi Indicates the pointer to the spi flash device. 135 * 136 * @return Returns 0 if add successfully; returns a negative value otherwise. 137 */ 138 int32_t SpiFlashAdd(struct SpiFlash *spi); 139 140 /** 141 * @brief Delete a spi flash device. 142 * 143 * do not call in irq context cause it may sleep 144 * 145 * @param spi Indicates the pointer to the spi flash device. 146 */ 147 void SpiFlashDel(struct SpiFlash *spi); 148 149 /****************************Spi Common Command Set **************************************/ 150 #define MTD_SPI_CMD_WRSR 0x01 /* Write Status Register */ 151 #define MTD_SPI_CMD_WRITE_STD 0x02 /* Standard page program */ 152 #define MTD_SPI_CMD_READ_STD 0x03 /* Standard page cache */ 153 #define MTD_SPI_CMD_WRDI 0x04 /* Write Disable */ 154 155 #define MTD_SPI_CMD_RDSR 0x05 /* Read Status Register */ 156 #define MTD_SPI_SR_WEL_MASK (1 << 1) 157 #define MTD_SPI_SR_WIP_MASK (1 << 0) 158 #define MTD_SPI_SR_QE_MASK (1 << 6) 159 160 #define MTD_SPI_CMD_WREN 0x06 /* Write Enable */ 161 162 #define MTD_SPI_CMD_GET_FEATURE 0x0F 163 #define MTD_SPI_CMD_SET_FEATURE 0x1F 164 165 #define MTD_SPI_CMD_RDSR3 0x15 /* Read Status Register 3 */ 166 #define MTD_SPI_SR3_4BYTE_SHIFT 5 167 #define MTD_SPI_SR3_4BYTE_MASK (1 << MTD_SPI_SR3_4BYTE_SHIFT) 168 #define MTD_SPI_SR3_IS_4BYTE(sr3) (((sr3) & MTD_SPI_SR3_4BYTE_MASK) >> MTD_SPI_SR3_4BYTE_SHIFT) 169 170 171 #define MTD_SPI_CMD_ERASE_4K 0x20 /* 4KB sector erase */ 172 #define MTD_SPI_CMD_ERASE_64K 0xD8 /* 64KB sector erase */ 173 174 #define MTD_SPI_CMD_WRSR2 0x31 /* Write Status Register 2 */ 175 176 #define MTD_SPI_CMD_RDSR2 0x35 /* Read Status Register 2 */ 177 #define MTD_SPI_CMD_RDCR 0x35 /* Read Config Register */ 178 #define MTD_SPI_CR_QE_MASK (1 << 1) 179 180 #define MTD_SPI_CMD_RDID 0x9F /* Read Identification */ 181 182 #define MTD_SPI_CMD_EN4B 0xB7 /* enter 4 bytes mode and set 4 byte bit */ 183 184 #define MTD_SPI_CMD_EX4B 0xE7 /* exit 4 bytes mode and clear 4 byte bit */ 185 186 187 #define MTD_SPI_CMD_RESET 0xFF 188 189 /**************************** Ohters **************************************/ 190 #define MTD_SPI_CS_MAX 2 191 #define MTD_SPI_STD_OP_ADDR_NUM 3 192 #define MTD_SPI_FEATURE_ECC_ENABLE (1 << 4) 193 #define MTD_SPI_FEATURE_QE_ENABLE (1 << 0) 194 195 196 #ifdef __cplusplus 197 #if __cplusplus 198 } 199 #endif 200 #endif /* __cplusplus */ 201 202 #endif /* MTD_SPI_COMMON_H */ 203