1* Renesas R-Car Gen2 Clock Pulse Generator (CPG) 2 3The CPG generates core clocks for the R-Car Gen2 SoCs. It includes three PLLs 4and several fixed ratio dividers. 5The CPG also provides a Clock Domain for SoC devices, in combination with the 6CPG Module Stop (MSTP) Clocks. 7 8Required Properties: 9 10 - compatible: Must be one of 11 - "renesas,r8a7790-cpg-clocks" for the r8a7790 CPG 12 - "renesas,r8a7791-cpg-clocks" for the r8a7791 CPG 13 - "renesas,r8a7792-cpg-clocks" for the r8a7792 CPG 14 - "renesas,r8a7793-cpg-clocks" for the r8a7793 CPG 15 - "renesas,r8a7794-cpg-clocks" for the r8a7794 CPG 16 and "renesas,rcar-gen2-cpg-clocks" as a fallback. 17 18 - reg: Base address and length of the memory resource used by the CPG 19 20 - clocks: References to the parent clocks: first to the EXTAL clock, second 21 to the USB_EXTAL clock 22 - #clock-cells: Must be 1 23 - clock-output-names: The names of the clocks. Supported clocks are "main", 24 "pll0", "pll1", "pll3", "lb", "qspi", "sdh", "sd0", "sd1", "z", "rcan", and 25 "adsp" 26 - #power-domain-cells: Must be 0 27 28SoC devices that are part of the CPG/MSTP Clock Domain and can be power-managed 29through an MSTP clock should refer to the CPG device node in their 30"power-domains" property, as documented by the generic PM domain bindings in 31Documentation/devicetree/bindings/power/power_domain.txt. 32 33 34Examples 35-------- 36 37 - CPG device node: 38 39 cpg_clocks: cpg_clocks@e6150000 { 40 compatible = "renesas,r8a7790-cpg-clocks", 41 "renesas,rcar-gen2-cpg-clocks"; 42 reg = <0 0xe6150000 0 0x1000>; 43 clocks = <&extal_clk &usb_extal_clk>; 44 #clock-cells = <1>; 45 clock-output-names = "main", "pll0, "pll1", "pll3", 46 "lb", "qspi", "sdh", "sd0", "sd1", "z", 47 "rcan", "adsp"; 48 #power-domain-cells = <0>; 49 }; 50 51 52 - CPG/MSTP Clock Domain member device node: 53 54 thermal@e61f0000 { 55 compatible = "renesas,thermal-r8a7790", "renesas,rcar-thermal"; 56 reg = <0 0xe61f0000 0 0x14>, <0 0xe61f0100 0 0x38>; 57 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; 58 clocks = <&mstp5_clks R8A7790_CLK_THERMAL>; 59 power-domains = <&cpg_clocks>; 60 }; 61