1Allwinner Display Engine 2.0 Clock Control Binding 2-------------------------------------------------- 3 4Required properties : 5- compatible: must contain one of the following compatibles: 6 - "allwinner,sun8i-a83t-de2-clk" 7 - "allwinner,sun8i-h3-de2-clk" 8 - "allwinner,sun8i-v3s-de2-clk" 9 - "allwinner,sun50i-a64-de2-clk" 10 - "allwinner,sun50i-h5-de2-clk" 11 12- reg: Must contain the registers base address and length 13- clocks: phandle to the clocks feeding the display engine subsystem. 14 Three are needed: 15 - "mod": the display engine module clock (on A83T it's the DE PLL) 16 - "bus": the bus clock for the whole display engine subsystem 17- clock-names: Must contain the clock names described just above 18- resets: phandle to the reset control for the display engine subsystem. 19- #clock-cells : must contain 1 20- #reset-cells : must contain 1 21 22Example: 23de2_clocks: clock@1000000 { 24 compatible = "allwinner,sun8i-h3-de2-clk"; 25 reg = <0x01000000 0x100000>; 26 clocks = <&ccu CLK_BUS_DE>, 27 <&ccu CLK_DE>; 28 clock-names = "bus", 29 "mod"; 30 resets = <&ccu RST_BUS_DE>; 31 #clock-cells = <1>; 32 #reset-cells = <1>; 33}; 34