1NVIDIA Tegra host1x 2 3Required properties: 4- compatible: "nvidia,tegra<chip>-host1x" 5- reg: Physical base address and length of the controller's registers. 6 For pre-Tegra186, one entry describing the whole register area. 7 For Tegra186, one entry for each entry in reg-names: 8 "vm" - VM region assigned to Linux 9 "hypervisor" - Hypervisor region (only if Linux acts as hypervisor) 10- interrupts: The interrupt outputs from the controller. 11- #address-cells: The number of cells used to represent physical base addresses 12 in the host1x address space. Should be 1. 13- #size-cells: The number of cells used to represent the size of an address 14 range in the host1x address space. Should be 1. 15- ranges: The mapping of the host1x address space to the CPU address space. 16- clocks: Must contain one entry, for the module clock. 17 See ../clocks/clock-bindings.txt for details. 18- resets: Must contain an entry for each entry in reset-names. 19 See ../reset/reset.txt for details. 20- reset-names: Must include the following entries: 21 - host1x 22 23The host1x top-level node defines a number of children, each representing one 24of the following host1x client modules: 25 26- mpe: video encoder 27 28 Required properties: 29 - compatible: "nvidia,tegra<chip>-mpe" 30 - reg: Physical base address and length of the controller's registers. 31 - interrupts: The interrupt outputs from the controller. 32 - clocks: Must contain one entry, for the module clock. 33 See ../clocks/clock-bindings.txt for details. 34 - resets: Must contain an entry for each entry in reset-names. 35 See ../reset/reset.txt for details. 36 - reset-names: Must include the following entries: 37 - mpe 38 39- vi: video input 40 41 Required properties: 42 - compatible: "nvidia,tegra<chip>-vi" 43 - reg: Physical base address and length of the controller's registers. 44 - interrupts: The interrupt outputs from the controller. 45 - clocks: Must contain one entry, for the module clock. 46 See ../clocks/clock-bindings.txt for details. 47 - resets: Must contain an entry for each entry in reset-names. 48 See ../reset/reset.txt for details. 49 - reset-names: Must include the following entries: 50 - vi 51 52- epp: encoder pre-processor 53 54 Required properties: 55 - compatible: "nvidia,tegra<chip>-epp" 56 - reg: Physical base address and length of the controller's registers. 57 - interrupts: The interrupt outputs from the controller. 58 - clocks: Must contain one entry, for the module clock. 59 See ../clocks/clock-bindings.txt for details. 60 - resets: Must contain an entry for each entry in reset-names. 61 See ../reset/reset.txt for details. 62 - reset-names: Must include the following entries: 63 - epp 64 65- isp: image signal processor 66 67 Required properties: 68 - compatible: "nvidia,tegra<chip>-isp" 69 - reg: Physical base address and length of the controller's registers. 70 - interrupts: The interrupt outputs from the controller. 71 - clocks: Must contain one entry, for the module clock. 72 See ../clocks/clock-bindings.txt for details. 73 - resets: Must contain an entry for each entry in reset-names. 74 See ../reset/reset.txt for details. 75 - reset-names: Must include the following entries: 76 - isp 77 78- gr2d: 2D graphics engine 79 80 Required properties: 81 - compatible: "nvidia,tegra<chip>-gr2d" 82 - reg: Physical base address and length of the controller's registers. 83 - interrupts: The interrupt outputs from the controller. 84 - clocks: Must contain one entry, for the module clock. 85 See ../clocks/clock-bindings.txt for details. 86 - resets: Must contain an entry for each entry in reset-names. 87 See ../reset/reset.txt for details. 88 - reset-names: Must include the following entries: 89 - 2d 90 91- gr3d: 3D graphics engine 92 93 Required properties: 94 - compatible: "nvidia,tegra<chip>-gr3d" 95 - reg: Physical base address and length of the controller's registers. 96 - clocks: Must contain an entry for each entry in clock-names. 97 See ../clocks/clock-bindings.txt for details. 98 - clock-names: Must include the following entries: 99 (This property may be omitted if the only clock in the list is "3d") 100 - 3d 101 This MUST be the first entry. 102 - 3d2 (Only required on SoCs with two 3D clocks) 103 - resets: Must contain an entry for each entry in reset-names. 104 See ../reset/reset.txt for details. 105 - reset-names: Must include the following entries: 106 - 3d 107 - 3d2 (Only required on SoCs with two 3D clocks) 108 109- dc: display controller 110 111 Required properties: 112 - compatible: "nvidia,tegra<chip>-dc" 113 - reg: Physical base address and length of the controller's registers. 114 - interrupts: The interrupt outputs from the controller. 115 - clocks: Must contain an entry for each entry in clock-names. 116 See ../clocks/clock-bindings.txt for details. 117 - clock-names: Must include the following entries: 118 - dc 119 This MUST be the first entry. 120 - parent 121 - resets: Must contain an entry for each entry in reset-names. 122 See ../reset/reset.txt for details. 123 - reset-names: Must include the following entries: 124 - dc 125 - nvidia,head: The number of the display controller head. This is used to 126 setup the various types of output to receive video data from the given 127 head. 128 129 Each display controller node has a child node, named "rgb", that represents 130 the RGB output associated with the controller. It can take the following 131 optional properties: 132 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 133 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 134 - nvidia,edid: supplies a binary EDID blob 135 - nvidia,panel: phandle of a display panel 136 137- hdmi: High Definition Multimedia Interface 138 139 Required properties: 140 - compatible: "nvidia,tegra<chip>-hdmi" 141 - reg: Physical base address and length of the controller's registers. 142 - interrupts: The interrupt outputs from the controller. 143 - hdmi-supply: supply for the +5V HDMI connector pin 144 - vdd-supply: regulator for supply voltage 145 - pll-supply: regulator for PLL 146 - clocks: Must contain an entry for each entry in clock-names. 147 See ../clocks/clock-bindings.txt for details. 148 - clock-names: Must include the following entries: 149 - hdmi 150 This MUST be the first entry. 151 - parent 152 - resets: Must contain an entry for each entry in reset-names. 153 See ../reset/reset.txt for details. 154 - reset-names: Must include the following entries: 155 - hdmi 156 157 Optional properties: 158 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 159 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 160 - nvidia,edid: supplies a binary EDID blob 161 - nvidia,panel: phandle of a display panel 162 163- tvo: TV encoder output 164 165 Required properties: 166 - compatible: "nvidia,tegra<chip>-tvo" 167 - reg: Physical base address and length of the controller's registers. 168 - interrupts: The interrupt outputs from the controller. 169 - clocks: Must contain one entry, for the module clock. 170 See ../clocks/clock-bindings.txt for details. 171 172- dsi: display serial interface 173 174 Required properties: 175 - compatible: "nvidia,tegra<chip>-dsi" 176 - reg: Physical base address and length of the controller's registers. 177 - clocks: Must contain an entry for each entry in clock-names. 178 See ../clocks/clock-bindings.txt for details. 179 - clock-names: Must include the following entries: 180 - dsi 181 This MUST be the first entry. 182 - lp 183 - parent 184 - resets: Must contain an entry for each entry in reset-names. 185 See ../reset/reset.txt for details. 186 - reset-names: Must include the following entries: 187 - dsi 188 - avdd-dsi-supply: phandle of a supply that powers the DSI controller 189 - nvidia,mipi-calibrate: Should contain a phandle and a specifier specifying 190 which pads are used by this DSI output and need to be calibrated. See also 191 ../display/tegra/nvidia,tegra114-mipi.txt. 192 193 Optional properties: 194 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 195 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 196 - nvidia,edid: supplies a binary EDID blob 197 - nvidia,panel: phandle of a display panel 198 - nvidia,ganged-mode: contains a phandle to a second DSI controller to gang 199 up with in order to support up to 8 data lanes 200 201- sor: serial output resource 202 203 Required properties: 204 - compatible: Should be: 205 - "nvidia,tegra124-sor": for Tegra124 and Tegra132 206 - "nvidia,tegra132-sor": for Tegra132 207 - "nvidia,tegra210-sor": for Tegra210 208 - "nvidia,tegra210-sor1": for Tegra210 209 - "nvidia,tegra186-sor": for Tegra186 210 - "nvidia,tegra186-sor1": for Tegra186 211 - reg: Physical base address and length of the controller's registers. 212 - interrupts: The interrupt outputs from the controller. 213 - clocks: Must contain an entry for each entry in clock-names. 214 See ../clocks/clock-bindings.txt for details. 215 - clock-names: Must include the following entries: 216 - sor: clock input for the SOR hardware 217 - out: SOR output clock 218 - parent: input for the pixel clock 219 - dp: reference clock for the SOR clock 220 - safe: safe reference for the SOR clock during power up 221 222 For Tegra186 and later: 223 - pad: SOR pad output clock (on Tegra186 and later) 224 225 Obsolete: 226 - source: source clock for the SOR clock (obsolete, use "out" instead) 227 228 - resets: Must contain an entry for each entry in reset-names. 229 See ../reset/reset.txt for details. 230 - reset-names: Must include the following entries: 231 - sor 232 233 Required properties on Tegra186 and later: 234 - nvidia,interface: index of the SOR interface 235 236 Optional properties: 237 - nvidia,ddc-i2c-bus: phandle of an I2C controller used for DDC EDID probing 238 - nvidia,hpd-gpio: specifies a GPIO used for hotplug detection 239 - nvidia,edid: supplies a binary EDID blob 240 - nvidia,panel: phandle of a display panel 241 242 Optional properties when driving an eDP output: 243 - nvidia,dpaux: phandle to a DispayPort AUX interface 244 245- dpaux: DisplayPort AUX interface 246 - compatible : Should contain one of the following: 247 - "nvidia,tegra124-dpaux": for Tegra124 and Tegra132 248 - "nvidia,tegra210-dpaux": for Tegra210 249 - reg: Physical base address and length of the controller's registers. 250 - interrupts: The interrupt outputs from the controller. 251 - clocks: Must contain an entry for each entry in clock-names. 252 See ../clocks/clock-bindings.txt for details. 253 - clock-names: Must include the following entries: 254 - dpaux: clock input for the DPAUX hardware 255 - parent: reference clock 256 - resets: Must contain an entry for each entry in reset-names. 257 See ../reset/reset.txt for details. 258 - reset-names: Must include the following entries: 259 - dpaux 260 - vdd-supply: phandle of a supply that powers the DisplayPort link 261 - i2c-bus: Subnode where I2C slave devices are listed. This subnode 262 must be always present. If there are no I2C slave devices, an empty 263 node should be added. See ../../i2c/i2c.txt for more information. 264 265 See ../pinctrl/nvidia,tegra124-dpaux-padctl.txt for information 266 regarding the DPAUX pad controller bindings. 267 268- vic: Video Image Compositor 269 - compatible : "nvidia,tegra<chip>-vic" 270 - reg: Physical base address and length of the controller's registers. 271 - interrupts: The interrupt outputs from the controller. 272 - clocks: Must contain an entry for each entry in clock-names. 273 See ../clocks/clock-bindings.txt for details. 274 - clock-names: Must include the following entries: 275 - vic: clock input for the VIC hardware 276 - resets: Must contain an entry for each entry in reset-names. 277 See ../reset/reset.txt for details. 278 - reset-names: Must include the following entries: 279 - vic 280 281Example: 282 283/ { 284 ... 285 286 host1x { 287 compatible = "nvidia,tegra20-host1x", "simple-bus"; 288 reg = <0x50000000 0x00024000>; 289 interrupts = <0 65 0x04 /* mpcore syncpt */ 290 0 67 0x04>; /* mpcore general */ 291 clocks = <&tegra_car TEGRA20_CLK_HOST1X>; 292 resets = <&tegra_car 28>; 293 reset-names = "host1x"; 294 295 #address-cells = <1>; 296 #size-cells = <1>; 297 298 ranges = <0x54000000 0x54000000 0x04000000>; 299 300 mpe { 301 compatible = "nvidia,tegra20-mpe"; 302 reg = <0x54040000 0x00040000>; 303 interrupts = <0 68 0x04>; 304 clocks = <&tegra_car TEGRA20_CLK_MPE>; 305 resets = <&tegra_car 60>; 306 reset-names = "mpe"; 307 }; 308 309 vi { 310 compatible = "nvidia,tegra20-vi"; 311 reg = <0x54080000 0x00040000>; 312 interrupts = <0 69 0x04>; 313 clocks = <&tegra_car TEGRA20_CLK_VI>; 314 resets = <&tegra_car 100>; 315 reset-names = "vi"; 316 }; 317 318 epp { 319 compatible = "nvidia,tegra20-epp"; 320 reg = <0x540c0000 0x00040000>; 321 interrupts = <0 70 0x04>; 322 clocks = <&tegra_car TEGRA20_CLK_EPP>; 323 resets = <&tegra_car 19>; 324 reset-names = "epp"; 325 }; 326 327 isp { 328 compatible = "nvidia,tegra20-isp"; 329 reg = <0x54100000 0x00040000>; 330 interrupts = <0 71 0x04>; 331 clocks = <&tegra_car TEGRA20_CLK_ISP>; 332 resets = <&tegra_car 23>; 333 reset-names = "isp"; 334 }; 335 336 gr2d { 337 compatible = "nvidia,tegra20-gr2d"; 338 reg = <0x54140000 0x00040000>; 339 interrupts = <0 72 0x04>; 340 clocks = <&tegra_car TEGRA20_CLK_GR2D>; 341 resets = <&tegra_car 21>; 342 reset-names = "2d"; 343 }; 344 345 gr3d { 346 compatible = "nvidia,tegra20-gr3d"; 347 reg = <0x54180000 0x00040000>; 348 clocks = <&tegra_car TEGRA20_CLK_GR3D>; 349 resets = <&tegra_car 24>; 350 reset-names = "3d"; 351 }; 352 353 dc@54200000 { 354 compatible = "nvidia,tegra20-dc"; 355 reg = <0x54200000 0x00040000>; 356 interrupts = <0 73 0x04>; 357 clocks = <&tegra_car TEGRA20_CLK_DISP1>, 358 <&tegra_car TEGRA20_CLK_PLL_P>; 359 clock-names = "dc", "parent"; 360 resets = <&tegra_car 27>; 361 reset-names = "dc"; 362 363 rgb { 364 status = "disabled"; 365 }; 366 }; 367 368 dc@54240000 { 369 compatible = "nvidia,tegra20-dc"; 370 reg = <0x54240000 0x00040000>; 371 interrupts = <0 74 0x04>; 372 clocks = <&tegra_car TEGRA20_CLK_DISP2>, 373 <&tegra_car TEGRA20_CLK_PLL_P>; 374 clock-names = "dc", "parent"; 375 resets = <&tegra_car 26>; 376 reset-names = "dc"; 377 378 rgb { 379 status = "disabled"; 380 }; 381 }; 382 383 hdmi { 384 compatible = "nvidia,tegra20-hdmi"; 385 reg = <0x54280000 0x00040000>; 386 interrupts = <0 75 0x04>; 387 clocks = <&tegra_car TEGRA20_CLK_HDMI>, 388 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 389 clock-names = "hdmi", "parent"; 390 resets = <&tegra_car 51>; 391 reset-names = "hdmi"; 392 status = "disabled"; 393 }; 394 395 tvo { 396 compatible = "nvidia,tegra20-tvo"; 397 reg = <0x542c0000 0x00040000>; 398 interrupts = <0 76 0x04>; 399 clocks = <&tegra_car TEGRA20_CLK_TVO>; 400 status = "disabled"; 401 }; 402 403 dsi { 404 compatible = "nvidia,tegra20-dsi"; 405 reg = <0x54300000 0x00040000>; 406 clocks = <&tegra_car TEGRA20_CLK_DSI>, 407 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>; 408 clock-names = "dsi", "parent"; 409 resets = <&tegra_car 48>; 410 reset-names = "dsi"; 411 status = "disabled"; 412 }; 413 }; 414 415 ... 416}; 417