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1* MTK MMC controller
2
3The MTK  MSDC can act as a MMC controller
4to support MMC, SD, and SDIO types of memory cards.
5
6This file documents differences between the core properties in mmc.txt
7and the properties used by the msdc driver.
8
9Required properties:
10- compatible: value should be either of the following.
11	"mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
12	"mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
13	"mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
14	"mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
15	"mediatek,mt7622-mmc": for MT7622 SoC
16	"mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC
17
18- reg: physical base address of the controller and length
19- interrupts: Should contain MSDC interrupt number
20- clocks: Should contain phandle for the clock feeding the MMC controller
21- clock-names: Should contain the following:
22	"source" - source clock (required)
23	"hclk" - HCLK which used for host (required)
24	"source_cg" - independent source clock gate (required for MT2712)
25- pinctrl-names: should be "default", "state_uhs"
26- pinctrl-0: should contain default/high speed pin ctrl
27- pinctrl-1: should contain uhs mode pin ctrl
28- vmmc-supply: power to the Core
29- vqmmc-supply: power to the IO
30
31Optional properties:
32- assigned-clocks: PLL of the source clock
33- assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock
34- hs400-ds-delay: HS400 DS delay setting
35- mediatek,hs200-cmd-int-delay: HS200 command internal delay setting.
36				This field has total 32 stages.
37				The value is an integer from 0 to 31.
38- mediatek,hs400-cmd-int-delay: HS400 command internal delay setting
39				This field has total 32 stages.
40				The value is an integer from 0 to 31.
41- mediatek,hs400-cmd-resp-sel-rising:  HS400 command response sample selection
42				       If present,HS400 command responses are sampled on rising edges.
43				       If not present,HS400 command responses are sampled on falling edges.
44- mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct latch-ck to avoid data crc
45		     error caused by stop clock(fifo full)
46		     Valid range = [0:0x7]. if not present, default value is 0.
47		     applied to compatible "mediatek,mt2701-mmc".
48
49Examples:
50mmc0: mmc@11230000 {
51	compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc";
52	reg = <0 0x11230000 0 0x108>;
53	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
54	vmmc-supply = <&mt6397_vemc_3v3_reg>;
55	vqmmc-supply = <&mt6397_vio18_reg>;
56	clocks = <&pericfg CLK_PERI_MSDC30_0>,
57	         <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
58	clock-names = "source", "hclk";
59	pinctrl-names = "default", "state_uhs";
60	pinctrl-0 = <&mmc0_pins_default>;
61	pinctrl-1 = <&mmc0_pins_uhs>;
62	assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
63	assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
64	hs400-ds-delay = <0x14015>;
65	mediatek,hs200-cmd-int-delay = <26>;
66	mediatek,hs400-cmd-int-delay = <14>;
67	mediatek,hs400-cmd-resp-sel-rising;
68};
69