1* Cadence Quad SPI controller 2 3Required properties: 4- compatible : should be one of the following: 5 Generic default - "cdns,qspi-nor". 6 For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor". 7- reg : Contains two entries, each of which is a tuple consisting of a 8 physical address and length. The first entry is the address and 9 length of the controller register set. The second entry is the 10 address and length of the QSPI Controller data area. 11- interrupts : Unit interrupt specifier for the controller interrupt. 12- clocks : phandle to the Quad SPI clock. 13- cdns,fifo-depth : Size of the data FIFO in words. 14- cdns,fifo-width : Bus width of the data FIFO in bytes. 15- cdns,trigger-address : 32-bit indirect AHB trigger address. 16 17Optional properties: 18- cdns,is-decoded-cs : Flag to indicate whether decoder is used or not. 19- cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch 20 the read data rather than the QSPI clock. Make sure that QSPI return 21 clock is populated on the board before using this property. 22 23Optional subnodes: 24Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional 25custom properties: 26- cdns,read-delay : Delay for read capture logic, in clock cycles 27- cdns,tshsl-ns : Delay in nanoseconds for the length that the master 28 mode chip select outputs are de-asserted between 29 transactions. 30- cdns,tsd2d-ns : Delay in nanoseconds between one chip select being 31 de-activated and the activation of another. 32- cdns,tchsh-ns : Delay in nanoseconds between last bit of current 33 transaction and deasserting the device chip select 34 (qspi_n_ss_out). 35- cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low 36 and first bit transfer. 37 38Example: 39 40 qspi: spi@ff705000 { 41 compatible = "cdns,qspi-nor"; 42 #address-cells = <1>; 43 #size-cells = <0>; 44 reg = <0xff705000 0x1000>, 45 <0xffa00000 0x1000>; 46 interrupts = <0 151 4>; 47 clocks = <&qspi_clk>; 48 cdns,is-decoded-cs; 49 cdns,fifo-depth = <128>; 50 cdns,fifo-width = <4>; 51 cdns,trigger-address = <0x00000000>; 52 53 flash0: n25q00@0 { 54 ... 55 cdns,read-delay = <4>; 56 cdns,tshsl-ns = <50>; 57 cdns,tsd2d-ns = <50>; 58 cdns,tchsh-ns = <4>; 59 cdns,tslch-ns = <4>; 60 }; 61 }; 62