1XILINX AXI ETHERNET Device Tree Bindings 2-------------------------------------------------------- 3 4Also called AXI 1G/2.5G Ethernet Subsystem, the xilinx axi ethernet IP core 5provides connectivity to an external ethernet PHY supporting different 6interfaces: MII, GMII, RGMII, SGMII, 1000BaseX. It also includes two 7segments of memory for buffering TX and RX, as well as the capability of 8offloading TX/RX checksum calculation off the processor. 9 10Management configuration is done through the AXI interface, while payload is 11sent and received through means of an AXI DMA controller. This driver 12includes the DMA driver code, so this driver is incompatible with AXI DMA 13driver. 14 15For more details about mdio please refer phy.txt file in the same directory. 16 17Required properties: 18- compatible : Must be one of "xlnx,axi-ethernet-1.00.a", 19 "xlnx,axi-ethernet-1.01.a", "xlnx,axi-ethernet-2.01.a" 20- reg : Address and length of the IO space. 21- interrupts : Should be a list of two interrupt, TX and RX. 22- phy-handle : Should point to the external phy device. 23 See ethernet.txt file in the same directory. 24- xlnx,rxmem : Set to allocated memory buffer for Rx/Tx in the hardware 25 26Optional properties: 27- phy-mode : See ethernet.txt 28- xlnx,phy-type : Deprecated, do not use, but still accepted in preference 29 to phy-mode. 30- xlnx,txcsum : 0 or empty for disabling TX checksum offload, 31 1 to enable partial TX checksum offload, 32 2 to enable full TX checksum offload 33- xlnx,rxcsum : Same values as xlnx,txcsum but for RX checksum offload 34 35Example: 36 axi_ethernet_eth: ethernet@40c00000 { 37 compatible = "xlnx,axi-ethernet-1.00.a"; 38 device_type = "network"; 39 interrupt-parent = <µblaze_0_axi_intc>; 40 interrupts = <2 0>; 41 phy-mode = "mii"; 42 reg = <0x40c00000 0x40000>; 43 xlnx,rxcsum = <0x2>; 44 xlnx,rxmem = <0x800>; 45 xlnx,txcsum = <0x2>; 46 phy-handle = <&phy0>; 47 axi_ethernetlite_0_mdio: mdio { 48 #address-cells = <1>; 49 #size-cells = <0>; 50 phy0: phy@0 { 51 device_type = "ethernet-phy"; 52 reg = <1>; 53 }; 54 }; 55 }; 56