1Freescale Synchronous Audio Interface (SAI). 2 3The SAI is based on I2S module that used communicating with audio codecs, 4which provides a synchronous audio interface that supports fullduplex 5serial interfaces with frame synchronization such as I2S, AC97, TDM, and 6codec/DSP interfaces. 7 8Required properties: 9 10 - compatible : Compatible list, contains "fsl,vf610-sai", 11 "fsl,imx6sx-sai" or "fsl,imx6ul-sai" 12 13 - reg : Offset and length of the register set for the device. 14 15 - clocks : Must contain an entry for each entry in clock-names. 16 17 - clock-names : Must include the "bus" for register access and 18 "mclk1", "mclk2", "mclk3" for bit clock and frame 19 clock providing. 20 - dmas : Generic dma devicetree binding as described in 21 Documentation/devicetree/bindings/dma/dma.txt. 22 23 - dma-names : Two dmas have to be defined, "tx" and "rx". 24 25 - pinctrl-names : Must contain a "default" entry. 26 27 - pinctrl-NNN : One property must exist for each entry in 28 pinctrl-names. See ../pinctrl/pinctrl-bindings.txt 29 for details of the property values. 30 31 - lsb-first : Configures whether the LSB or the MSB is transmitted 32 first for the fifo data. If this property is absent, 33 the MSB is transmitted first as default, or the LSB 34 is transmitted first. 35 36 - fsl,sai-synchronous-rx: This is a boolean property. If present, indicating 37 that SAI will work in the synchronous mode (sync Tx 38 with Rx) which means both the transimitter and the 39 receiver will send and receive data by following 40 receiver's bit clocks and frame sync clocks. 41 42 - fsl,sai-asynchronous: This is a boolean property. If present, indicating 43 that SAI will work in the asynchronous mode, which 44 means both transimitter and receiver will send and 45 receive data by following their own bit clocks and 46 frame sync clocks separately. 47 48Optional properties: 49 50 - big-endian : Boolean property, required if all the SAI 51 registers are big-endian rather than little-endian. 52 53Optional properties (for mx6ul): 54 55 - fsl,sai-mclk-direction-output: This is a boolean property. If present, 56 indicates that SAI will output the SAI MCLK clock. 57 58Note: 59- If both fsl,sai-asynchronous and fsl,sai-synchronous-rx are absent, the 60 default synchronous mode (sync Rx with Tx) will be used, which means both 61 transimitter and receiver will send and receive data by following clocks 62 of transimitter. 63- fsl,sai-asynchronous and fsl,sai-synchronous-rx are exclusive. 64 65Example: 66sai2: sai@40031000 { 67 compatible = "fsl,vf610-sai"; 68 reg = <0x40031000 0x1000>; 69 pinctrl-names = "default"; 70 pinctrl-0 = <&pinctrl_sai2_1>; 71 clocks = <&clks VF610_CLK_PLATFORM_BUS>, 72 <&clks VF610_CLK_SAI2>, 73 <&clks 0>, <&clks 0>; 74 clock-names = "bus", "mclk1", "mclk2", "mclk3"; 75 dma-names = "tx", "rx"; 76 dmas = <&edma0 0 VF610_EDMA_MUXID0_SAI2_TX>, 77 <&edma0 0 VF610_EDMA_MUXID0_SAI2_RX>; 78 big-endian; 79 lsb-first; 80}; 81