1synopsys DWC3 CORE 2 3DWC3- USB3 CONTROLLER. Complies to the generic USB binding properties 4 as described in 'usb/generic.txt' 5 6Required properties: 7 - compatible: must be "snps,dwc3" 8 - reg : Address and length of the register set for the device 9 - interrupts: Interrupts used by the dwc3 controller. 10 - clock-names: should contain "ref", "bus_early", "suspend" 11 - clocks: list of phandle and clock specifier pairs corresponding to 12 entries in the clock-names property. 13 14Exception for clocks: 15 clocks are optional if the parent node (i.e. glue-layer) is compatible to 16 one of the following: 17 "amlogic,meson-axg-dwc3" 18 "amlogic,meson-gxl-dwc3" 19 "cavium,octeon-7130-usb-uctl" 20 "qcom,dwc3" 21 "samsung,exynos5250-dwusb3" 22 "samsung,exynos7-dwusb3" 23 "sprd,sc9860-dwc3" 24 "st,stih407-dwc3" 25 "ti,am437x-dwc3" 26 "ti,dwc3" 27 "ti,keystone-dwc3" 28 "rockchip,rk3399-dwc3" 29 "xlnx,zynqmp-dwc3" 30 31Optional properties: 32 - usb-phy : array of phandle for the PHY device. The first element 33 in the array is expected to be a handle to the USB2/HS PHY and 34 the second element is expected to be a handle to the USB3/SS PHY 35 - phys: from the *Generic PHY* bindings 36 - phy-names: from the *Generic PHY* bindings; supported names are "usb2-phy" 37 or "usb3-phy". 38 - resets: a single pair of phandle and reset specifier 39 - snps,usb3_lpm_capable: determines if platform is USB3 LPM capable 40 - snps,disable_scramble_quirk: true when SW should disable data scrambling. 41 Only really useful for FPGA builds. 42 - snps,has-lpm-erratum: true when DWC3 was configured with LPM Erratum enabled 43 - snps,lpm-nyet-threshold: LPM NYET threshold 44 - snps,u2exit_lfps_quirk: set if we want to enable u2exit lfps quirk 45 - snps,u2ss_inp3_quirk: set if we enable P3 OK for U2/SS Inactive quirk 46 - snps,req_p1p2p3_quirk: when set, the core will always request for 47 P1/P2/P3 transition sequence. 48 - snps,del_p1p2p3_quirk: when set core will delay P1/P2/P3 until a certain 49 amount of 8B10B errors occur. 50 - snps,del_phy_power_chg_quirk: when set core will delay PHY power change 51 from P0 to P1/P2/P3. 52 - snps,lfps_filter_quirk: when set core will filter LFPS reception. 53 - snps,rx_detect_poll_quirk: when set core will disable a 400us delay to start 54 Polling LFPS after RX.Detect. 55 - snps,tx_de_emphasis_quirk: when set core will set Tx de-emphasis value. 56 - snps,tx_de_emphasis: the value driven to the PHY is controlled by the 57 LTSSM during USB3 Compliance mode. 58 - snps,dis_u3_susphy_quirk: when set core will disable USB3 suspend phy. 59 - snps,dis_u2_susphy_quirk: when set core will disable USB2 suspend phy. 60 - snps,dis_enblslpm_quirk: when set clears the enblslpm in GUSB2PHYCFG, 61 disabling the suspend signal to the PHY. 62 - snps,dis_rxdet_inp3_quirk: when set core will disable receiver detection 63 in PHY P3 power state. 64 - snps,dis-u2-freeclk-exists-quirk: when set, clear the u2_freeclk_exists 65 in GUSB2PHYCFG, specify that USB2 PHY doesn't provide 66 a free-running PHY clock. 67 - snps,dis-del-phy-power-chg-quirk: when set core will change PHY power 68 from P0 to P1/P2/P3 without delay. 69 - snps,dis-tx-ipgap-linecheck-quirk: when set, disable u2mac linestate check 70 during HS transmit. 71 - snps,parkmode-disable-ss-quirk: when set, all SuperSpeed bus instances in 72 park mode are disabled. 73 - snps,dis_metastability_quirk: when set, disable metastability workaround. 74 CAUTION: use only if you are absolutely sure of it. 75 - snps,is-utmi-l1-suspend: true when DWC3 asserts output signal 76 utmi_l1_suspend_n, false when asserts utmi_sleep_n 77 - snps,hird-threshold: HIRD threshold 78 - snps,hsphy_interface: High-Speed PHY interface selection between "utmi" for 79 UTMI+ and "ulpi" for ULPI when the DWC_USB3_HSPHY_INTERFACE has value 3. 80 - snps,quirk-frame-length-adjustment: Value for GFLADJ_30MHZ field of GFLADJ 81 register for post-silicon frame length adjustment when the 82 fladj_30mhz_sdbnd signal is invalid or incorrect. 83 - snps,rx-thr-num-pkt-prd: periodic ESS RX packet threshold count - host mode 84 only. Set this and rx-max-burst-prd to a valid, 85 non-zero value 1-16 (DWC_usb31 programming guide 86 section 1.2.4) to enable periodic ESS RX threshold. 87 - snps,rx-max-burst-prd: max periodic ESS RX burst size - host mode only. Set 88 this and rx-thr-num-pkt-prd to a valid, non-zero value 89 1-16 (DWC_usb31 programming guide section 1.2.4) to 90 enable periodic ESS RX threshold. 91 - snps,tx-thr-num-pkt-prd: periodic ESS TX packet threshold count - host mode 92 only. Set this and tx-max-burst-prd to a valid, 93 non-zero value 1-16 (DWC_usb31 programming guide 94 section 1.2.3) to enable periodic ESS TX threshold. 95 - snps,tx-max-burst-prd: max periodic ESS TX burst size - host mode only. Set 96 this and tx-thr-num-pkt-prd to a valid, non-zero value 97 1-16 (DWC_usb31 programming guide section 1.2.3) to 98 enable periodic ESS TX threshold. 99 100 - <DEPRECATED> tx-fifo-resize: determines if the FIFO *has* to be reallocated. 101 - snps,incr-burst-type-adjustment: Value for INCR burst type of GSBUSCFG0 102 register, undefined length INCR burst type enable and INCRx type. 103 When just one value, which means INCRX burst mode enabled. When 104 more than one value, which means undefined length INCR burst type 105 enabled. The values can be 1, 4, 8, 16, 32, 64, 128 and 256. 106 107 - in addition all properties from usb-xhci.txt from the current directory are 108 supported as well 109 110 111This is usually a subnode to DWC3 glue to which it is connected. 112 113dwc3@4a030000 { 114 compatible = "snps,dwc3"; 115 reg = <0x4a030000 0xcfff>; 116 interrupts = <0 92 4> 117 usb-phy = <&usb2_phy>, <&usb3,phy>; 118 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 119}; 120