1Samsung Exynos SoC USB controller 2 3The USB devices interface with USB controllers on Exynos SOCs. 4The device node has following properties. 5 6EHCI 7Required properties: 8 - compatible: should be "samsung,exynos4210-ehci" for USB 2.0 9 EHCI controller in host mode. 10 - reg: physical base address of the controller and length of memory mapped 11 region. 12 - interrupts: interrupt number to the cpu. 13 - clocks: from common clock binding: handle to usb clock. 14 - clock-names: from common clock binding: Shall be "usbhost". 15 - port: if in the SoC there are EHCI phys, they should be listed here. 16 One phy per port. Each port should have following entries: 17 - reg: port number on EHCI controller, e.g 18 On Exynos5250, port 0 is USB2.0 otg phy 19 port 1 is HSIC phy0 20 port 2 is HSIC phy1 21 - phys: from the *Generic PHY* bindings; specifying phy used by port. 22 23Optional properties: 24 - samsung,vbus-gpio: if present, specifies the GPIO that 25 needs to be pulled up for the bus to be powered. 26 27Example: 28 29 usb@12110000 { 30 compatible = "samsung,exynos4210-ehci"; 31 reg = <0x12110000 0x100>; 32 interrupts = <0 71 0>; 33 samsung,vbus-gpio = <&gpx2 6 1 3 3>; 34 35 clocks = <&clock 285>; 36 clock-names = "usbhost"; 37 38 #address-cells = <1>; 39 #size-cells = <0>; 40 port@0 { 41 reg = <0>; 42 phys = <&usb2phy 1>; 43 }; 44 }; 45 46OHCI 47Required properties: 48 - compatible: should be "samsung,exynos4210-ohci" for USB 2.0 49 OHCI companion controller in host mode. 50 - reg: physical base address of the controller and length of memory mapped 51 region. 52 - interrupts: interrupt number to the cpu. 53 - clocks: from common clock binding: handle to usb clock. 54 - clock-names: from common clock binding: Shall be "usbhost". 55 - port: if in the SoC there are OHCI phys, they should be listed here. 56 One phy per port. Each port should have following entries: 57 - reg: port number on OHCI controller, e.g 58 On Exynos5250, port 0 is USB2.0 otg phy 59 port 1 is HSIC phy0 60 port 2 is HSIC phy1 61 - phys: from the *Generic PHY* bindings, specifying phy used by port. 62 63Example: 64 usb@12120000 { 65 compatible = "samsung,exynos4210-ohci"; 66 reg = <0x12120000 0x100>; 67 interrupts = <0 71 0>; 68 69 clocks = <&clock 285>; 70 clock-names = "usbhost"; 71 72 #address-cells = <1>; 73 #size-cells = <0>; 74 port@0 { 75 reg = <0>; 76 phys = <&usb2phy 1>; 77 }; 78 79 }; 80 81DWC3 82Required properties: 83 - compatible: should be one of the following - 84 "samsung,exynos5250-dwusb3": for USB 3.0 DWC3 controller on 85 Exynos5250/5420. 86 "samsung,exynos7-dwusb3": for USB 3.0 DWC3 controller on Exynos7. 87 - #address-cells, #size-cells : should be '1' if the device has sub-nodes 88 with 'reg' property. 89 - ranges: allows valid 1:1 translation between child's address space and 90 parent's address space 91 - clocks: Clock IDs array as required by the controller. 92 - clock-names: names of clocks correseponding to IDs in the clock property 93 - vdd10-supply: 1.0V powr supply 94 - vdd33-supply: 3.0V/3.3V power supply 95 96Sub-nodes: 97The dwc3 core should be added as subnode to Exynos dwc3 glue. 98- dwc3 : 99 The binding details of dwc3 can be found in: 100 Documentation/devicetree/bindings/usb/dwc3.txt 101 102Example: 103 usb@12000000 { 104 compatible = "samsung,exynos5250-dwusb3"; 105 clocks = <&clock 286>; 106 clock-names = "usbdrd30"; 107 #address-cells = <1>; 108 #size-cells = <1>; 109 ranges; 110 vdd10-supply = <&ldo11_reg>; 111 vdd33-supply = <&ldo9_reg>; 112 113 dwc3 { 114 compatible = "synopsys,dwc3"; 115 reg = <0x12000000 0x10000>; 116 interrupts = <0 72 0>; 117 usb-phy = <&usb2_phy &usb3_phy>; 118 }; 119 }; 120