1/* 2 * Device Tree Source for AM4372 SoC 3 * 4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * This file is licensed under the terms of the GNU General Public License 7 * version 2. This program is licensed "as is" without any warranty of any 8 * kind, whether express or implied. 9 */ 10 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/clock/am4.h> 14 15/ { 16 compatible = "ti,am4372", "ti,am43"; 17 interrupt-parent = <&wakeupgen>; 18 #address-cells = <1>; 19 #size-cells = <1>; 20 chosen { }; 21 22 memory@0 { 23 device_type = "memory"; 24 reg = <0 0>; 25 }; 26 27 aliases { 28 i2c0 = &i2c0; 29 i2c1 = &i2c1; 30 i2c2 = &i2c2; 31 serial0 = &uart0; 32 serial1 = &uart1; 33 serial2 = &uart2; 34 serial3 = &uart3; 35 serial4 = &uart4; 36 serial5 = &uart5; 37 ethernet0 = &cpsw_emac0; 38 ethernet1 = &cpsw_emac1; 39 spi0 = &qspi; 40 }; 41 42 cpus { 43 #address-cells = <1>; 44 #size-cells = <0>; 45 cpu: cpu@0 { 46 compatible = "arm,cortex-a9"; 47 device_type = "cpu"; 48 reg = <0>; 49 50 clocks = <&dpll_mpu_ck>; 51 clock-names = "cpu"; 52 53 operating-points-v2 = <&cpu0_opp_table>; 54 55 clock-latency = <300000>; /* From omap-cpufreq driver */ 56 }; 57 }; 58 59 cpu0_opp_table: opp-table { 60 compatible = "operating-points-v2-ti-cpu"; 61 syscon = <&scm_conf>; 62 63 opp50-300000000 { 64 opp-hz = /bits/ 64 <300000000>; 65 opp-microvolt = <950000 931000 969000>; 66 opp-supported-hw = <0xFF 0x01>; 67 opp-suspend; 68 }; 69 70 opp100-600000000 { 71 opp-hz = /bits/ 64 <600000000>; 72 opp-microvolt = <1100000 1078000 1122000>; 73 opp-supported-hw = <0xFF 0x04>; 74 }; 75 76 opp120-720000000 { 77 opp-hz = /bits/ 64 <720000000>; 78 opp-microvolt = <1200000 1176000 1224000>; 79 opp-supported-hw = <0xFF 0x08>; 80 }; 81 82 oppturbo-800000000 { 83 opp-hz = /bits/ 64 <800000000>; 84 opp-microvolt = <1260000 1234800 1285200>; 85 opp-supported-hw = <0xFF 0x10>; 86 }; 87 88 oppnitro-1000000000 { 89 opp-hz = /bits/ 64 <1000000000>; 90 opp-microvolt = <1325000 1298500 1351500>; 91 opp-supported-hw = <0xFF 0x20>; 92 }; 93 }; 94 95 soc { 96 compatible = "ti,omap-infra"; 97 mpu { 98 compatible = "ti,omap4-mpu"; 99 ti,hwmods = "mpu"; 100 pm-sram = <&pm_sram_code 101 &pm_sram_data>; 102 }; 103 }; 104 105 gic: interrupt-controller@48241000 { 106 compatible = "arm,cortex-a9-gic"; 107 interrupt-controller; 108 #interrupt-cells = <3>; 109 reg = <0x48241000 0x1000>, 110 <0x48240100 0x0100>; 111 interrupt-parent = <&gic>; 112 }; 113 114 wakeupgen: interrupt-controller@48281000 { 115 compatible = "ti,omap4-wugen-mpu"; 116 interrupt-controller; 117 #interrupt-cells = <3>; 118 reg = <0x48281000 0x1000>; 119 interrupt-parent = <&gic>; 120 }; 121 122 scu: scu@48240000 { 123 compatible = "arm,cortex-a9-scu"; 124 reg = <0x48240000 0x100>; 125 }; 126 127 global_timer: timer@48240200 { 128 compatible = "arm,cortex-a9-global-timer"; 129 reg = <0x48240200 0x100>; 130 interrupts = <GIC_PPI 11 IRQ_TYPE_EDGE_RISING>; 131 interrupt-parent = <&gic>; 132 clocks = <&mpu_periphclk>; 133 }; 134 135 local_timer: timer@48240600 { 136 compatible = "arm,cortex-a9-twd-timer"; 137 reg = <0x48240600 0x100>; 138 interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE_RISING>; 139 interrupt-parent = <&gic>; 140 clocks = <&mpu_periphclk>; 141 }; 142 143 l2-cache-controller@48242000 { 144 compatible = "arm,pl310-cache"; 145 reg = <0x48242000 0x1000>; 146 cache-unified; 147 cache-level = <2>; 148 }; 149 150 ocp@44000000 { 151 compatible = "ti,am4372-l3-noc", "simple-bus"; 152 #address-cells = <1>; 153 #size-cells = <1>; 154 ranges; 155 ti,hwmods = "l3_main"; 156 ti,no-idle; 157 reg = <0x44000000 0x400000 158 0x44800000 0x400000>; 159 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 160 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 161 162 l4_wkup: l4_wkup@44c00000 { 163 compatible = "ti,am4-l4-wkup", "simple-bus"; 164 #address-cells = <1>; 165 #size-cells = <1>; 166 ranges = <0 0x44c00000 0x287000>; 167 168 wkup_m3: wkup_m3@100000 { 169 compatible = "ti,am4372-wkup-m3"; 170 reg = <0x100000 0x4000>, 171 <0x180000 0x2000>; 172 reg-names = "umem", "dmem"; 173 ti,hwmods = "wkup_m3"; 174 ti,pm-firmware = "am335x-pm-firmware.elf"; 175 }; 176 177 prcm: prcm@1f0000 { 178 compatible = "ti,am4-prcm", "simple-bus"; 179 reg = <0x1f0000 0x11000>; 180 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 181 #address-cells = <1>; 182 #size-cells = <1>; 183 ranges = <0 0x1f0000 0x11000>; 184 185 prcm_clocks: clocks { 186 #address-cells = <1>; 187 #size-cells = <0>; 188 }; 189 190 prcm_clockdomains: clockdomains { 191 }; 192 }; 193 194 scm: scm@210000 { 195 compatible = "ti,am4-scm", "simple-bus"; 196 reg = <0x210000 0x4000>; 197 #address-cells = <1>; 198 #size-cells = <1>; 199 ranges = <0 0x210000 0x4000>; 200 201 am43xx_pinmux: pinmux@800 { 202 compatible = "ti,am437-padconf", 203 "pinctrl-single"; 204 reg = <0x800 0x31c>; 205 #address-cells = <1>; 206 #size-cells = <0>; 207 #pinctrl-cells = <1>; 208 #interrupt-cells = <1>; 209 interrupt-controller; 210 pinctrl-single,register-width = <32>; 211 pinctrl-single,function-mask = <0xffffffff>; 212 }; 213 214 scm_conf: scm_conf@0 { 215 compatible = "syscon"; 216 reg = <0x0 0x800>; 217 #address-cells = <1>; 218 #size-cells = <1>; 219 220 scm_clocks: clocks { 221 #address-cells = <1>; 222 #size-cells = <0>; 223 }; 224 }; 225 226 wkup_m3_ipc: wkup_m3_ipc@1324 { 227 compatible = "ti,am4372-wkup-m3-ipc"; 228 reg = <0x1324 0x44>; 229 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 230 ti,rproc = <&wkup_m3>; 231 mboxes = <&mailbox &mbox_wkupm3>; 232 }; 233 234 edma_xbar: dma-router@f90 { 235 compatible = "ti,am335x-edma-crossbar"; 236 reg = <0xf90 0x40>; 237 #dma-cells = <3>; 238 dma-requests = <64>; 239 dma-masters = <&edma>; 240 }; 241 242 scm_clockdomains: clockdomains { 243 }; 244 }; 245 }; 246 247 emif: emif@4c000000 { 248 compatible = "ti,emif-am4372"; 249 reg = <0x4c000000 0x1000000>; 250 ti,hwmods = "emif"; 251 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 252 ti,no-idle; 253 sram = <&pm_sram_code 254 &pm_sram_data>; 255 }; 256 257 edma: edma@49000000 { 258 compatible = "ti,edma3-tpcc"; 259 ti,hwmods = "tpcc"; 260 reg = <0x49000000 0x10000>; 261 reg-names = "edma3_cc"; 262 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 264 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 265 interrupt-names = "edma3_ccint", "edma3_mperr", 266 "edma3_ccerrint"; 267 dma-requests = <64>; 268 #dma-cells = <2>; 269 270 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 5>, 271 <&edma_tptc2 0>; 272 273 ti,edma-memcpy-channels = <58 59>; 274 }; 275 276 edma_tptc0: tptc@49800000 { 277 compatible = "ti,edma3-tptc"; 278 ti,hwmods = "tptc0"; 279 reg = <0x49800000 0x100000>; 280 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 281 interrupt-names = "edma3_tcerrint"; 282 }; 283 284 edma_tptc1: tptc@49900000 { 285 compatible = "ti,edma3-tptc"; 286 ti,hwmods = "tptc1"; 287 reg = <0x49900000 0x100000>; 288 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; 289 interrupt-names = "edma3_tcerrint"; 290 }; 291 292 edma_tptc2: tptc@49a00000 { 293 compatible = "ti,edma3-tptc"; 294 ti,hwmods = "tptc2"; 295 reg = <0x49a00000 0x100000>; 296 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 297 interrupt-names = "edma3_tcerrint"; 298 }; 299 300 uart0: serial@44e09000 { 301 compatible = "ti,am4372-uart","ti,omap2-uart"; 302 reg = <0x44e09000 0x2000>; 303 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 304 ti,hwmods = "uart1"; 305 }; 306 307 uart1: serial@48022000 { 308 compatible = "ti,am4372-uart","ti,omap2-uart"; 309 reg = <0x48022000 0x2000>; 310 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 311 ti,hwmods = "uart2"; 312 status = "disabled"; 313 }; 314 315 uart2: serial@48024000 { 316 compatible = "ti,am4372-uart","ti,omap2-uart"; 317 reg = <0x48024000 0x2000>; 318 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 319 ti,hwmods = "uart3"; 320 status = "disabled"; 321 }; 322 323 uart3: serial@481a6000 { 324 compatible = "ti,am4372-uart","ti,omap2-uart"; 325 reg = <0x481a6000 0x2000>; 326 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 327 ti,hwmods = "uart4"; 328 status = "disabled"; 329 }; 330 331 uart4: serial@481a8000 { 332 compatible = "ti,am4372-uart","ti,omap2-uart"; 333 reg = <0x481a8000 0x2000>; 334 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 335 ti,hwmods = "uart5"; 336 status = "disabled"; 337 }; 338 339 uart5: serial@481aa000 { 340 compatible = "ti,am4372-uart","ti,omap2-uart"; 341 reg = <0x481aa000 0x2000>; 342 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 343 ti,hwmods = "uart6"; 344 status = "disabled"; 345 }; 346 347 mailbox: mailbox@480c8000 { 348 compatible = "ti,omap4-mailbox"; 349 reg = <0x480C8000 0x200>; 350 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 351 ti,hwmods = "mailbox"; 352 #mbox-cells = <1>; 353 ti,mbox-num-users = <4>; 354 ti,mbox-num-fifos = <8>; 355 mbox_wkupm3: wkup_m3 { 356 ti,mbox-send-noirq; 357 ti,mbox-tx = <0 0 0>; 358 ti,mbox-rx = <0 0 3>; 359 }; 360 }; 361 362 timer1: timer@44e31000 { 363 compatible = "ti,am4372-timer-1ms","ti,am335x-timer-1ms"; 364 reg = <0x44e31000 0x400>; 365 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 366 ti,timer-alwon; 367 ti,hwmods = "timer1"; 368 clocks = <&timer1_fck>; 369 clock-names = "fck"; 370 }; 371 372 timer2: timer@48040000 { 373 compatible = "ti,am4372-timer","ti,am335x-timer"; 374 reg = <0x48040000 0x400>; 375 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 376 ti,hwmods = "timer2"; 377 clocks = <&timer2_fck>; 378 clock-names = "fck"; 379 }; 380 381 timer3: timer@48042000 { 382 compatible = "ti,am4372-timer","ti,am335x-timer"; 383 reg = <0x48042000 0x400>; 384 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 385 ti,hwmods = "timer3"; 386 status = "disabled"; 387 }; 388 389 timer4: timer@48044000 { 390 compatible = "ti,am4372-timer","ti,am335x-timer"; 391 reg = <0x48044000 0x400>; 392 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 393 ti,timer-pwm; 394 ti,hwmods = "timer4"; 395 status = "disabled"; 396 }; 397 398 timer5: timer@48046000 { 399 compatible = "ti,am4372-timer","ti,am335x-timer"; 400 reg = <0x48046000 0x400>; 401 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 402 ti,timer-pwm; 403 ti,hwmods = "timer5"; 404 status = "disabled"; 405 }; 406 407 timer6: timer@48048000 { 408 compatible = "ti,am4372-timer","ti,am335x-timer"; 409 reg = <0x48048000 0x400>; 410 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 411 ti,timer-pwm; 412 ti,hwmods = "timer6"; 413 status = "disabled"; 414 }; 415 416 timer7: timer@4804a000 { 417 compatible = "ti,am4372-timer","ti,am335x-timer"; 418 reg = <0x4804a000 0x400>; 419 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; 420 ti,timer-pwm; 421 ti,hwmods = "timer7"; 422 status = "disabled"; 423 }; 424 425 timer8: timer@481c1000 { 426 compatible = "ti,am4372-timer","ti,am335x-timer"; 427 reg = <0x481c1000 0x400>; 428 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; 429 ti,hwmods = "timer8"; 430 status = "disabled"; 431 }; 432 433 timer9: timer@4833d000 { 434 compatible = "ti,am4372-timer","ti,am335x-timer"; 435 reg = <0x4833d000 0x400>; 436 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; 437 ti,hwmods = "timer9"; 438 status = "disabled"; 439 }; 440 441 timer10: timer@4833f000 { 442 compatible = "ti,am4372-timer","ti,am335x-timer"; 443 reg = <0x4833f000 0x400>; 444 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 445 ti,hwmods = "timer10"; 446 status = "disabled"; 447 }; 448 449 timer11: timer@48341000 { 450 compatible = "ti,am4372-timer","ti,am335x-timer"; 451 reg = <0x48341000 0x400>; 452 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 453 ti,hwmods = "timer11"; 454 status = "disabled"; 455 }; 456 457 counter32k: counter@44e86000 { 458 compatible = "ti,am4372-counter32k","ti,omap-counter32k"; 459 reg = <0x44e86000 0x40>; 460 ti,hwmods = "counter_32k"; 461 }; 462 463 rtc: rtc@44e3e000 { 464 compatible = "ti,am4372-rtc", "ti,am3352-rtc", 465 "ti,da830-rtc"; 466 reg = <0x44e3e000 0x1000>; 467 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH 468 GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 469 ti,hwmods = "rtc"; 470 clocks = <&clk_32768_ck>; 471 clock-names = "int-clk"; 472 system-power-controller; 473 status = "disabled"; 474 }; 475 476 wdt: wdt@44e35000 { 477 compatible = "ti,am4372-wdt","ti,omap3-wdt"; 478 reg = <0x44e35000 0x1000>; 479 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 480 ti,hwmods = "wd_timer2"; 481 }; 482 483 gpio0: gpio@44e07000 { 484 compatible = "ti,am4372-gpio","ti,omap4-gpio"; 485 reg = <0x44e07000 0x1000>; 486 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 487 gpio-controller; 488 #gpio-cells = <2>; 489 interrupt-controller; 490 #interrupt-cells = <2>; 491 ti,hwmods = "gpio1"; 492 status = "disabled"; 493 }; 494 495 gpio1: gpio@4804c000 { 496 compatible = "ti,am4372-gpio","ti,omap4-gpio"; 497 reg = <0x4804c000 0x1000>; 498 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; 499 gpio-controller; 500 #gpio-cells = <2>; 501 interrupt-controller; 502 #interrupt-cells = <2>; 503 ti,hwmods = "gpio2"; 504 status = "disabled"; 505 }; 506 507 gpio2: gpio@481ac000 { 508 compatible = "ti,am4372-gpio","ti,omap4-gpio"; 509 reg = <0x481ac000 0x1000>; 510 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 511 gpio-controller; 512 #gpio-cells = <2>; 513 interrupt-controller; 514 #interrupt-cells = <2>; 515 ti,hwmods = "gpio3"; 516 status = "disabled"; 517 }; 518 519 gpio3: gpio@481ae000 { 520 compatible = "ti,am4372-gpio","ti,omap4-gpio"; 521 reg = <0x481ae000 0x1000>; 522 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 523 gpio-controller; 524 #gpio-cells = <2>; 525 interrupt-controller; 526 #interrupt-cells = <2>; 527 ti,hwmods = "gpio4"; 528 status = "disabled"; 529 }; 530 531 gpio4: gpio@48320000 { 532 compatible = "ti,am4372-gpio","ti,omap4-gpio"; 533 reg = <0x48320000 0x1000>; 534 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 535 gpio-controller; 536 #gpio-cells = <2>; 537 interrupt-controller; 538 #interrupt-cells = <2>; 539 ti,hwmods = "gpio5"; 540 status = "disabled"; 541 }; 542 543 gpio5: gpio@48322000 { 544 compatible = "ti,am4372-gpio","ti,omap4-gpio"; 545 reg = <0x48322000 0x1000>; 546 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 547 gpio-controller; 548 #gpio-cells = <2>; 549 interrupt-controller; 550 #interrupt-cells = <2>; 551 ti,hwmods = "gpio6"; 552 status = "disabled"; 553 }; 554 555 hwspinlock: spinlock@480ca000 { 556 compatible = "ti,omap4-hwspinlock"; 557 reg = <0x480ca000 0x1000>; 558 ti,hwmods = "spinlock"; 559 #hwlock-cells = <1>; 560 }; 561 562 i2c0: i2c@44e0b000 { 563 compatible = "ti,am4372-i2c","ti,omap4-i2c"; 564 reg = <0x44e0b000 0x1000>; 565 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 566 ti,hwmods = "i2c1"; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 status = "disabled"; 570 }; 571 572 i2c1: i2c@4802a000 { 573 compatible = "ti,am4372-i2c","ti,omap4-i2c"; 574 reg = <0x4802a000 0x1000>; 575 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; 576 ti,hwmods = "i2c2"; 577 #address-cells = <1>; 578 #size-cells = <0>; 579 status = "disabled"; 580 }; 581 582 i2c2: i2c@4819c000 { 583 compatible = "ti,am4372-i2c","ti,omap4-i2c"; 584 reg = <0x4819c000 0x1000>; 585 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 586 ti,hwmods = "i2c3"; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 status = "disabled"; 590 }; 591 592 spi0: spi@48030000 { 593 compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; 594 reg = <0x48030000 0x400>; 595 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 596 ti,hwmods = "spi0"; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 status = "disabled"; 600 }; 601 602 mmc1: mmc@48060000 { 603 compatible = "ti,omap4-hsmmc"; 604 reg = <0x48060000 0x1000>; 605 ti,hwmods = "mmc1"; 606 ti,dual-volt; 607 ti,needs-special-reset; 608 dmas = <&edma 24 0>, 609 <&edma 25 0>; 610 dma-names = "tx", "rx"; 611 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 612 status = "disabled"; 613 }; 614 615 mmc2: mmc@481d8000 { 616 compatible = "ti,omap4-hsmmc"; 617 reg = <0x481d8000 0x1000>; 618 ti,hwmods = "mmc2"; 619 ti,needs-special-reset; 620 dmas = <&edma 2 0>, 621 <&edma 3 0>; 622 dma-names = "tx", "rx"; 623 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 624 status = "disabled"; 625 }; 626 627 mmc3: mmc@47810000 { 628 compatible = "ti,omap4-hsmmc"; 629 reg = <0x47810000 0x1000>; 630 ti,hwmods = "mmc3"; 631 ti,needs-special-reset; 632 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 633 status = "disabled"; 634 }; 635 636 spi1: spi@481a0000 { 637 compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; 638 reg = <0x481a0000 0x400>; 639 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; 640 ti,hwmods = "spi1"; 641 #address-cells = <1>; 642 #size-cells = <0>; 643 status = "disabled"; 644 }; 645 646 spi2: spi@481a2000 { 647 compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; 648 reg = <0x481a2000 0x400>; 649 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; 650 ti,hwmods = "spi2"; 651 #address-cells = <1>; 652 #size-cells = <0>; 653 status = "disabled"; 654 }; 655 656 spi3: spi@481a4000 { 657 compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; 658 reg = <0x481a4000 0x400>; 659 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; 660 ti,hwmods = "spi3"; 661 #address-cells = <1>; 662 #size-cells = <0>; 663 status = "disabled"; 664 }; 665 666 spi4: spi@48345000 { 667 compatible = "ti,am4372-mcspi","ti,omap4-mcspi"; 668 reg = <0x48345000 0x400>; 669 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; 670 ti,hwmods = "spi4"; 671 #address-cells = <1>; 672 #size-cells = <0>; 673 status = "disabled"; 674 }; 675 676 mac: ethernet@4a100000 { 677 compatible = "ti,am4372-cpsw","ti,cpsw"; 678 reg = <0x4a100000 0x800 679 0x4a101200 0x100>; 680 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 681 GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 682 GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 683 GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 684 #address-cells = <1>; 685 #size-cells = <1>; 686 ti,hwmods = "cpgmac0"; 687 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>, 688 <&dpll_clksel_mac_clk>; 689 clock-names = "fck", "cpts", "50mclk"; 690 assigned-clocks = <&dpll_clksel_mac_clk>; 691 assigned-clock-rates = <50000000>; 692 status = "disabled"; 693 cpdma_channels = <8>; 694 ale_entries = <1024>; 695 bd_ram_size = <0x2000>; 696 mac_control = <0x20>; 697 slaves = <2>; 698 active_slave = <0>; 699 cpts_clock_mult = <0x80000000>; 700 cpts_clock_shift = <29>; 701 ranges; 702 syscon = <&scm_conf>; 703 704 davinci_mdio: mdio@4a101000 { 705 compatible = "ti,am4372-mdio","ti,cpsw-mdio","ti,davinci_mdio"; 706 reg = <0x4a101000 0x100>; 707 #address-cells = <1>; 708 #size-cells = <0>; 709 ti,hwmods = "davinci_mdio"; 710 bus_freq = <1000000>; 711 status = "disabled"; 712 }; 713 714 cpsw_emac0: slave@4a100200 { 715 /* Filled in by U-Boot */ 716 mac-address = [ 00 00 00 00 00 00 ]; 717 }; 718 719 cpsw_emac1: slave@4a100300 { 720 /* Filled in by U-Boot */ 721 mac-address = [ 00 00 00 00 00 00 ]; 722 }; 723 724 phy_sel: cpsw-phy-sel@44e10650 { 725 compatible = "ti,am43xx-cpsw-phy-sel"; 726 reg= <0x44e10650 0x4>; 727 reg-names = "gmii-sel"; 728 }; 729 }; 730 731 epwmss0: epwmss@48300000 { 732 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 733 reg = <0x48300000 0x10>; 734 #address-cells = <1>; 735 #size-cells = <1>; 736 ranges; 737 ti,hwmods = "epwmss0"; 738 status = "disabled"; 739 740 ecap0: ecap@48300100 { 741 compatible = "ti,am4372-ecap", 742 "ti,am3352-ecap", 743 "ti,am33xx-ecap"; 744 #pwm-cells = <3>; 745 reg = <0x48300100 0x80>; 746 clocks = <&l4ls_gclk>; 747 clock-names = "fck"; 748 status = "disabled"; 749 }; 750 751 ehrpwm0: pwm@48300200 { 752 compatible = "ti,am4372-ehrpwm", 753 "ti,am3352-ehrpwm", 754 "ti,am33xx-ehrpwm"; 755 #pwm-cells = <3>; 756 reg = <0x48300200 0x80>; 757 clocks = <&ehrpwm0_tbclk>, <&l4ls_gclk>; 758 clock-names = "tbclk", "fck"; 759 status = "disabled"; 760 }; 761 }; 762 763 epwmss1: epwmss@48302000 { 764 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 765 reg = <0x48302000 0x10>; 766 #address-cells = <1>; 767 #size-cells = <1>; 768 ranges; 769 ti,hwmods = "epwmss1"; 770 status = "disabled"; 771 772 ecap1: ecap@48302100 { 773 compatible = "ti,am4372-ecap", 774 "ti,am3352-ecap", 775 "ti,am33xx-ecap"; 776 #pwm-cells = <3>; 777 reg = <0x48302100 0x80>; 778 clocks = <&l4ls_gclk>; 779 clock-names = "fck"; 780 status = "disabled"; 781 }; 782 783 ehrpwm1: pwm@48302200 { 784 compatible = "ti,am4372-ehrpwm", 785 "ti,am3352-ehrpwm", 786 "ti,am33xx-ehrpwm"; 787 #pwm-cells = <3>; 788 reg = <0x48302200 0x80>; 789 clocks = <&ehrpwm1_tbclk>, <&l4ls_gclk>; 790 clock-names = "tbclk", "fck"; 791 status = "disabled"; 792 }; 793 }; 794 795 epwmss2: epwmss@48304000 { 796 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 797 reg = <0x48304000 0x10>; 798 #address-cells = <1>; 799 #size-cells = <1>; 800 ranges; 801 ti,hwmods = "epwmss2"; 802 status = "disabled"; 803 804 ecap2: ecap@48304100 { 805 compatible = "ti,am4372-ecap", 806 "ti,am3352-ecap", 807 "ti,am33xx-ecap"; 808 #pwm-cells = <3>; 809 reg = <0x48304100 0x80>; 810 clocks = <&l4ls_gclk>; 811 clock-names = "fck"; 812 status = "disabled"; 813 }; 814 815 ehrpwm2: pwm@48304200 { 816 compatible = "ti,am4372-ehrpwm", 817 "ti,am3352-ehrpwm", 818 "ti,am33xx-ehrpwm"; 819 #pwm-cells = <3>; 820 reg = <0x48304200 0x80>; 821 clocks = <&ehrpwm2_tbclk>, <&l4ls_gclk>; 822 clock-names = "tbclk", "fck"; 823 status = "disabled"; 824 }; 825 }; 826 827 epwmss3: epwmss@48306000 { 828 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 829 reg = <0x48306000 0x10>; 830 #address-cells = <1>; 831 #size-cells = <1>; 832 ranges; 833 ti,hwmods = "epwmss3"; 834 status = "disabled"; 835 836 ehrpwm3: pwm@48306200 { 837 compatible = "ti,am4372-ehrpwm", 838 "ti,am3352-ehrpwm", 839 "ti,am33xx-ehrpwm"; 840 #pwm-cells = <3>; 841 reg = <0x48306200 0x80>; 842 clocks = <&ehrpwm3_tbclk>, <&l4ls_gclk>; 843 clock-names = "tbclk", "fck"; 844 status = "disabled"; 845 }; 846 }; 847 848 epwmss4: epwmss@48308000 { 849 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 850 reg = <0x48308000 0x10>; 851 #address-cells = <1>; 852 #size-cells = <1>; 853 ranges; 854 ti,hwmods = "epwmss4"; 855 status = "disabled"; 856 857 ehrpwm4: pwm@48308200 { 858 compatible = "ti,am4372-ehrpwm", 859 "ti,am3352-ehrpwm", 860 "ti,am33xx-ehrpwm"; 861 #pwm-cells = <3>; 862 reg = <0x48308200 0x80>; 863 clocks = <&ehrpwm4_tbclk>, <&l4ls_gclk>; 864 clock-names = "tbclk", "fck"; 865 status = "disabled"; 866 }; 867 }; 868 869 epwmss5: epwmss@4830a000 { 870 compatible = "ti,am4372-pwmss","ti,am33xx-pwmss"; 871 reg = <0x4830a000 0x10>; 872 #address-cells = <1>; 873 #size-cells = <1>; 874 ranges; 875 ti,hwmods = "epwmss5"; 876 status = "disabled"; 877 878 ehrpwm5: pwm@4830a200 { 879 compatible = "ti,am4372-ehrpwm", 880 "ti,am3352-ehrpwm", 881 "ti,am33xx-ehrpwm"; 882 #pwm-cells = <3>; 883 reg = <0x4830a200 0x80>; 884 clocks = <&ehrpwm5_tbclk>, <&l4ls_gclk>; 885 clock-names = "tbclk", "fck"; 886 status = "disabled"; 887 }; 888 }; 889 890 tscadc: tscadc@44e0d000 { 891 compatible = "ti,am3359-tscadc"; 892 reg = <0x44e0d000 0x1000>; 893 ti,hwmods = "adc_tsc"; 894 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 895 clocks = <&adc_tsc_fck>; 896 clock-names = "fck"; 897 status = "disabled"; 898 dmas = <&edma 53 0>, <&edma 57 0>; 899 dma-names = "fifo0", "fifo1"; 900 901 tsc { 902 compatible = "ti,am3359-tsc"; 903 }; 904 905 adc { 906 #io-channel-cells = <1>; 907 compatible = "ti,am3359-adc"; 908 }; 909 910 }; 911 912 sham: sham@53100000 { 913 compatible = "ti,omap5-sham"; 914 ti,hwmods = "sham"; 915 reg = <0x53100000 0x300>; 916 dmas = <&edma 36 0>; 917 dma-names = "rx"; 918 interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; 919 }; 920 921 aes: aes@53501000 { 922 compatible = "ti,omap4-aes"; 923 ti,hwmods = "aes"; 924 reg = <0x53501000 0xa0>; 925 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 926 dmas = <&edma 6 0>, 927 <&edma 5 0>; 928 dma-names = "tx", "rx"; 929 }; 930 931 des: des@53701000 { 932 compatible = "ti,omap4-des"; 933 ti,hwmods = "des"; 934 reg = <0x53701000 0xa0>; 935 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; 936 dmas = <&edma 34 0>, 937 <&edma 33 0>; 938 dma-names = "tx", "rx"; 939 }; 940 941 rng: rng@48310000 { 942 compatible = "ti,omap4-rng"; 943 ti,hwmods = "rng"; 944 reg = <0x48310000 0x2000>; 945 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 946 }; 947 948 mcasp0: mcasp@48038000 { 949 compatible = "ti,am33xx-mcasp-audio"; 950 ti,hwmods = "mcasp0"; 951 reg = <0x48038000 0x2000>, 952 <0x46000000 0x400000>; 953 reg-names = "mpu", "dat"; 954 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 956 interrupt-names = "tx", "rx"; 957 status = "disabled"; 958 dmas = <&edma 8 2>, 959 <&edma 9 2>; 960 dma-names = "tx", "rx"; 961 }; 962 963 mcasp1: mcasp@4803c000 { 964 compatible = "ti,am33xx-mcasp-audio"; 965 ti,hwmods = "mcasp1"; 966 reg = <0x4803C000 0x2000>, 967 <0x46400000 0x400000>; 968 reg-names = "mpu", "dat"; 969 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>, 970 <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 971 interrupt-names = "tx", "rx"; 972 status = "disabled"; 973 dmas = <&edma 10 2>, 974 <&edma 11 2>; 975 dma-names = "tx", "rx"; 976 }; 977 978 elm: elm@48080000 { 979 compatible = "ti,am3352-elm"; 980 reg = <0x48080000 0x2000>; 981 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 982 ti,hwmods = "elm"; 983 clocks = <&l4ls_gclk>; 984 clock-names = "fck"; 985 status = "disabled"; 986 }; 987 988 gpmc: gpmc@50000000 { 989 compatible = "ti,am3352-gpmc"; 990 ti,hwmods = "gpmc"; 991 dmas = <&edma 52 0>; 992 dma-names = "rxtx"; 993 clocks = <&l3s_gclk>; 994 clock-names = "fck"; 995 reg = <0x50000000 0x2000>; 996 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 997 gpmc,num-cs = <7>; 998 gpmc,num-waitpins = <2>; 999 #address-cells = <2>; 1000 #size-cells = <1>; 1001 interrupt-controller; 1002 #interrupt-cells = <2>; 1003 gpio-controller; 1004 #gpio-cells = <2>; 1005 status = "disabled"; 1006 }; 1007 1008 ocp2scp0: ocp2scp@483a8000 { 1009 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; 1010 #address-cells = <1>; 1011 #size-cells = <1>; 1012 ranges; 1013 ti,hwmods = "ocp2scp0"; 1014 1015 usb2_phy1: phy@483a8000 { 1016 compatible = "ti,am437x-usb2"; 1017 reg = <0x483a8000 0x8000>; 1018 syscon-phy-power = <&scm_conf 0x620>; 1019 clocks = <&usb_phy0_always_on_clk32k>, 1020 <&l4_per_clkctrl AM4_USB_OTG_SS0_CLKCTRL 8>; 1021 clock-names = "wkupclk", "refclk"; 1022 #phy-cells = <0>; 1023 status = "disabled"; 1024 }; 1025 }; 1026 1027 ocp2scp1: ocp2scp@483e8000 { 1028 compatible = "ti,am437x-ocp2scp", "ti,omap-ocp2scp"; 1029 #address-cells = <1>; 1030 #size-cells = <1>; 1031 ranges; 1032 ti,hwmods = "ocp2scp1"; 1033 1034 usb2_phy2: phy@483e8000 { 1035 compatible = "ti,am437x-usb2"; 1036 reg = <0x483e8000 0x8000>; 1037 syscon-phy-power = <&scm_conf 0x628>; 1038 clocks = <&usb_phy1_always_on_clk32k>, 1039 <&l4_per_clkctrl AM4_USB_OTG_SS1_CLKCTRL 8>; 1040 clock-names = "wkupclk", "refclk"; 1041 #phy-cells = <0>; 1042 status = "disabled"; 1043 }; 1044 }; 1045 1046 dwc3_1: omap_dwc3@48380000 { 1047 compatible = "ti,am437x-dwc3"; 1048 ti,hwmods = "usb_otg_ss0"; 1049 reg = <0x48380000 0x10000>; 1050 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1051 #address-cells = <1>; 1052 #size-cells = <1>; 1053 utmi-mode = <1>; 1054 ranges; 1055 1056 usb1: usb@48390000 { 1057 compatible = "synopsys,dwc3"; 1058 reg = <0x48390000 0x10000>; 1059 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 1062 interrupt-names = "peripheral", 1063 "host", 1064 "otg"; 1065 phys = <&usb2_phy1>; 1066 phy-names = "usb2-phy"; 1067 maximum-speed = "high-speed"; 1068 dr_mode = "otg"; 1069 status = "disabled"; 1070 snps,dis_u3_susphy_quirk; 1071 snps,dis_u2_susphy_quirk; 1072 }; 1073 }; 1074 1075 dwc3_2: omap_dwc3@483c0000 { 1076 compatible = "ti,am437x-dwc3"; 1077 ti,hwmods = "usb_otg_ss1"; 1078 reg = <0x483c0000 0x10000>; 1079 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 1080 #address-cells = <1>; 1081 #size-cells = <1>; 1082 utmi-mode = <1>; 1083 ranges; 1084 1085 usb2: usb@483d0000 { 1086 compatible = "synopsys,dwc3"; 1087 reg = <0x483d0000 0x10000>; 1088 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 1091 interrupt-names = "peripheral", 1092 "host", 1093 "otg"; 1094 phys = <&usb2_phy2>; 1095 phy-names = "usb2-phy"; 1096 maximum-speed = "high-speed"; 1097 dr_mode = "otg"; 1098 status = "disabled"; 1099 snps,dis_u3_susphy_quirk; 1100 snps,dis_u2_susphy_quirk; 1101 }; 1102 }; 1103 1104 qspi: spi@47900000 { 1105 compatible = "ti,am4372-qspi"; 1106 reg = <0x47900000 0x100>, 1107 <0x30000000 0x4000000>; 1108 reg-names = "qspi_base", "qspi_mmap"; 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 ti,hwmods = "qspi"; 1112 interrupts = <0 138 0x4>; 1113 num-cs = <4>; 1114 status = "disabled"; 1115 }; 1116 1117 hdq: hdq@48347000 { 1118 compatible = "ti,am4372-hdq"; 1119 reg = <0x48347000 0x1000>; 1120 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; 1121 clocks = <&func_12m_clk>; 1122 clock-names = "fck"; 1123 ti,hwmods = "hdq1w"; 1124 status = "disabled"; 1125 }; 1126 1127 dss: dss@4832a000 { 1128 compatible = "ti,omap3-dss"; 1129 reg = <0x4832a000 0x200>; 1130 status = "disabled"; 1131 ti,hwmods = "dss_core"; 1132 clocks = <&disp_clk>; 1133 clock-names = "fck"; 1134 #address-cells = <1>; 1135 #size-cells = <1>; 1136 ranges; 1137 1138 dispc: dispc@4832a400 { 1139 compatible = "ti,omap3-dispc"; 1140 reg = <0x4832a400 0x400>; 1141 interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; 1142 ti,hwmods = "dss_dispc"; 1143 clocks = <&disp_clk>; 1144 clock-names = "fck"; 1145 1146 max-memory-bandwidth = <230000000>; 1147 }; 1148 1149 rfbi: rfbi@4832a800 { 1150 compatible = "ti,omap3-rfbi"; 1151 reg = <0x4832a800 0x100>; 1152 ti,hwmods = "dss_rfbi"; 1153 clocks = <&disp_clk>; 1154 clock-names = "fck"; 1155 status = "disabled"; 1156 }; 1157 }; 1158 1159 ocmcram: ocmcram@40300000 { 1160 compatible = "mmio-sram"; 1161 reg = <0x40300000 0x40000>; /* 256k */ 1162 ranges = <0x0 0x40300000 0x40000>; 1163 #address-cells = <1>; 1164 #size-cells = <1>; 1165 1166 pm_sram_code: pm-sram-code@0 { 1167 compatible = "ti,sram"; 1168 reg = <0x0 0x1000>; 1169 protect-exec; 1170 }; 1171 1172 pm_sram_data: pm-sram-data@1000 { 1173 compatible = "ti,sram"; 1174 reg = <0x1000 0x1000>; 1175 pool; 1176 }; 1177 }; 1178 1179 dcan0: can@481cc000 { 1180 compatible = "ti,am4372-d_can", "ti,am3352-d_can"; 1181 ti,hwmods = "d_can0"; 1182 clocks = <&dcan0_fck>; 1183 clock-names = "fck"; 1184 reg = <0x481cc000 0x2000>; 1185 syscon-raminit = <&scm_conf 0x644 0>; 1186 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1187 status = "disabled"; 1188 }; 1189 1190 dcan1: can@481d0000 { 1191 compatible = "ti,am4372-d_can", "ti,am3352-d_can"; 1192 ti,hwmods = "d_can1"; 1193 clocks = <&dcan1_fck>; 1194 clock-names = "fck"; 1195 reg = <0x481d0000 0x2000>; 1196 syscon-raminit = <&scm_conf 0x644 1>; 1197 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1198 status = "disabled"; 1199 }; 1200 1201 vpfe0: vpfe@48326000 { 1202 compatible = "ti,am437x-vpfe"; 1203 reg = <0x48326000 0x2000>; 1204 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 1205 ti,hwmods = "vpfe0"; 1206 status = "disabled"; 1207 }; 1208 1209 vpfe1: vpfe@48328000 { 1210 compatible = "ti,am437x-vpfe"; 1211 reg = <0x48328000 0x2000>; 1212 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 1213 ti,hwmods = "vpfe1"; 1214 status = "disabled"; 1215 }; 1216 }; 1217}; 1218 1219#include "am43xx-clocks.dtsi" 1220