1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Device Tree file for Marvell Armada 370 Reference Design board 4 * (RD-88F6710-A1) 5 * 6 * Copied from arch/arm/boot/dts/armada-370-db.dts 7 * 8 * Copyright (C) 2013 Florian Fainelli <florian@openwrt.org> 9 * 10 * Note: this Device Tree assumes that the bootloader has remapped the 11 * internal registers to 0xf1000000 (instead of the default 12 * 0xd0000000). The 0xf1000000 is the default used by the recent, 13 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier 14 * boards were delivered with an older version of the bootloader that 15 * left internal registers mapped at 0xd0000000. If you are in this 16 * situation, you should either update your bootloader (preferred 17 * solution) or the below Device Tree should be adjusted. 18 */ 19 20/dts-v1/; 21#include <dt-bindings/input/input.h> 22#include <dt-bindings/interrupt-controller/irq.h> 23#include <dt-bindings/gpio/gpio.h> 24#include "armada-370.dtsi" 25 26/ { 27 model = "Marvell Armada 370 Reference Design"; 28 compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp"; 29 30 chosen { 31 stdout-path = "serial0:115200n8"; 32 }; 33 34 memory@0 { 35 device_type = "memory"; 36 reg = <0x00000000 0x20000000>; /* 512 MB */ 37 }; 38 39 soc { 40 ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000 41 MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000 42 MBUS_ID(0x09, 0x01) 0 0xf1100000 0x10000>; 43 44 internal-regs { 45 serial@12000 { 46 status = "okay"; 47 }; 48 sata@a0000 { 49 nr-ports = <2>; 50 status = "okay"; 51 }; 52 53 ethernet@70000 { 54 status = "okay"; 55 phy = <&phy0>; 56 phy-mode = "sgmii"; 57 }; 58 ethernet@74000 { 59 pinctrl-0 = <&ge1_rgmii_pins>; 60 pinctrl-names = "default"; 61 status = "okay"; 62 phy-mode = "rgmii-id"; 63 fixed-link { 64 speed = <1000>; 65 full-duplex; 66 }; 67 }; 68 69 mvsdio@d4000 { 70 pinctrl-0 = <&sdio_pins1>; 71 pinctrl-names = "default"; 72 status = "okay"; 73 /* No CD or WP GPIOs */ 74 broken-cd; 75 }; 76 77 usb@50000 { 78 status = "okay"; 79 }; 80 81 usb@51000 { 82 status = "okay"; 83 }; 84 85 gpio-keys { 86 compatible = "gpio-keys"; 87 #address-cells = <1>; 88 #size-cells = <0>; 89 button { 90 label = "Software Button"; 91 linux,code = <KEY_POWER>; 92 gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; 93 }; 94 }; 95 96 gpio-fan { 97 compatible = "gpio-fan"; 98 gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>; 99 gpio-fan,speed-map = <0 0 3000 1>; 100 pinctrl-0 = <&fan_pins>; 101 pinctrl-names = "default"; 102 }; 103 104 gpio_leds { 105 compatible = "gpio-leds"; 106 pinctrl-names = "default"; 107 pinctrl-0 = <&led_pins>; 108 109 sw_led { 110 label = "370rd:green:sw"; 111 gpios = <&gpio1 0 GPIO_ACTIVE_LOW>; 112 default-state = "keep"; 113 }; 114 }; 115 }; 116 }; 117 118 dsa { 119 status = "disabled"; 120 121 compatible = "marvell,dsa"; 122 #address-cells = <2>; 123 #size-cells = <0>; 124 125 dsa,ethernet = <ð1>; 126 dsa,mii-bus = <&mdio>; 127 128 switch@0 { 129 #address-cells = <1>; 130 #size-cells = <0>; 131 reg = <0x10 0>; /* MDIO address 16, switch 0 in tree */ 132 133 port@0 { 134 reg = <0>; 135 label = "lan0"; 136 }; 137 138 port@1 { 139 reg = <1>; 140 label = "lan1"; 141 }; 142 143 port@2 { 144 reg = <2>; 145 label = "lan2"; 146 }; 147 148 port@3 { 149 reg = <3>; 150 label = "lan3"; 151 }; 152 153 port@5 { 154 reg = <5>; 155 label = "cpu"; 156 }; 157 }; 158 }; 159}; 160 161&pciec { 162 status = "okay"; 163 164 /* Internal mini-PCIe connector */ 165 pcie@1,0 { 166 /* Port 0, Lane 0 */ 167 status = "okay"; 168 }; 169 170 /* Internal mini-PCIe connector */ 171 pcie@2,0 { 172 /* Port 1, Lane 0 */ 173 status = "okay"; 174 }; 175}; 176 177&mdio { 178 pinctrl-0 = <&mdio_pins>; 179 pinctrl-names = "default"; 180 phy0: ethernet-phy@0 { 181 reg = <0>; 182 }; 183 184 switch: switch@10 { 185 compatible = "marvell,mv88e6085"; 186 #address-cells = <1>; 187 #size-cells = <0>; 188 reg = <0x10>; 189 interrupt-controller; 190 #interrupt-cells = <2>; 191 192 ports { 193 #address-cells = <1>; 194 #size-cells = <0>; 195 196 port@0 { 197 reg = <0>; 198 label = "lan0"; 199 }; 200 201 port@1 { 202 reg = <1>; 203 label = "lan1"; 204 }; 205 206 port@2 { 207 reg = <2>; 208 label = "lan2"; 209 }; 210 211 port@3 { 212 reg = <3>; 213 label = "lan3"; 214 }; 215 216 port@5 { 217 reg = <5>; 218 label = "cpu"; 219 ethernet = <ð1>; 220 fixed-link { 221 speed = <1000>; 222 full-duplex; 223 }; 224 }; 225 }; 226 227 mdio { 228 #address-cells = <1>; 229 #size-cells = <0>; 230 231 switchphy0: switchphy@0 { 232 reg = <0>; 233 interrupt-parent = <&switch>; 234 interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; 235 }; 236 237 switchphy1: switchphy@1 { 238 reg = <1>; 239 interrupt-parent = <&switch>; 240 interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; 241 }; 242 243 switchphy2: switchphy@2 { 244 reg = <2>; 245 interrupt-parent = <&switch>; 246 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; 247 }; 248 249 switchphy3: switchphy@3 { 250 reg = <3>; 251 interrupt-parent = <&switch>; 252 interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; 253 }; 254 }; 255 }; 256}; 257 258 259&pinctrl { 260 fan_pins: fan-pins { 261 marvell,pins = "mpp8"; 262 marvell,function = "gpio"; 263 }; 264 265 led_pins: led-pins { 266 marvell,pins = "mpp32"; 267 marvell,function = "gpio"; 268 }; 269}; 270 271&nand_controller { 272 status = "okay"; 273 274 nand@0 { 275 reg = <0>; 276 label = "pxa3xx_nand-0"; 277 nand-rb = <0>; 278 marvell,nand-keep-config; 279 nand-on-flash-bbt; 280 281 partitions { 282 compatible = "fixed-partitions"; 283 #address-cells = <1>; 284 #size-cells = <1>; 285 286 partition@0 { 287 label = "U-Boot"; 288 reg = <0 0x800000>; 289 }; 290 partition@800000 { 291 label = "Linux"; 292 reg = <0x800000 0x800000>; 293 }; 294 partition@1000000 { 295 label = "Filesystem"; 296 reg = <0x1000000 0x3f000000>; 297 }; 298 }; 299 }; 300}; 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