1/* 2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * Based on "omap4.dtsi" 8 */ 9 10#include <dt-bindings/bus/ti-sysc.h> 11#include <dt-bindings/clock/dra7.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/pinctrl/dra.h> 14#include <dt-bindings/clock/dra7.h> 15 16#define MAX_SOURCES 400 17 18/ { 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 compatible = "ti,dra7xx"; 23 interrupt-parent = <&crossbar_mpu>; 24 chosen { }; 25 26 aliases { 27 i2c0 = &i2c1; 28 i2c1 = &i2c2; 29 i2c2 = &i2c3; 30 i2c3 = &i2c4; 31 i2c4 = &i2c5; 32 serial0 = &uart1; 33 serial1 = &uart2; 34 serial2 = &uart3; 35 serial3 = &uart4; 36 serial4 = &uart5; 37 serial5 = &uart6; 38 serial6 = &uart7; 39 serial7 = &uart8; 40 serial8 = &uart9; 41 serial9 = &uart10; 42 ethernet0 = &cpsw_emac0; 43 ethernet1 = &cpsw_emac1; 44 d_can0 = &dcan1; 45 d_can1 = &dcan2; 46 spi0 = &qspi; 47 }; 48 49 timer { 50 compatible = "arm,armv7-timer"; 51 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 52 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 53 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, 54 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; 55 interrupt-parent = <&gic>; 56 }; 57 58 gic: interrupt-controller@48211000 { 59 compatible = "arm,cortex-a15-gic"; 60 interrupt-controller; 61 #interrupt-cells = <3>; 62 reg = <0x0 0x48211000 0x0 0x1000>, 63 <0x0 0x48212000 0x0 0x2000>, 64 <0x0 0x48214000 0x0 0x2000>, 65 <0x0 0x48216000 0x0 0x2000>; 66 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; 67 interrupt-parent = <&gic>; 68 }; 69 70 wakeupgen: interrupt-controller@48281000 { 71 compatible = "ti,omap5-wugen-mpu", "ti,omap4-wugen-mpu"; 72 interrupt-controller; 73 #interrupt-cells = <3>; 74 reg = <0x0 0x48281000 0x0 0x1000>; 75 interrupt-parent = <&gic>; 76 }; 77 78 cpus { 79 #address-cells = <1>; 80 #size-cells = <0>; 81 82 cpu0: cpu@0 { 83 device_type = "cpu"; 84 compatible = "arm,cortex-a15"; 85 reg = <0>; 86 87 operating-points-v2 = <&cpu0_opp_table>; 88 89 clocks = <&dpll_mpu_ck>; 90 clock-names = "cpu"; 91 92 clock-latency = <300000>; /* From omap-cpufreq driver */ 93 94 /* cooling options */ 95 #cooling-cells = <2>; /* min followed by max */ 96 97 vbb-supply = <&abb_mpu>; 98 }; 99 }; 100 101 cpu0_opp_table: opp-table { 102 compatible = "operating-points-v2-ti-cpu"; 103 syscon = <&scm_wkup>; 104 105 opp_nom-1000000000 { 106 opp-hz = /bits/ 64 <1000000000>; 107 opp-microvolt = <1060000 850000 1150000>, 108 <1060000 850000 1150000>; 109 opp-supported-hw = <0xFF 0x01>; 110 opp-suspend; 111 }; 112 113 opp_od-1176000000 { 114 opp-hz = /bits/ 64 <1176000000>; 115 opp-microvolt = <1160000 885000 1160000>, 116 <1160000 885000 1160000>; 117 118 opp-supported-hw = <0xFF 0x02>; 119 }; 120 121 opp_high@1500000000 { 122 opp-hz = /bits/ 64 <1500000000>; 123 opp-microvolt = <1210000 950000 1250000>, 124 <1210000 950000 1250000>; 125 opp-supported-hw = <0xFF 0x04>; 126 }; 127 }; 128 129 /* 130 * The soc node represents the soc top level view. It is used for IPs 131 * that are not memory mapped in the MPU view or for the MPU itself. 132 */ 133 soc { 134 compatible = "ti,omap-infra"; 135 mpu { 136 compatible = "ti,omap5-mpu"; 137 ti,hwmods = "mpu"; 138 }; 139 }; 140 141 /* 142 * XXX: Use a flat representation of the SOC interconnect. 143 * The real OMAP interconnect network is quite complex. 144 * Since it will not bring real advantage to represent that in DT for 145 * the moment, just use a fake OCP bus entry to represent the whole bus 146 * hierarchy. 147 */ 148 ocp { 149 compatible = "ti,dra7-l3-noc", "simple-bus"; 150 #address-cells = <1>; 151 #size-cells = <1>; 152 ranges = <0x0 0x0 0x0 0xc0000000>; 153 dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>; 154 ti,hwmods = "l3_main_1", "l3_main_2"; 155 reg = <0x0 0x44000000 0x0 0x1000000>, 156 <0x0 0x45000000 0x0 0x1000>; 157 interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 158 <&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 159 160 l4_cfg: l4@4a000000 { 161 compatible = "ti,dra7-l4-cfg", "simple-bus"; 162 #address-cells = <1>; 163 #size-cells = <1>; 164 ranges = <0 0x4a000000 0x22c000>; 165 166 scm: scm@2000 { 167 compatible = "ti,dra7-scm-core", "simple-bus"; 168 reg = <0x2000 0x2000>; 169 #address-cells = <1>; 170 #size-cells = <1>; 171 ranges = <0 0x2000 0x2000>; 172 173 scm_conf: scm_conf@0 { 174 compatible = "syscon", "simple-bus"; 175 reg = <0x0 0x1400>; 176 #address-cells = <1>; 177 #size-cells = <1>; 178 ranges = <0 0x0 0x1400>; 179 180 pbias_regulator: pbias_regulator@e00 { 181 compatible = "ti,pbias-dra7", "ti,pbias-omap"; 182 reg = <0xe00 0x4>; 183 syscon = <&scm_conf>; 184 pbias_mmc_reg: pbias_mmc_omap5 { 185 regulator-name = "pbias_mmc_omap5"; 186 regulator-min-microvolt = <1800000>; 187 regulator-max-microvolt = <3300000>; 188 }; 189 }; 190 191 scm_conf_clocks: clocks { 192 #address-cells = <1>; 193 #size-cells = <0>; 194 }; 195 }; 196 197 dra7_pmx_core: pinmux@1400 { 198 compatible = "ti,dra7-padconf", 199 "pinctrl-single"; 200 reg = <0x1400 0x0468>; 201 #address-cells = <1>; 202 #size-cells = <0>; 203 #pinctrl-cells = <1>; 204 #interrupt-cells = <1>; 205 interrupt-controller; 206 pinctrl-single,register-width = <32>; 207 pinctrl-single,function-mask = <0x3fffffff>; 208 }; 209 210 scm_conf1: scm_conf@1c04 { 211 compatible = "syscon"; 212 reg = <0x1c04 0x0020>; 213 #syscon-cells = <2>; 214 }; 215 216 scm_conf_pcie: scm_conf@1c24 { 217 compatible = "syscon"; 218 reg = <0x1c24 0x0024>; 219 }; 220 221 sdma_xbar: dma-router@b78 { 222 compatible = "ti,dra7-dma-crossbar"; 223 reg = <0xb78 0xfc>; 224 #dma-cells = <1>; 225 dma-requests = <205>; 226 ti,dma-safe-map = <0>; 227 dma-masters = <&sdma>; 228 }; 229 230 edma_xbar: dma-router@c78 { 231 compatible = "ti,dra7-dma-crossbar"; 232 reg = <0xc78 0x7c>; 233 #dma-cells = <2>; 234 dma-requests = <204>; 235 ti,dma-safe-map = <0>; 236 dma-masters = <&edma>; 237 }; 238 }; 239 240 cm_core_aon: cm_core_aon@5000 { 241 compatible = "ti,dra7-cm-core-aon", 242 "simple-bus"; 243 #address-cells = <1>; 244 #size-cells = <1>; 245 reg = <0x5000 0x2000>; 246 ranges = <0 0x5000 0x2000>; 247 248 cm_core_aon_clocks: clocks { 249 #address-cells = <1>; 250 #size-cells = <0>; 251 }; 252 253 cm_core_aon_clockdomains: clockdomains { 254 }; 255 }; 256 257 cm_core: cm_core@8000 { 258 compatible = "ti,dra7-cm-core", "simple-bus"; 259 #address-cells = <1>; 260 #size-cells = <1>; 261 reg = <0x8000 0x3000>; 262 ranges = <0 0x8000 0x3000>; 263 264 cm_core_clocks: clocks { 265 #address-cells = <1>; 266 #size-cells = <0>; 267 }; 268 269 cm_core_clockdomains: clockdomains { 270 }; 271 }; 272 }; 273 274 l4_wkup: l4@4ae00000 { 275 compatible = "ti,dra7-l4-wkup", "simple-bus"; 276 #address-cells = <1>; 277 #size-cells = <1>; 278 ranges = <0 0x4ae00000 0x3f000>; 279 280 counter32k: counter@4000 { 281 compatible = "ti,omap-counter32k"; 282 reg = <0x4000 0x40>; 283 ti,hwmods = "counter_32k"; 284 }; 285 286 prm: prm@6000 { 287 compatible = "ti,dra7-prm", "simple-bus"; 288 reg = <0x6000 0x3000>; 289 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 290 #address-cells = <1>; 291 #size-cells = <1>; 292 ranges = <0 0x6000 0x3000>; 293 294 prm_clocks: clocks { 295 #address-cells = <1>; 296 #size-cells = <0>; 297 }; 298 299 prm_clockdomains: clockdomains { 300 }; 301 }; 302 303 scm_wkup: scm_conf@c000 { 304 compatible = "syscon"; 305 reg = <0xc000 0x1000>; 306 }; 307 }; 308 309 axi@0 { 310 compatible = "simple-bus"; 311 #size-cells = <1>; 312 #address-cells = <1>; 313 ranges = <0x51000000 0x51000000 0x3000 314 0x0 0x20000000 0x10000000>; 315 dma-ranges; 316 /** 317 * To enable PCI endpoint mode, disable the pcie1_rc 318 * node and enable pcie1_ep mode. 319 */ 320 pcie1_rc: pcie@51000000 { 321 reg = <0x51000000 0x2000>, <0x51002000 0x14c>, <0x1000 0x2000>; 322 reg-names = "rc_dbics", "ti_conf", "config"; 323 interrupts = <0 232 0x4>, <0 233 0x4>; 324 #address-cells = <3>; 325 #size-cells = <2>; 326 device_type = "pci"; 327 ranges = <0x81000000 0 0 0x03000 0 0x00010000 328 0x82000000 0 0x20013000 0x13000 0 0xffed000>; 329 bus-range = <0x00 0xff>; 330 #interrupt-cells = <1>; 331 num-lanes = <1>; 332 linux,pci-domain = <0>; 333 ti,hwmods = "pcie1"; 334 phys = <&pcie1_phy>; 335 phy-names = "pcie-phy0"; 336 interrupt-map-mask = <0 0 0 7>; 337 interrupt-map = <0 0 0 1 &pcie1_intc 1>, 338 <0 0 0 2 &pcie1_intc 2>, 339 <0 0 0 3 &pcie1_intc 3>, 340 <0 0 0 4 &pcie1_intc 4>; 341 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; 342 status = "disabled"; 343 pcie1_intc: interrupt-controller { 344 interrupt-controller; 345 #address-cells = <0>; 346 #interrupt-cells = <1>; 347 }; 348 }; 349 350 pcie1_ep: pcie_ep@51000000 { 351 reg = <0x51000000 0x28>, <0x51002000 0x14c>, <0x51001000 0x28>, <0x1000 0x10000000>; 352 reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space"; 353 interrupts = <0 232 0x4>; 354 num-lanes = <1>; 355 num-ib-windows = <4>; 356 num-ob-windows = <16>; 357 ti,hwmods = "pcie1"; 358 phys = <&pcie1_phy>; 359 phy-names = "pcie-phy0"; 360 ti,syscon-unaligned-access = <&scm_conf1 0x14 1>; 361 status = "disabled"; 362 }; 363 }; 364 365 axi@1 { 366 compatible = "simple-bus"; 367 #size-cells = <1>; 368 #address-cells = <1>; 369 ranges = <0x51800000 0x51800000 0x3000 370 0x0 0x30000000 0x10000000>; 371 dma-ranges; 372 status = "disabled"; 373 pcie2_rc: pcie@51800000 { 374 reg = <0x51800000 0x2000>, <0x51802000 0x14c>, <0x1000 0x2000>; 375 reg-names = "rc_dbics", "ti_conf", "config"; 376 interrupts = <0 355 0x4>, <0 356 0x4>; 377 #address-cells = <3>; 378 #size-cells = <2>; 379 device_type = "pci"; 380 ranges = <0x81000000 0 0 0x03000 0 0x00010000 381 0x82000000 0 0x30013000 0x13000 0 0xffed000>; 382 bus-range = <0x00 0xff>; 383 #interrupt-cells = <1>; 384 num-lanes = <1>; 385 linux,pci-domain = <1>; 386 ti,hwmods = "pcie2"; 387 phys = <&pcie2_phy>; 388 phy-names = "pcie-phy0"; 389 interrupt-map-mask = <0 0 0 7>; 390 interrupt-map = <0 0 0 1 &pcie2_intc 1>, 391 <0 0 0 2 &pcie2_intc 2>, 392 <0 0 0 3 &pcie2_intc 3>, 393 <0 0 0 4 &pcie2_intc 4>; 394 ti,syscon-unaligned-access = <&scm_conf1 0x14 2>; 395 pcie2_intc: interrupt-controller { 396 interrupt-controller; 397 #address-cells = <0>; 398 #interrupt-cells = <1>; 399 }; 400 }; 401 }; 402 403 ocmcram1: ocmcram@40300000 { 404 compatible = "mmio-sram"; 405 reg = <0x40300000 0x80000>; 406 ranges = <0x0 0x40300000 0x80000>; 407 #address-cells = <1>; 408 #size-cells = <1>; 409 /* 410 * This is a placeholder for an optional reserved 411 * region for use by secure software. The size 412 * of this region is not known until runtime so it 413 * is set as zero to either be updated to reserve 414 * space or left unchanged to leave all SRAM for use. 415 * On HS parts that that require the reserved region 416 * either the bootloader can update the size to 417 * the required amount or the node can be overridden 418 * from the board dts file for the secure platform. 419 */ 420 sram-hs@0 { 421 compatible = "ti,secure-ram"; 422 reg = <0x0 0x0>; 423 }; 424 }; 425 426 /* 427 * NOTE: ocmcram2 and ocmcram3 are not available on all 428 * DRA7xx and AM57xx variants. Confirm availability in 429 * the data manual for the exact part number in use 430 * before enabling these nodes in the board dts file. 431 */ 432 ocmcram2: ocmcram@40400000 { 433 status = "disabled"; 434 compatible = "mmio-sram"; 435 reg = <0x40400000 0x100000>; 436 ranges = <0x0 0x40400000 0x100000>; 437 #address-cells = <1>; 438 #size-cells = <1>; 439 }; 440 441 ocmcram3: ocmcram@40500000 { 442 status = "disabled"; 443 compatible = "mmio-sram"; 444 reg = <0x40500000 0x100000>; 445 ranges = <0x0 0x40500000 0x100000>; 446 #address-cells = <1>; 447 #size-cells = <1>; 448 }; 449 450 bandgap: bandgap@4a0021e0 { 451 reg = <0x4a0021e0 0xc 452 0x4a00232c 0xc 453 0x4a002380 0x2c 454 0x4a0023C0 0x3c 455 0x4a002564 0x8 456 0x4a002574 0x50>; 457 compatible = "ti,dra752-bandgap"; 458 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; 459 #thermal-sensor-cells = <1>; 460 }; 461 462 dsp1_system: dsp_system@40d00000 { 463 compatible = "syscon"; 464 reg = <0x40d00000 0x100>; 465 }; 466 467 dra7_iodelay_core: padconf@4844a000 { 468 compatible = "ti,dra7-iodelay"; 469 reg = <0x4844a000 0x0d1c>; 470 #address-cells = <1>; 471 #size-cells = <0>; 472 #pinctrl-cells = <2>; 473 }; 474 475 sdma: dma-controller@4a056000 { 476 compatible = "ti,omap4430-sdma"; 477 reg = <0x4a056000 0x1000>; 478 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 479 <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 480 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 481 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 482 #dma-cells = <1>; 483 dma-channels = <32>; 484 dma-requests = <127>; 485 ti,hwmods = "dma_system"; 486 }; 487 488 edma: edma@43300000 { 489 compatible = "ti,edma3-tpcc"; 490 ti,hwmods = "tpcc"; 491 reg = <0x43300000 0x100000>; 492 reg-names = "edma3_cc"; 493 interrupts = <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 494 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 495 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 496 interrupt-names = "edma3_ccint", "edma3_mperr", 497 "edma3_ccerrint"; 498 dma-requests = <64>; 499 #dma-cells = <2>; 500 501 ti,tptcs = <&edma_tptc0 7>, <&edma_tptc1 0>; 502 503 /* 504 * memcpy is disabled, can be enabled with: 505 * ti,edma-memcpy-channels = <20 21>; 506 * for example. Note that these channels need to be 507 * masked in the xbar as well. 508 */ 509 }; 510 511 edma_tptc0: tptc@43400000 { 512 compatible = "ti,edma3-tptc"; 513 ti,hwmods = "tptc0"; 514 reg = <0x43400000 0x100000>; 515 interrupts = <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>; 516 interrupt-names = "edma3_tcerrint"; 517 }; 518 519 edma_tptc1: tptc@43500000 { 520 compatible = "ti,edma3-tptc"; 521 ti,hwmods = "tptc1"; 522 reg = <0x43500000 0x100000>; 523 interrupts = <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>; 524 interrupt-names = "edma3_tcerrint"; 525 }; 526 527 gpio1: gpio@4ae10000 { 528 compatible = "ti,omap4-gpio"; 529 reg = <0x4ae10000 0x200>; 530 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 531 ti,hwmods = "gpio1"; 532 gpio-controller; 533 #gpio-cells = <2>; 534 interrupt-controller; 535 #interrupt-cells = <2>; 536 }; 537 538 gpio2: gpio@48055000 { 539 compatible = "ti,omap4-gpio"; 540 reg = <0x48055000 0x200>; 541 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 542 ti,hwmods = "gpio2"; 543 gpio-controller; 544 #gpio-cells = <2>; 545 interrupt-controller; 546 #interrupt-cells = <2>; 547 }; 548 549 gpio3: gpio@48057000 { 550 compatible = "ti,omap4-gpio"; 551 reg = <0x48057000 0x200>; 552 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 553 ti,hwmods = "gpio3"; 554 gpio-controller; 555 #gpio-cells = <2>; 556 interrupt-controller; 557 #interrupt-cells = <2>; 558 }; 559 560 gpio4: gpio@48059000 { 561 compatible = "ti,omap4-gpio"; 562 reg = <0x48059000 0x200>; 563 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 564 ti,hwmods = "gpio4"; 565 gpio-controller; 566 #gpio-cells = <2>; 567 interrupt-controller; 568 #interrupt-cells = <2>; 569 }; 570 571 gpio5: gpio@4805b000 { 572 compatible = "ti,omap4-gpio"; 573 reg = <0x4805b000 0x200>; 574 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 575 ti,hwmods = "gpio5"; 576 gpio-controller; 577 #gpio-cells = <2>; 578 interrupt-controller; 579 #interrupt-cells = <2>; 580 }; 581 582 gpio6: gpio@4805d000 { 583 compatible = "ti,omap4-gpio"; 584 reg = <0x4805d000 0x200>; 585 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 586 ti,hwmods = "gpio6"; 587 gpio-controller; 588 #gpio-cells = <2>; 589 interrupt-controller; 590 #interrupt-cells = <2>; 591 }; 592 593 gpio7: gpio@48051000 { 594 compatible = "ti,omap4-gpio"; 595 reg = <0x48051000 0x200>; 596 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 597 ti,hwmods = "gpio7"; 598 gpio-controller; 599 #gpio-cells = <2>; 600 interrupt-controller; 601 #interrupt-cells = <2>; 602 }; 603 604 gpio8: gpio@48053000 { 605 compatible = "ti,omap4-gpio"; 606 reg = <0x48053000 0x200>; 607 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; 608 ti,hwmods = "gpio8"; 609 gpio-controller; 610 #gpio-cells = <2>; 611 interrupt-controller; 612 #interrupt-cells = <2>; 613 }; 614 615 uart1: serial@4806a000 { 616 compatible = "ti,dra742-uart", "ti,omap4-uart"; 617 reg = <0x4806a000 0x100>; 618 interrupts-extended = <&crossbar_mpu GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 619 ti,hwmods = "uart1"; 620 clock-frequency = <48000000>; 621 status = "disabled"; 622 dmas = <&sdma_xbar 49>, <&sdma_xbar 50>; 623 dma-names = "tx", "rx"; 624 }; 625 626 uart2: serial@4806c000 { 627 compatible = "ti,dra742-uart", "ti,omap4-uart"; 628 reg = <0x4806c000 0x100>; 629 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 630 ti,hwmods = "uart2"; 631 clock-frequency = <48000000>; 632 status = "disabled"; 633 dmas = <&sdma_xbar 51>, <&sdma_xbar 52>; 634 dma-names = "tx", "rx"; 635 }; 636 637 uart3: serial@48020000 { 638 compatible = "ti,dra742-uart", "ti,omap4-uart"; 639 reg = <0x48020000 0x100>; 640 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 641 ti,hwmods = "uart3"; 642 clock-frequency = <48000000>; 643 status = "disabled"; 644 dmas = <&sdma_xbar 53>, <&sdma_xbar 54>; 645 dma-names = "tx", "rx"; 646 }; 647 648 uart4: serial@4806e000 { 649 compatible = "ti,dra742-uart", "ti,omap4-uart"; 650 reg = <0x4806e000 0x100>; 651 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 652 ti,hwmods = "uart4"; 653 clock-frequency = <48000000>; 654 status = "disabled"; 655 dmas = <&sdma_xbar 55>, <&sdma_xbar 56>; 656 dma-names = "tx", "rx"; 657 }; 658 659 uart5: serial@48066000 { 660 compatible = "ti,dra742-uart", "ti,omap4-uart"; 661 reg = <0x48066000 0x100>; 662 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 663 ti,hwmods = "uart5"; 664 clock-frequency = <48000000>; 665 status = "disabled"; 666 dmas = <&sdma_xbar 63>, <&sdma_xbar 64>; 667 dma-names = "tx", "rx"; 668 }; 669 670 uart6: serial@48068000 { 671 compatible = "ti,dra742-uart", "ti,omap4-uart"; 672 reg = <0x48068000 0x100>; 673 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 674 ti,hwmods = "uart6"; 675 clock-frequency = <48000000>; 676 status = "disabled"; 677 dmas = <&sdma_xbar 79>, <&sdma_xbar 80>; 678 dma-names = "tx", "rx"; 679 }; 680 681 uart7: serial@48420000 { 682 compatible = "ti,dra742-uart", "ti,omap4-uart"; 683 reg = <0x48420000 0x100>; 684 interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>; 685 ti,hwmods = "uart7"; 686 clock-frequency = <48000000>; 687 status = "disabled"; 688 }; 689 690 uart8: serial@48422000 { 691 compatible = "ti,dra742-uart", "ti,omap4-uart"; 692 reg = <0x48422000 0x100>; 693 interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>; 694 ti,hwmods = "uart8"; 695 clock-frequency = <48000000>; 696 status = "disabled"; 697 }; 698 699 uart9: serial@48424000 { 700 compatible = "ti,dra742-uart", "ti,omap4-uart"; 701 reg = <0x48424000 0x100>; 702 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; 703 ti,hwmods = "uart9"; 704 clock-frequency = <48000000>; 705 status = "disabled"; 706 }; 707 708 uart10: serial@4ae2b000 { 709 compatible = "ti,dra742-uart", "ti,omap4-uart"; 710 reg = <0x4ae2b000 0x100>; 711 interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; 712 ti,hwmods = "uart10"; 713 clock-frequency = <48000000>; 714 status = "disabled"; 715 }; 716 717 mailbox1: mailbox@4a0f4000 { 718 compatible = "ti,omap4-mailbox"; 719 reg = <0x4a0f4000 0x200>; 720 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; 723 ti,hwmods = "mailbox1"; 724 #mbox-cells = <1>; 725 ti,mbox-num-users = <3>; 726 ti,mbox-num-fifos = <8>; 727 status = "disabled"; 728 }; 729 730 mailbox2: mailbox@4883a000 { 731 compatible = "ti,omap4-mailbox"; 732 reg = <0x4883a000 0x200>; 733 interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 737 ti,hwmods = "mailbox2"; 738 #mbox-cells = <1>; 739 ti,mbox-num-users = <4>; 740 ti,mbox-num-fifos = <12>; 741 status = "disabled"; 742 }; 743 744 mailbox3: mailbox@4883c000 { 745 compatible = "ti,omap4-mailbox"; 746 reg = <0x4883c000 0x200>; 747 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 751 ti,hwmods = "mailbox3"; 752 #mbox-cells = <1>; 753 ti,mbox-num-users = <4>; 754 ti,mbox-num-fifos = <12>; 755 status = "disabled"; 756 }; 757 758 mailbox4: mailbox@4883e000 { 759 compatible = "ti,omap4-mailbox"; 760 reg = <0x4883e000 0x200>; 761 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 765 ti,hwmods = "mailbox4"; 766 #mbox-cells = <1>; 767 ti,mbox-num-users = <4>; 768 ti,mbox-num-fifos = <12>; 769 status = "disabled"; 770 }; 771 772 mailbox5: mailbox@48840000 { 773 compatible = "ti,omap4-mailbox"; 774 reg = <0x48840000 0x200>; 775 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 776 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 779 ti,hwmods = "mailbox5"; 780 #mbox-cells = <1>; 781 ti,mbox-num-users = <4>; 782 ti,mbox-num-fifos = <12>; 783 status = "disabled"; 784 }; 785 786 mailbox6: mailbox@48842000 { 787 compatible = "ti,omap4-mailbox"; 788 reg = <0x48842000 0x200>; 789 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>; 793 ti,hwmods = "mailbox6"; 794 #mbox-cells = <1>; 795 ti,mbox-num-users = <4>; 796 ti,mbox-num-fifos = <12>; 797 status = "disabled"; 798 }; 799 800 mailbox7: mailbox@48844000 { 801 compatible = "ti,omap4-mailbox"; 802 reg = <0x48844000 0x200>; 803 interrupts = <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 804 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 805 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 806 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>; 807 ti,hwmods = "mailbox7"; 808 #mbox-cells = <1>; 809 ti,mbox-num-users = <4>; 810 ti,mbox-num-fifos = <12>; 811 status = "disabled"; 812 }; 813 814 mailbox8: mailbox@48846000 { 815 compatible = "ti,omap4-mailbox"; 816 reg = <0x48846000 0x200>; 817 interrupts = <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 818 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 819 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 820 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>; 821 ti,hwmods = "mailbox8"; 822 #mbox-cells = <1>; 823 ti,mbox-num-users = <4>; 824 ti,mbox-num-fifos = <12>; 825 status = "disabled"; 826 }; 827 828 mailbox9: mailbox@4885e000 { 829 compatible = "ti,omap4-mailbox"; 830 reg = <0x4885e000 0x200>; 831 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; 835 ti,hwmods = "mailbox9"; 836 #mbox-cells = <1>; 837 ti,mbox-num-users = <4>; 838 ti,mbox-num-fifos = <12>; 839 status = "disabled"; 840 }; 841 842 mailbox10: mailbox@48860000 { 843 compatible = "ti,omap4-mailbox"; 844 reg = <0x48860000 0x200>; 845 interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 848 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 849 ti,hwmods = "mailbox10"; 850 #mbox-cells = <1>; 851 ti,mbox-num-users = <4>; 852 ti,mbox-num-fifos = <12>; 853 status = "disabled"; 854 }; 855 856 mailbox11: mailbox@48862000 { 857 compatible = "ti,omap4-mailbox"; 858 reg = <0x48862000 0x200>; 859 interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 860 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 861 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 862 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>; 863 ti,hwmods = "mailbox11"; 864 #mbox-cells = <1>; 865 ti,mbox-num-users = <4>; 866 ti,mbox-num-fifos = <12>; 867 status = "disabled"; 868 }; 869 870 mailbox12: mailbox@48864000 { 871 compatible = "ti,omap4-mailbox"; 872 reg = <0x48864000 0x200>; 873 interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 874 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 875 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 876 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 877 ti,hwmods = "mailbox12"; 878 #mbox-cells = <1>; 879 ti,mbox-num-users = <4>; 880 ti,mbox-num-fifos = <12>; 881 status = "disabled"; 882 }; 883 884 mailbox13: mailbox@48802000 { 885 compatible = "ti,omap4-mailbox"; 886 reg = <0x48802000 0x200>; 887 interrupts = <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 888 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, 889 <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 890 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>; 891 ti,hwmods = "mailbox13"; 892 #mbox-cells = <1>; 893 ti,mbox-num-users = <4>; 894 ti,mbox-num-fifos = <12>; 895 status = "disabled"; 896 }; 897 898 timer1: timer@4ae18000 { 899 compatible = "ti,omap5430-timer"; 900 reg = <0x4ae18000 0x80>; 901 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 902 ti,hwmods = "timer1"; 903 ti,timer-alwon; 904 clock-names = "fck"; 905 clocks = <&wkupaon_clkctrl DRA7_TIMER1_CLKCTRL 24>; 906 }; 907 908 timer2: timer@48032000 { 909 compatible = "ti,omap5430-timer"; 910 reg = <0x48032000 0x80>; 911 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 912 ti,hwmods = "timer2"; 913 }; 914 915 timer3: timer@48034000 { 916 compatible = "ti,omap5430-timer"; 917 reg = <0x48034000 0x80>; 918 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 919 ti,hwmods = "timer3"; 920 }; 921 922 timer4: timer@48036000 { 923 compatible = "ti,omap5430-timer"; 924 reg = <0x48036000 0x80>; 925 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; 926 ti,hwmods = "timer4"; 927 }; 928 929 timer5: timer@48820000 { 930 compatible = "ti,omap5430-timer"; 931 reg = <0x48820000 0x80>; 932 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 933 ti,hwmods = "timer5"; 934 }; 935 936 timer6: timer@48822000 { 937 compatible = "ti,omap5430-timer"; 938 reg = <0x48822000 0x80>; 939 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 940 ti,hwmods = "timer6"; 941 }; 942 943 timer7: timer@48824000 { 944 compatible = "ti,omap5430-timer"; 945 reg = <0x48824000 0x80>; 946 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 947 ti,hwmods = "timer7"; 948 }; 949 950 timer8: timer@48826000 { 951 compatible = "ti,omap5430-timer"; 952 reg = <0x48826000 0x80>; 953 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 954 ti,hwmods = "timer8"; 955 }; 956 957 timer9: timer@4803e000 { 958 compatible = "ti,omap5430-timer"; 959 reg = <0x4803e000 0x80>; 960 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 961 ti,hwmods = "timer9"; 962 }; 963 964 timer10: timer@48086000 { 965 compatible = "ti,omap5430-timer"; 966 reg = <0x48086000 0x80>; 967 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 968 ti,hwmods = "timer10"; 969 }; 970 971 timer11: timer@48088000 { 972 compatible = "ti,omap5430-timer"; 973 reg = <0x48088000 0x80>; 974 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 975 ti,hwmods = "timer11"; 976 }; 977 978 timer12: timer@4ae20000 { 979 compatible = "ti,omap5430-timer"; 980 reg = <0x4ae20000 0x80>; 981 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 982 ti,hwmods = "timer12"; 983 ti,timer-alwon; 984 ti,timer-secure; 985 }; 986 987 timer13: timer@48828000 { 988 compatible = "ti,omap5430-timer"; 989 reg = <0x48828000 0x80>; 990 interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>; 991 ti,hwmods = "timer13"; 992 }; 993 994 timer14: timer@4882a000 { 995 compatible = "ti,omap5430-timer"; 996 reg = <0x4882a000 0x80>; 997 interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>; 998 ti,hwmods = "timer14"; 999 }; 1000 1001 timer15: timer@4882c000 { 1002 compatible = "ti,omap5430-timer"; 1003 reg = <0x4882c000 0x80>; 1004 interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>; 1005 ti,hwmods = "timer15"; 1006 }; 1007 1008 timer16: timer@4882e000 { 1009 compatible = "ti,omap5430-timer"; 1010 reg = <0x4882e000 0x80>; 1011 interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>; 1012 ti,hwmods = "timer16"; 1013 }; 1014 1015 wdt2: wdt@4ae14000 { 1016 compatible = "ti,omap3-wdt"; 1017 reg = <0x4ae14000 0x80>; 1018 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1019 ti,hwmods = "wd_timer2"; 1020 }; 1021 1022 hwspinlock: spinlock@4a0f6000 { 1023 compatible = "ti,omap4-hwspinlock"; 1024 reg = <0x4a0f6000 0x1000>; 1025 ti,hwmods = "spinlock"; 1026 #hwlock-cells = <1>; 1027 }; 1028 1029 dmm@4e000000 { 1030 compatible = "ti,omap5-dmm"; 1031 reg = <0x4e000000 0x800>; 1032 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; 1033 ti,hwmods = "dmm"; 1034 }; 1035 1036 i2c1: i2c@48070000 { 1037 compatible = "ti,omap4-i2c"; 1038 reg = <0x48070000 0x100>; 1039 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; 1040 #address-cells = <1>; 1041 #size-cells = <0>; 1042 ti,hwmods = "i2c1"; 1043 status = "disabled"; 1044 }; 1045 1046 i2c2: i2c@48072000 { 1047 compatible = "ti,omap4-i2c"; 1048 reg = <0x48072000 0x100>; 1049 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1050 #address-cells = <1>; 1051 #size-cells = <0>; 1052 ti,hwmods = "i2c2"; 1053 status = "disabled"; 1054 }; 1055 1056 i2c3: i2c@48060000 { 1057 compatible = "ti,omap4-i2c"; 1058 reg = <0x48060000 0x100>; 1059 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1060 #address-cells = <1>; 1061 #size-cells = <0>; 1062 ti,hwmods = "i2c3"; 1063 status = "disabled"; 1064 }; 1065 1066 i2c4: i2c@4807a000 { 1067 compatible = "ti,omap4-i2c"; 1068 reg = <0x4807a000 0x100>; 1069 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 1070 #address-cells = <1>; 1071 #size-cells = <0>; 1072 ti,hwmods = "i2c4"; 1073 status = "disabled"; 1074 }; 1075 1076 i2c5: i2c@4807c000 { 1077 compatible = "ti,omap4-i2c"; 1078 reg = <0x4807c000 0x100>; 1079 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1080 #address-cells = <1>; 1081 #size-cells = <0>; 1082 ti,hwmods = "i2c5"; 1083 status = "disabled"; 1084 }; 1085 1086 mmc1: mmc@4809c000 { 1087 compatible = "ti,dra7-sdhci"; 1088 reg = <0x4809c000 0x400>; 1089 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1090 ti,hwmods = "mmc1"; 1091 status = "disabled"; 1092 pbias-supply = <&pbias_mmc_reg>; 1093 max-frequency = <192000000>; 1094 mmc-ddr-1_8v; 1095 mmc-ddr-3_3v; 1096 }; 1097 1098 hdqw1w: 1w@480b2000 { 1099 compatible = "ti,omap3-1w"; 1100 reg = <0x480b2000 0x1000>; 1101 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 1102 ti,hwmods = "hdq1w"; 1103 }; 1104 1105 mmc2: mmc@480b4000 { 1106 compatible = "ti,dra7-sdhci"; 1107 reg = <0x480b4000 0x400>; 1108 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 1109 ti,hwmods = "mmc2"; 1110 status = "disabled"; 1111 max-frequency = <192000000>; 1112 /* SDR104/DDR50/SDR50 bits in CAPA2 is not supported */ 1113 sdhci-caps-mask = <0x7 0x0>; 1114 mmc-hs200-1_8v; 1115 mmc-ddr-1_8v; 1116 mmc-ddr-3_3v; 1117 }; 1118 1119 mmc3: mmc@480ad000 { 1120 compatible = "ti,dra7-sdhci"; 1121 reg = <0x480ad000 0x400>; 1122 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 1123 ti,hwmods = "mmc3"; 1124 status = "disabled"; 1125 /* Errata i887 limits max-frequency of MMC3 to 64 MHz */ 1126 max-frequency = <64000000>; 1127 /* SDMA is not supported */ 1128 sdhci-caps-mask = <0x0 0x400000>; 1129 }; 1130 1131 mmc4: mmc@480d1000 { 1132 compatible = "ti,dra7-sdhci"; 1133 reg = <0x480d1000 0x400>; 1134 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 1135 ti,hwmods = "mmc4"; 1136 status = "disabled"; 1137 max-frequency = <192000000>; 1138 /* SDMA is not supported */ 1139 sdhci-caps-mask = <0x0 0x400000>; 1140 }; 1141 1142 mmu0_dsp1: mmu@40d01000 { 1143 compatible = "ti,dra7-dsp-iommu"; 1144 reg = <0x40d01000 0x100>; 1145 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1146 ti,hwmods = "mmu0_dsp1"; 1147 #iommu-cells = <0>; 1148 ti,syscon-mmuconfig = <&dsp1_system 0x0>; 1149 status = "disabled"; 1150 }; 1151 1152 mmu1_dsp1: mmu@40d02000 { 1153 compatible = "ti,dra7-dsp-iommu"; 1154 reg = <0x40d02000 0x100>; 1155 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 1156 ti,hwmods = "mmu1_dsp1"; 1157 #iommu-cells = <0>; 1158 ti,syscon-mmuconfig = <&dsp1_system 0x1>; 1159 status = "disabled"; 1160 }; 1161 1162 mmu_ipu1: mmu@58882000 { 1163 compatible = "ti,dra7-iommu"; 1164 reg = <0x58882000 0x100>; 1165 interrupts = <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>; 1166 ti,hwmods = "mmu_ipu1"; 1167 #iommu-cells = <0>; 1168 ti,iommu-bus-err-back; 1169 status = "disabled"; 1170 }; 1171 1172 mmu_ipu2: mmu@55082000 { 1173 compatible = "ti,dra7-iommu"; 1174 reg = <0x55082000 0x100>; 1175 interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>; 1176 ti,hwmods = "mmu_ipu2"; 1177 #iommu-cells = <0>; 1178 ti,iommu-bus-err-back; 1179 status = "disabled"; 1180 }; 1181 1182 abb_mpu: regulator-abb-mpu { 1183 compatible = "ti,abb-v3"; 1184 regulator-name = "abb_mpu"; 1185 #address-cells = <0>; 1186 #size-cells = <0>; 1187 clocks = <&sys_clkin1>; 1188 ti,settling-time = <50>; 1189 ti,clock-cycles = <16>; 1190 1191 reg = <0x4ae07ddc 0x4>, <0x4ae07de0 0x4>, 1192 <0x4ae06014 0x4>, <0x4a003b20 0xc>, 1193 <0x4ae0c158 0x4>; 1194 reg-names = "setup-address", "control-address", 1195 "int-address", "efuse-address", 1196 "ldo-address"; 1197 ti,tranxdone-status-mask = <0x80>; 1198 /* LDOVBBMPU_FBB_MUX_CTRL */ 1199 ti,ldovbb-override-mask = <0x400>; 1200 /* LDOVBBMPU_FBB_VSET_OUT */ 1201 ti,ldovbb-vset-mask = <0x1F>; 1202 1203 /* 1204 * NOTE: only FBB mode used but actual vset will 1205 * determine final biasing 1206 */ 1207 ti,abb_info = < 1208 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1209 1060000 0 0x0 0 0x02000000 0x01F00000 1210 1160000 0 0x4 0 0x02000000 0x01F00000 1211 1210000 0 0x8 0 0x02000000 0x01F00000 1212 >; 1213 }; 1214 1215 abb_ivahd: regulator-abb-ivahd { 1216 compatible = "ti,abb-v3"; 1217 regulator-name = "abb_ivahd"; 1218 #address-cells = <0>; 1219 #size-cells = <0>; 1220 clocks = <&sys_clkin1>; 1221 ti,settling-time = <50>; 1222 ti,clock-cycles = <16>; 1223 1224 reg = <0x4ae07e34 0x4>, <0x4ae07e24 0x4>, 1225 <0x4ae06010 0x4>, <0x4a0025cc 0xc>, 1226 <0x4a002470 0x4>; 1227 reg-names = "setup-address", "control-address", 1228 "int-address", "efuse-address", 1229 "ldo-address"; 1230 ti,tranxdone-status-mask = <0x40000000>; 1231 /* LDOVBBIVA_FBB_MUX_CTRL */ 1232 ti,ldovbb-override-mask = <0x400>; 1233 /* LDOVBBIVA_FBB_VSET_OUT */ 1234 ti,ldovbb-vset-mask = <0x1F>; 1235 1236 /* 1237 * NOTE: only FBB mode used but actual vset will 1238 * determine final biasing 1239 */ 1240 ti,abb_info = < 1241 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1242 1055000 0 0x0 0 0x02000000 0x01F00000 1243 1150000 0 0x4 0 0x02000000 0x01F00000 1244 1250000 0 0x8 0 0x02000000 0x01F00000 1245 >; 1246 }; 1247 1248 abb_dspeve: regulator-abb-dspeve { 1249 compatible = "ti,abb-v3"; 1250 regulator-name = "abb_dspeve"; 1251 #address-cells = <0>; 1252 #size-cells = <0>; 1253 clocks = <&sys_clkin1>; 1254 ti,settling-time = <50>; 1255 ti,clock-cycles = <16>; 1256 1257 reg = <0x4ae07e30 0x4>, <0x4ae07e20 0x4>, 1258 <0x4ae06010 0x4>, <0x4a0025e0 0xc>, 1259 <0x4a00246c 0x4>; 1260 reg-names = "setup-address", "control-address", 1261 "int-address", "efuse-address", 1262 "ldo-address"; 1263 ti,tranxdone-status-mask = <0x20000000>; 1264 /* LDOVBBDSPEVE_FBB_MUX_CTRL */ 1265 ti,ldovbb-override-mask = <0x400>; 1266 /* LDOVBBDSPEVE_FBB_VSET_OUT */ 1267 ti,ldovbb-vset-mask = <0x1F>; 1268 1269 /* 1270 * NOTE: only FBB mode used but actual vset will 1271 * determine final biasing 1272 */ 1273 ti,abb_info = < 1274 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1275 1055000 0 0x0 0 0x02000000 0x01F00000 1276 1150000 0 0x4 0 0x02000000 0x01F00000 1277 1250000 0 0x8 0 0x02000000 0x01F00000 1278 >; 1279 }; 1280 1281 abb_gpu: regulator-abb-gpu { 1282 compatible = "ti,abb-v3"; 1283 regulator-name = "abb_gpu"; 1284 #address-cells = <0>; 1285 #size-cells = <0>; 1286 clocks = <&sys_clkin1>; 1287 ti,settling-time = <50>; 1288 ti,clock-cycles = <16>; 1289 1290 reg = <0x4ae07de4 0x4>, <0x4ae07de8 0x4>, 1291 <0x4ae06010 0x4>, <0x4a003b08 0xc>, 1292 <0x4ae0c154 0x4>; 1293 reg-names = "setup-address", "control-address", 1294 "int-address", "efuse-address", 1295 "ldo-address"; 1296 ti,tranxdone-status-mask = <0x10000000>; 1297 /* LDOVBBGPU_FBB_MUX_CTRL */ 1298 ti,ldovbb-override-mask = <0x400>; 1299 /* LDOVBBGPU_FBB_VSET_OUT */ 1300 ti,ldovbb-vset-mask = <0x1F>; 1301 1302 /* 1303 * NOTE: only FBB mode used but actual vset will 1304 * determine final biasing 1305 */ 1306 ti,abb_info = < 1307 /*uV ABB efuse rbb_m fbb_m vset_m*/ 1308 1090000 0 0x0 0 0x02000000 0x01F00000 1309 1210000 0 0x4 0 0x02000000 0x01F00000 1310 1280000 0 0x8 0 0x02000000 0x01F00000 1311 >; 1312 }; 1313 1314 mcspi1: spi@48098000 { 1315 compatible = "ti,omap4-mcspi"; 1316 reg = <0x48098000 0x200>; 1317 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 1318 #address-cells = <1>; 1319 #size-cells = <0>; 1320 ti,hwmods = "mcspi1"; 1321 ti,spi-num-cs = <4>; 1322 dmas = <&sdma_xbar 35>, 1323 <&sdma_xbar 36>, 1324 <&sdma_xbar 37>, 1325 <&sdma_xbar 38>, 1326 <&sdma_xbar 39>, 1327 <&sdma_xbar 40>, 1328 <&sdma_xbar 41>, 1329 <&sdma_xbar 42>; 1330 dma-names = "tx0", "rx0", "tx1", "rx1", 1331 "tx2", "rx2", "tx3", "rx3"; 1332 status = "disabled"; 1333 }; 1334 1335 mcspi2: spi@4809a000 { 1336 compatible = "ti,omap4-mcspi"; 1337 reg = <0x4809a000 0x200>; 1338 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 1339 #address-cells = <1>; 1340 #size-cells = <0>; 1341 ti,hwmods = "mcspi2"; 1342 ti,spi-num-cs = <2>; 1343 dmas = <&sdma_xbar 43>, 1344 <&sdma_xbar 44>, 1345 <&sdma_xbar 45>, 1346 <&sdma_xbar 46>; 1347 dma-names = "tx0", "rx0", "tx1", "rx1"; 1348 status = "disabled"; 1349 }; 1350 1351 mcspi3: spi@480b8000 { 1352 compatible = "ti,omap4-mcspi"; 1353 reg = <0x480b8000 0x200>; 1354 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 1355 #address-cells = <1>; 1356 #size-cells = <0>; 1357 ti,hwmods = "mcspi3"; 1358 ti,spi-num-cs = <2>; 1359 dmas = <&sdma_xbar 15>, <&sdma_xbar 16>; 1360 dma-names = "tx0", "rx0"; 1361 status = "disabled"; 1362 }; 1363 1364 mcspi4: spi@480ba000 { 1365 compatible = "ti,omap4-mcspi"; 1366 reg = <0x480ba000 0x200>; 1367 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 1368 #address-cells = <1>; 1369 #size-cells = <0>; 1370 ti,hwmods = "mcspi4"; 1371 ti,spi-num-cs = <1>; 1372 dmas = <&sdma_xbar 70>, <&sdma_xbar 71>; 1373 dma-names = "tx0", "rx0"; 1374 status = "disabled"; 1375 }; 1376 1377 qspi: spi@4b300000 { 1378 compatible = "ti,dra7xxx-qspi"; 1379 reg = <0x4b300000 0x100>, 1380 <0x5c000000 0x4000000>; 1381 reg-names = "qspi_base", "qspi_mmap"; 1382 syscon-chipselects = <&scm_conf 0x558>; 1383 #address-cells = <1>; 1384 #size-cells = <0>; 1385 ti,hwmods = "qspi"; 1386 clocks = <&l4per_clkctrl DRA7_QSPI_CLKCTRL 25>; 1387 clock-names = "fck"; 1388 num-cs = <4>; 1389 interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>; 1390 status = "disabled"; 1391 }; 1392 1393 /* OCP2SCP3 */ 1394 ocp2scp@4a090000 { 1395 compatible = "ti,omap-ocp2scp"; 1396 #address-cells = <1>; 1397 #size-cells = <1>; 1398 ranges; 1399 reg = <0x4a090000 0x20>; 1400 ti,hwmods = "ocp2scp3"; 1401 sata_phy: phy@4a096000 { 1402 compatible = "ti,phy-pipe3-sata"; 1403 reg = <0x4A096000 0x80>, /* phy_rx */ 1404 <0x4A096400 0x64>, /* phy_tx */ 1405 <0x4A096800 0x40>; /* pll_ctrl */ 1406 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 1407 syscon-phy-power = <&scm_conf 0x374>; 1408 clocks = <&sys_clkin1>, 1409 <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>; 1410 clock-names = "sysclk", "refclk"; 1411 syscon-pllreset = <&scm_conf 0x3fc>; 1412 #phy-cells = <0>; 1413 }; 1414 1415 pcie1_phy: pciephy@4a094000 { 1416 compatible = "ti,phy-pipe3-pcie"; 1417 reg = <0x4a094000 0x80>, /* phy_rx */ 1418 <0x4a094400 0x64>; /* phy_tx */ 1419 reg-names = "phy_rx", "phy_tx"; 1420 syscon-phy-power = <&scm_conf_pcie 0x1c>; 1421 syscon-pcs = <&scm_conf_pcie 0x10>; 1422 clocks = <&dpll_pcie_ref_ck>, 1423 <&dpll_pcie_ref_m2ldo_ck>, 1424 <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 8>, 1425 <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 9>, 1426 <&l3init_clkctrl DRA7_PCIE1_CLKCTRL 10>, 1427 <&optfclk_pciephy_div>, 1428 <&sys_clkin1>; 1429 clock-names = "dpll_ref", "dpll_ref_m2", 1430 "wkupclk", "refclk", 1431 "div-clk", "phy-div", "sysclk"; 1432 #phy-cells = <0>; 1433 }; 1434 1435 pcie2_phy: pciephy@4a095000 { 1436 compatible = "ti,phy-pipe3-pcie"; 1437 reg = <0x4a095000 0x80>, /* phy_rx */ 1438 <0x4a095400 0x64>; /* phy_tx */ 1439 reg-names = "phy_rx", "phy_tx"; 1440 syscon-phy-power = <&scm_conf_pcie 0x20>; 1441 syscon-pcs = <&scm_conf_pcie 0x10>; 1442 clocks = <&dpll_pcie_ref_ck>, 1443 <&dpll_pcie_ref_m2ldo_ck>, 1444 <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 8>, 1445 <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 9>, 1446 <&l3init_clkctrl DRA7_PCIE2_CLKCTRL 10>, 1447 <&optfclk_pciephy_div>, 1448 <&sys_clkin1>; 1449 clock-names = "dpll_ref", "dpll_ref_m2", 1450 "wkupclk", "refclk", 1451 "div-clk", "phy-div", "sysclk"; 1452 #phy-cells = <0>; 1453 status = "disabled"; 1454 }; 1455 }; 1456 1457 sata: sata@4a141100 { 1458 compatible = "snps,dwc-ahci"; 1459 reg = <0x4a140000 0x1100>, <0x4a141100 0x7>; 1460 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; 1461 phys = <&sata_phy>; 1462 phy-names = "sata-phy"; 1463 clocks = <&l3init_clkctrl DRA7_SATA_CLKCTRL 8>; 1464 ti,hwmods = "sata"; 1465 ports-implemented = <0x1>; 1466 }; 1467 1468 rtc: rtc@48838000 { 1469 compatible = "ti,am3352-rtc"; 1470 reg = <0x48838000 0x100>; 1471 interrupts = <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>, 1472 <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; 1473 ti,hwmods = "rtcss"; 1474 clocks = <&sys_32k_ck>; 1475 }; 1476 1477 /* OCP2SCP1 */ 1478 ocp2scp@4a080000 { 1479 compatible = "ti,omap-ocp2scp"; 1480 #address-cells = <1>; 1481 #size-cells = <1>; 1482 ranges; 1483 reg = <0x4a080000 0x20>; 1484 ti,hwmods = "ocp2scp1"; 1485 1486 usb2_phy1: phy@4a084000 { 1487 compatible = "ti,dra7x-usb2", "ti,omap-usb2"; 1488 reg = <0x4a084000 0x400>; 1489 syscon-phy-power = <&scm_conf 0x300>; 1490 clocks = <&usb_phy1_always_on_clk32k>, 1491 <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>; 1492 clock-names = "wkupclk", 1493 "refclk"; 1494 #phy-cells = <0>; 1495 }; 1496 1497 usb2_phy2: phy@4a085000 { 1498 compatible = "ti,dra7x-usb2-phy2", 1499 "ti,omap-usb2"; 1500 reg = <0x4a085000 0x400>; 1501 syscon-phy-power = <&scm_conf 0xe74>; 1502 clocks = <&usb_phy2_always_on_clk32k>, 1503 <&l3init_clkctrl DRA7_USB_OTG_SS2_CLKCTRL 8>; 1504 clock-names = "wkupclk", 1505 "refclk"; 1506 #phy-cells = <0>; 1507 }; 1508 1509 usb3_phy1: phy@4a084400 { 1510 compatible = "ti,omap-usb3"; 1511 reg = <0x4a084400 0x80>, 1512 <0x4a084800 0x64>, 1513 <0x4a084c00 0x40>; 1514 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 1515 syscon-phy-power = <&scm_conf 0x370>; 1516 clocks = <&usb_phy3_always_on_clk32k>, 1517 <&sys_clkin1>, 1518 <&l3init_clkctrl DRA7_USB_OTG_SS1_CLKCTRL 8>; 1519 clock-names = "wkupclk", 1520 "sysclk", 1521 "refclk"; 1522 #phy-cells = <0>; 1523 }; 1524 }; 1525 1526 target-module@4a0dd000 { 1527 compatible = "ti,sysc-omap4-sr", "ti,sysc"; 1528 ti,hwmods = "smartreflex_core"; 1529 reg = <0x4a0dd038 0x4>; 1530 reg-names = "sysc"; 1531 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; 1532 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1533 <SYSC_IDLE_NO>, 1534 <SYSC_IDLE_SMART>, 1535 <SYSC_IDLE_SMART_WKUP>; 1536 clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_CORE_CLKCTRL 0>; 1537 clock-names = "fck"; 1538 #address-cells = <1>; 1539 #size-cells = <1>; 1540 ranges = <0 0x4a0dd000 0x001000>; 1541 1542 /* SmartReflex child device marked reserved in TRM */ 1543 }; 1544 1545 target-module@4a0d9000 { 1546 compatible = "ti,sysc-omap4-sr", "ti,sysc"; 1547 ti,hwmods = "smartreflex_mpu"; 1548 reg = <0x4a0d9038 0x4>; 1549 reg-names = "sysc"; 1550 ti,sysc-mask = <SYSC_OMAP3_SR_ENAWAKEUP>; 1551 ti,sysc-sidle = <SYSC_IDLE_FORCE>, 1552 <SYSC_IDLE_NO>, 1553 <SYSC_IDLE_SMART>, 1554 <SYSC_IDLE_SMART_WKUP>; 1555 clocks = <&coreaon_clkctrl DRA7_SMARTREFLEX_MPU_CLKCTRL 0>; 1556 clock-names = "fck"; 1557 #address-cells = <1>; 1558 #size-cells = <1>; 1559 ranges = <0 0x4a0d9000 0x001000>; 1560 1561 /* SmartReflex child device marked reserved in TRM */ 1562 }; 1563 1564 omap_dwc3_1: omap_dwc3_1@48880000 { 1565 compatible = "ti,dwc3"; 1566 ti,hwmods = "usb_otg_ss1"; 1567 reg = <0x48880000 0x10000>; 1568 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1569 #address-cells = <1>; 1570 #size-cells = <1>; 1571 utmi-mode = <2>; 1572 ranges; 1573 usb1: usb@48890000 { 1574 compatible = "snps,dwc3"; 1575 reg = <0x48890000 0x17000>; 1576 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 1577 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, 1578 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1579 interrupt-names = "peripheral", 1580 "host", 1581 "otg"; 1582 phys = <&usb2_phy1>, <&usb3_phy1>; 1583 phy-names = "usb2-phy", "usb3-phy"; 1584 maximum-speed = "super-speed"; 1585 dr_mode = "otg"; 1586 snps,dis_u3_susphy_quirk; 1587 snps,dis_u2_susphy_quirk; 1588 }; 1589 }; 1590 1591 omap_dwc3_2: omap_dwc3_2@488c0000 { 1592 compatible = "ti,dwc3"; 1593 ti,hwmods = "usb_otg_ss2"; 1594 reg = <0x488c0000 0x10000>; 1595 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1596 #address-cells = <1>; 1597 #size-cells = <1>; 1598 utmi-mode = <2>; 1599 ranges; 1600 usb2: usb@488d0000 { 1601 compatible = "snps,dwc3"; 1602 reg = <0x488d0000 0x17000>; 1603 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 1606 interrupt-names = "peripheral", 1607 "host", 1608 "otg"; 1609 phys = <&usb2_phy2>; 1610 phy-names = "usb2-phy"; 1611 maximum-speed = "high-speed"; 1612 dr_mode = "otg"; 1613 snps,dis_u3_susphy_quirk; 1614 snps,dis_u2_susphy_quirk; 1615 snps,dis_metastability_quirk; 1616 }; 1617 }; 1618 1619 /* IRQ for DWC3_3 and DWC3_4 need IRQ crossbar */ 1620 omap_dwc3_3: omap_dwc3_3@48900000 { 1621 compatible = "ti,dwc3"; 1622 ti,hwmods = "usb_otg_ss3"; 1623 reg = <0x48900000 0x10000>; 1624 interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1625 #address-cells = <1>; 1626 #size-cells = <1>; 1627 utmi-mode = <2>; 1628 ranges; 1629 status = "disabled"; 1630 usb3: usb@48910000 { 1631 compatible = "snps,dwc3"; 1632 reg = <0x48910000 0x17000>; 1633 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1634 <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>, 1635 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>; 1636 interrupt-names = "peripheral", 1637 "host", 1638 "otg"; 1639 maximum-speed = "high-speed"; 1640 dr_mode = "otg"; 1641 snps,dis_u3_susphy_quirk; 1642 snps,dis_u2_susphy_quirk; 1643 }; 1644 }; 1645 1646 elm: elm@48078000 { 1647 compatible = "ti,am3352-elm"; 1648 reg = <0x48078000 0xfc0>; /* device IO registers */ 1649 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; 1650 ti,hwmods = "elm"; 1651 status = "disabled"; 1652 }; 1653 1654 gpmc: gpmc@50000000 { 1655 compatible = "ti,am3352-gpmc"; 1656 ti,hwmods = "gpmc"; 1657 reg = <0x50000000 0x37c>; /* device IO registers */ 1658 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 1659 dmas = <&edma_xbar 4 0>; 1660 dma-names = "rxtx"; 1661 gpmc,num-cs = <8>; 1662 gpmc,num-waitpins = <2>; 1663 #address-cells = <2>; 1664 #size-cells = <1>; 1665 interrupt-controller; 1666 #interrupt-cells = <2>; 1667 gpio-controller; 1668 #gpio-cells = <2>; 1669 status = "disabled"; 1670 }; 1671 1672 atl: atl@4843c000 { 1673 compatible = "ti,dra7-atl"; 1674 reg = <0x4843c000 0x3ff>; 1675 ti,hwmods = "atl"; 1676 ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, 1677 <&atl_clkin2_ck>, <&atl_clkin3_ck>; 1678 clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>; 1679 clock-names = "fck"; 1680 status = "disabled"; 1681 }; 1682 1683 mcasp1: mcasp@48460000 { 1684 compatible = "ti,dra7-mcasp-audio"; 1685 ti,hwmods = "mcasp1"; 1686 reg = <0x48460000 0x2000>, 1687 <0x45800000 0x1000>; 1688 reg-names = "mpu","dat"; 1689 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1690 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 1691 interrupt-names = "tx", "rx"; 1692 dmas = <&edma_xbar 129 1>, <&edma_xbar 128 1>; 1693 dma-names = "tx", "rx"; 1694 clocks = <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 22>, <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 24>, 1695 <&ipu_clkctrl DRA7_MCASP1_CLKCTRL 28>; 1696 clock-names = "fck", "ahclkx", "ahclkr"; 1697 status = "disabled"; 1698 }; 1699 1700 mcasp2: mcasp@48464000 { 1701 compatible = "ti,dra7-mcasp-audio"; 1702 ti,hwmods = "mcasp2"; 1703 reg = <0x48464000 0x2000>, 1704 <0x45c00000 0x1000>; 1705 reg-names = "mpu","dat"; 1706 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 1707 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>; 1708 interrupt-names = "tx", "rx"; 1709 dmas = <&edma_xbar 131 1>, <&edma_xbar 130 1>; 1710 dma-names = "tx", "rx"; 1711 clocks = <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 22>, 1712 <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 24>, 1713 <&l4per_clkctrl DRA7_MCASP2_CLKCTRL 28>; 1714 clock-names = "fck", "ahclkx", "ahclkr"; 1715 status = "disabled"; 1716 }; 1717 1718 mcasp3: mcasp@48468000 { 1719 compatible = "ti,dra7-mcasp-audio"; 1720 ti,hwmods = "mcasp3"; 1721 reg = <0x48468000 0x2000>, 1722 <0x46000000 0x1000>; 1723 reg-names = "mpu","dat"; 1724 interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 1725 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>; 1726 interrupt-names = "tx", "rx"; 1727 dmas = <&edma_xbar 133 1>, <&edma_xbar 132 1>; 1728 dma-names = "tx", "rx"; 1729 clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 22>, 1730 <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>; 1731 clock-names = "fck", "ahclkx"; 1732 status = "disabled"; 1733 }; 1734 1735 mcasp4: mcasp@4846c000 { 1736 compatible = "ti,dra7-mcasp-audio"; 1737 ti,hwmods = "mcasp4"; 1738 reg = <0x4846c000 0x2000>, 1739 <0x48436000 0x1000>; 1740 reg-names = "mpu","dat"; 1741 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 1742 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 1743 interrupt-names = "tx", "rx"; 1744 dmas = <&edma_xbar 135 1>, <&edma_xbar 134 1>; 1745 dma-names = "tx", "rx"; 1746 clocks = <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 22>, 1747 <&l4per_clkctrl DRA7_MCASP4_CLKCTRL 24>; 1748 clock-names = "fck", "ahclkx"; 1749 status = "disabled"; 1750 }; 1751 1752 mcasp5: mcasp@48470000 { 1753 compatible = "ti,dra7-mcasp-audio"; 1754 ti,hwmods = "mcasp5"; 1755 reg = <0x48470000 0x2000>, 1756 <0x4843a000 0x1000>; 1757 reg-names = "mpu","dat"; 1758 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 1759 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; 1760 interrupt-names = "tx", "rx"; 1761 dmas = <&edma_xbar 137 1>, <&edma_xbar 136 1>; 1762 dma-names = "tx", "rx"; 1763 clocks = <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 22>, 1764 <&l4per_clkctrl DRA7_MCASP5_CLKCTRL 24>; 1765 clock-names = "fck", "ahclkx"; 1766 status = "disabled"; 1767 }; 1768 1769 mcasp6: mcasp@48474000 { 1770 compatible = "ti,dra7-mcasp-audio"; 1771 ti,hwmods = "mcasp6"; 1772 reg = <0x48474000 0x2000>, 1773 <0x4844c000 0x1000>; 1774 reg-names = "mpu","dat"; 1775 interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 1776 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; 1777 interrupt-names = "tx", "rx"; 1778 dmas = <&edma_xbar 139 1>, <&edma_xbar 138 1>; 1779 dma-names = "tx", "rx"; 1780 clocks = <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 22>, 1781 <&l4per_clkctrl DRA7_MCASP6_CLKCTRL 24>; 1782 clock-names = "fck", "ahclkx"; 1783 status = "disabled"; 1784 }; 1785 1786 mcasp7: mcasp@48478000 { 1787 compatible = "ti,dra7-mcasp-audio"; 1788 ti,hwmods = "mcasp7"; 1789 reg = <0x48478000 0x2000>, 1790 <0x48450000 0x1000>; 1791 reg-names = "mpu","dat"; 1792 interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 1793 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; 1794 interrupt-names = "tx", "rx"; 1795 dmas = <&edma_xbar 141 1>, <&edma_xbar 140 1>; 1796 dma-names = "tx", "rx"; 1797 clocks = <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 22>, 1798 <&l4per_clkctrl DRA7_MCASP7_CLKCTRL 24>; 1799 clock-names = "fck", "ahclkx"; 1800 status = "disabled"; 1801 }; 1802 1803 mcasp8: mcasp@4847c000 { 1804 compatible = "ti,dra7-mcasp-audio"; 1805 ti,hwmods = "mcasp8"; 1806 reg = <0x4847c000 0x2000>, 1807 <0x48454000 0x1000>; 1808 reg-names = "mpu","dat"; 1809 interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, 1810 <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; 1811 interrupt-names = "tx", "rx"; 1812 dmas = <&edma_xbar 143 1>, <&edma_xbar 142 1>; 1813 dma-names = "tx", "rx"; 1814 clocks = <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 22>, 1815 <&l4per_clkctrl DRA7_MCASP8_CLKCTRL 24>; 1816 clock-names = "fck", "ahclkx"; 1817 status = "disabled"; 1818 }; 1819 1820 crossbar_mpu: crossbar@4a002a48 { 1821 compatible = "ti,irq-crossbar"; 1822 reg = <0x4a002a48 0x130>; 1823 interrupt-controller; 1824 interrupt-parent = <&wakeupgen>; 1825 #interrupt-cells = <3>; 1826 ti,max-irqs = <160>; 1827 ti,max-crossbar-sources = <MAX_SOURCES>; 1828 ti,reg-size = <2>; 1829 ti,irqs-reserved = <0 1 2 3 5 6 131 132>; 1830 ti,irqs-skip = <10 133 139 140>; 1831 ti,irqs-safe-map = <0>; 1832 }; 1833 1834 mac: ethernet@48484000 { 1835 compatible = "ti,dra7-cpsw","ti,cpsw"; 1836 ti,hwmods = "gmac"; 1837 clocks = <&gmac_main_clk>, <&l3init_clkctrl DRA7_GMAC_CLKCTRL 25>; 1838 clock-names = "fck", "cpts"; 1839 cpdma_channels = <8>; 1840 ale_entries = <1024>; 1841 bd_ram_size = <0x2000>; 1842 mac_control = <0x20>; 1843 slaves = <2>; 1844 active_slave = <0>; 1845 cpts_clock_mult = <0x784CFE14>; 1846 cpts_clock_shift = <29>; 1847 reg = <0x48484000 0x1000 1848 0x48485200 0x2E00>; 1849 #address-cells = <1>; 1850 #size-cells = <1>; 1851 1852 /* 1853 * Do not allow gating of cpsw clock as workaround 1854 * for errata i877. Keeping internal clock disabled 1855 * causes the device switching characteristics 1856 * to degrade over time and eventually fail to meet 1857 * the data manual delay time/skew specs. 1858 */ 1859 ti,no-idle; 1860 1861 /* 1862 * rx_thresh_pend 1863 * rx_pend 1864 * tx_pend 1865 * misc_pend 1866 */ 1867 interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1868 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1869 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1870 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>; 1871 ranges; 1872 syscon = <&scm_conf>; 1873 status = "disabled"; 1874 1875 davinci_mdio: mdio@48485000 { 1876 compatible = "ti,cpsw-mdio","ti,davinci_mdio"; 1877 #address-cells = <1>; 1878 #size-cells = <0>; 1879 ti,hwmods = "davinci_mdio"; 1880 bus_freq = <1000000>; 1881 reg = <0x48485000 0x100>; 1882 }; 1883 1884 cpsw_emac0: slave@48480200 { 1885 /* Filled in by U-Boot */ 1886 mac-address = [ 00 00 00 00 00 00 ]; 1887 }; 1888 1889 cpsw_emac1: slave@48480300 { 1890 /* Filled in by U-Boot */ 1891 mac-address = [ 00 00 00 00 00 00 ]; 1892 }; 1893 1894 phy_sel: cpsw-phy-sel@4a002554 { 1895 compatible = "ti,dra7xx-cpsw-phy-sel"; 1896 reg= <0x4a002554 0x4>; 1897 reg-names = "gmii-sel"; 1898 }; 1899 }; 1900 1901 dcan1: can@4ae3c000 { 1902 compatible = "ti,dra7-d_can"; 1903 ti,hwmods = "dcan1"; 1904 reg = <0x4ae3c000 0x2000>; 1905 syscon-raminit = <&scm_conf 0x558 0>; 1906 interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; 1907 clocks = <&wkupaon_clkctrl DRA7_DCAN1_CLKCTRL 24>; 1908 status = "disabled"; 1909 }; 1910 1911 dcan2: can@48480000 { 1912 compatible = "ti,dra7-d_can"; 1913 ti,hwmods = "dcan2"; 1914 reg = <0x48480000 0x2000>; 1915 syscon-raminit = <&scm_conf 0x558 1>; 1916 interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; 1917 clocks = <&sys_clkin1>; 1918 status = "disabled"; 1919 }; 1920 1921 dss: dss@58000000 { 1922 compatible = "ti,dra7-dss"; 1923 /* 'reg' defined in dra72x.dtsi and dra74x.dtsi */ 1924 /* 'clocks' defined in dra72x.dtsi and dra74x.dtsi */ 1925 status = "disabled"; 1926 ti,hwmods = "dss_core"; 1927 /* CTRL_CORE_DSS_PLL_CONTROL */ 1928 syscon-pll-ctrl = <&scm_conf 0x538>; 1929 #address-cells = <1>; 1930 #size-cells = <1>; 1931 ranges; 1932 1933 dispc@58001000 { 1934 compatible = "ti,dra7-dispc"; 1935 reg = <0x58001000 0x1000>; 1936 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1937 ti,hwmods = "dss_dispc"; 1938 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 8>; 1939 clock-names = "fck"; 1940 /* CTRL_CORE_SMA_SW_1 */ 1941 syscon-pol = <&scm_conf 0x534>; 1942 }; 1943 1944 hdmi: encoder@58060000 { 1945 compatible = "ti,dra7-hdmi"; 1946 reg = <0x58040000 0x200>, 1947 <0x58040200 0x80>, 1948 <0x58040300 0x80>, 1949 <0x58060000 0x19000>; 1950 reg-names = "wp", "pll", "phy", "core"; 1951 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 1952 status = "disabled"; 1953 ti,hwmods = "dss_hdmi"; 1954 clocks = <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 9>, 1955 <&dss_clkctrl DRA7_DSS_CORE_CLKCTRL 10>; 1956 clock-names = "fck", "sys_clk"; 1957 dmas = <&sdma_xbar 76>; 1958 dma-names = "audio_tx"; 1959 }; 1960 }; 1961 1962 epwmss0: epwmss@4843e000 { 1963 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 1964 reg = <0x4843e000 0x30>; 1965 ti,hwmods = "epwmss0"; 1966 #address-cells = <1>; 1967 #size-cells = <1>; 1968 status = "disabled"; 1969 ranges; 1970 1971 ehrpwm0: pwm@4843e200 { 1972 compatible = "ti,dra746-ehrpwm", 1973 "ti,am3352-ehrpwm"; 1974 #pwm-cells = <3>; 1975 reg = <0x4843e200 0x80>; 1976 clocks = <&ehrpwm0_tbclk>, <&l4_root_clk_div>; 1977 clock-names = "tbclk", "fck"; 1978 status = "disabled"; 1979 }; 1980 1981 ecap0: ecap@4843e100 { 1982 compatible = "ti,dra746-ecap", 1983 "ti,am3352-ecap"; 1984 #pwm-cells = <3>; 1985 reg = <0x4843e100 0x80>; 1986 clocks = <&l4_root_clk_div>; 1987 clock-names = "fck"; 1988 status = "disabled"; 1989 }; 1990 }; 1991 1992 epwmss1: epwmss@48440000 { 1993 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 1994 reg = <0x48440000 0x30>; 1995 ti,hwmods = "epwmss1"; 1996 #address-cells = <1>; 1997 #size-cells = <1>; 1998 status = "disabled"; 1999 ranges; 2000 2001 ehrpwm1: pwm@48440200 { 2002 compatible = "ti,dra746-ehrpwm", 2003 "ti,am3352-ehrpwm"; 2004 #pwm-cells = <3>; 2005 reg = <0x48440200 0x80>; 2006 clocks = <&ehrpwm1_tbclk>, <&l4_root_clk_div>; 2007 clock-names = "tbclk", "fck"; 2008 status = "disabled"; 2009 }; 2010 2011 ecap1: ecap@48440100 { 2012 compatible = "ti,dra746-ecap", 2013 "ti,am3352-ecap"; 2014 #pwm-cells = <3>; 2015 reg = <0x48440100 0x80>; 2016 clocks = <&l4_root_clk_div>; 2017 clock-names = "fck"; 2018 status = "disabled"; 2019 }; 2020 }; 2021 2022 epwmss2: epwmss@48442000 { 2023 compatible = "ti,dra746-pwmss", "ti,am33xx-pwmss"; 2024 reg = <0x48442000 0x30>; 2025 ti,hwmods = "epwmss2"; 2026 #address-cells = <1>; 2027 #size-cells = <1>; 2028 status = "disabled"; 2029 ranges; 2030 2031 ehrpwm2: pwm@48442200 { 2032 compatible = "ti,dra746-ehrpwm", 2033 "ti,am3352-ehrpwm"; 2034 #pwm-cells = <3>; 2035 reg = <0x48442200 0x80>; 2036 clocks = <&ehrpwm2_tbclk>, <&l4_root_clk_div>; 2037 clock-names = "tbclk", "fck"; 2038 status = "disabled"; 2039 }; 2040 2041 ecap2: ecap@48442100 { 2042 compatible = "ti,dra746-ecap", 2043 "ti,am3352-ecap"; 2044 #pwm-cells = <3>; 2045 reg = <0x48442100 0x80>; 2046 clocks = <&l4_root_clk_div>; 2047 clock-names = "fck"; 2048 status = "disabled"; 2049 }; 2050 }; 2051 2052 aes1: aes@4b500000 { 2053 compatible = "ti,omap4-aes"; 2054 ti,hwmods = "aes1"; 2055 reg = <0x4b500000 0xa0>; 2056 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 2057 dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>; 2058 dma-names = "tx", "rx"; 2059 clocks = <&l3_iclk_div>; 2060 clock-names = "fck"; 2061 }; 2062 2063 aes2: aes@4b700000 { 2064 compatible = "ti,omap4-aes"; 2065 ti,hwmods = "aes2"; 2066 reg = <0x4b700000 0xa0>; 2067 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 2068 dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>; 2069 dma-names = "tx", "rx"; 2070 clocks = <&l3_iclk_div>; 2071 clock-names = "fck"; 2072 }; 2073 2074 des: des@480a5000 { 2075 compatible = "ti,omap4-des"; 2076 ti,hwmods = "des"; 2077 reg = <0x480a5000 0xa0>; 2078 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 2079 dmas = <&sdma_xbar 117>, <&sdma_xbar 116>; 2080 dma-names = "tx", "rx"; 2081 clocks = <&l3_iclk_div>; 2082 clock-names = "fck"; 2083 }; 2084 2085 sham: sham@53100000 { 2086 compatible = "ti,omap5-sham"; 2087 ti,hwmods = "sham"; 2088 reg = <0x4b101000 0x300>; 2089 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 2090 dmas = <&edma_xbar 119 0>; 2091 dma-names = "rx"; 2092 clocks = <&l3_iclk_div>; 2093 clock-names = "fck"; 2094 }; 2095 2096 rng: rng@48090000 { 2097 compatible = "ti,omap4-rng"; 2098 ti,hwmods = "rng"; 2099 reg = <0x48090000 0x2000>; 2100 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 2101 clocks = <&l3_iclk_div>; 2102 clock-names = "fck"; 2103 }; 2104 2105 opp_supply_mpu: opp-supply@4a003b20 { 2106 compatible = "ti,omap5-opp-supply"; 2107 reg = <0x4a003b20 0xc>; 2108 ti,efuse-settings = < 2109 /* uV offset */ 2110 1060000 0x0 2111 1160000 0x4 2112 1210000 0x8 2113 >; 2114 ti,absolute-max-voltage-uv = <1500000>; 2115 }; 2116 2117 }; 2118 2119 thermal_zones: thermal-zones { 2120 #include "omap4-cpu-thermal.dtsi" 2121 #include "omap5-gpu-thermal.dtsi" 2122 #include "omap5-core-thermal.dtsi" 2123 #include "dra7-dspeve-thermal.dtsi" 2124 #include "dra7-iva-thermal.dtsi" 2125 }; 2126 2127}; 2128 2129&cpu_thermal { 2130 polling-delay = <500>; /* milliseconds */ 2131 coefficients = <0 2000>; 2132}; 2133 2134&gpu_thermal { 2135 coefficients = <0 2000>; 2136}; 2137 2138&core_thermal { 2139 coefficients = <0 2000>; 2140}; 2141 2142&dspeve_thermal { 2143 coefficients = <0 2000>; 2144}; 2145 2146&iva_thermal { 2147 coefficients = <0 2000>; 2148}; 2149 2150&cpu_crit { 2151 temperature = <120000>; /* milli Celsius */ 2152}; 2153 2154#include "dra7xx-clocks.dtsi" 2155 2156&core_crit { 2157 temperature = <120000>; /* milli Celsius */ 2158}; 2159 2160&gpu_crit { 2161 temperature = <120000>; /* milli Celsius */ 2162}; 2163 2164&dspeve_crit { 2165 temperature = <120000>; /* milli Celsius */ 2166}; 2167 2168&iva_crit { 2169 temperature = <120000>; /* milli Celsius */ 2170}; 2171