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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Hardkernel Odroid XU3 audio subsystem device tree source
4 *
5 * Copyright (c) 2015 Krzysztof Kozlowski
6 * Copyright (c) 2014 Collabora Ltd.
7 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
8 *		http://www.samsung.com
9 */
10
11#include <dt-bindings/sound/samsung-i2s.h>
12
13/ {
14	sound: sound {
15		compatible = "samsung,odroid-xu3-audio";
16		model = "Odroid-XU3";
17
18		samsung,audio-widgets =
19			"Headphone", "Headphone Jack",
20			"Speakers", "Speakers";
21		samsung,audio-routing =
22			"Headphone Jack", "HPL",
23			"Headphone Jack", "HPR",
24			"Headphone Jack", "MICBIAS",
25			"IN12", "Headphone Jack",
26			"Speakers", "SPKL",
27			"Speakers", "SPKR";
28
29		assigned-clocks = <&clock CLK_MOUT_EPLL>,
30				<&clock CLK_MOUT_MAU_EPLL>,
31				<&clock CLK_MOUT_USER_MAU_EPLL>,
32				<&clock_audss EXYNOS_MOUT_AUDSS>,
33				<&clock_audss EXYNOS_MOUT_I2S>,
34				<&clock_audss EXYNOS_DOUT_SRP>,
35				<&clock_audss EXYNOS_DOUT_AUD_BUS>,
36				<&clock_audss EXYNOS_DOUT_I2S>;
37
38		assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
39				<&clock CLK_MOUT_EPLL>,
40				<&clock CLK_MOUT_MAU_EPLL>,
41				<&clock CLK_MAU_EPLL>,
42				<&clock_audss EXYNOS_MOUT_AUDSS>;
43
44		assigned-clock-rates = <0>,
45				<0>,
46				<0>,
47				<0>,
48				<0>,
49				<196608001>,
50				<(196608002 / 2)>,
51				<196608000>;
52
53		cpu {
54			sound-dai = <&i2s0 0>;
55		};
56		codec {
57			sound-dai = <&hdmi>, <&max98090>;
58		};
59	};
60};
61
62&clock_audss {
63	assigned-clocks = <&clock_audss EXYNOS_DOUT_SRP>,
64			  <&clock CLK_FOUT_EPLL>;
65	assigned-clock-rates = <(196608000 / 256)>,
66			       <196608000>;
67};
68
69&hsi2c_5 {
70	status = "okay";
71	max98090: max98090@10 {
72		compatible = "maxim,max98090";
73		reg = <0x10>;
74		interrupt-parent = <&gpx3>;
75		interrupts = <2 IRQ_TYPE_NONE>;
76		clocks = <&i2s0 CLK_I2S_CDCLK>;
77		clock-names = "mclk";
78		#sound-dai-cells = <0>;
79	};
80};
81
82&i2s0 {
83	status = "okay";
84	assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
85	assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
86};
87