1// SPDX-License-Identifier: GPL-2.0+ 2// 3// Copyright 2011 Freescale Semiconductor, Inc. 4// Copyright 2011 Linaro Ltd. 5 6#include "imx51-pinfunc.h" 7#include <dt-bindings/clock/imx5-clock.h> 8#include <dt-bindings/gpio/gpio.h> 9#include <dt-bindings/input/input.h> 10#include <dt-bindings/interrupt-controller/irq.h> 11 12/ { 13 #address-cells = <1>; 14 #size-cells = <1>; 15 /* 16 * The decompressor and also some bootloaders rely on a 17 * pre-existing /chosen node to be available to insert the 18 * command line and merge other ATAGS info. 19 */ 20 chosen {}; 21 22 aliases { 23 ethernet0 = &fec; 24 gpio0 = &gpio1; 25 gpio1 = &gpio2; 26 gpio2 = &gpio3; 27 gpio3 = &gpio4; 28 i2c0 = &i2c1; 29 i2c1 = &i2c2; 30 mmc0 = &esdhc1; 31 mmc1 = &esdhc2; 32 mmc2 = &esdhc3; 33 mmc3 = &esdhc4; 34 serial0 = &uart1; 35 serial1 = &uart2; 36 serial2 = &uart3; 37 spi0 = &ecspi1; 38 spi1 = &ecspi2; 39 spi2 = &cspi; 40 }; 41 42 tzic: tz-interrupt-controller@e0000000 { 43 compatible = "fsl,imx51-tzic", "fsl,tzic"; 44 interrupt-controller; 45 #interrupt-cells = <1>; 46 reg = <0xe0000000 0x4000>; 47 }; 48 49 clocks { 50 ckil { 51 compatible = "fsl,imx-ckil", "fixed-clock"; 52 #clock-cells = <0>; 53 clock-frequency = <32768>; 54 }; 55 56 ckih1 { 57 compatible = "fsl,imx-ckih1", "fixed-clock"; 58 #clock-cells = <0>; 59 clock-frequency = <0>; 60 }; 61 62 ckih2 { 63 compatible = "fsl,imx-ckih2", "fixed-clock"; 64 #clock-cells = <0>; 65 clock-frequency = <0>; 66 }; 67 68 osc { 69 compatible = "fsl,imx-osc", "fixed-clock"; 70 #clock-cells = <0>; 71 clock-frequency = <24000000>; 72 }; 73 }; 74 75 cpus { 76 #address-cells = <1>; 77 #size-cells = <0>; 78 cpu: cpu@0 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a8"; 81 reg = <0>; 82 clock-latency = <62500>; 83 clocks = <&clks IMX5_CLK_CPU_PODF>; 84 clock-names = "cpu"; 85 operating-points = < 86 166000 1000000 87 600000 1050000 88 800000 1100000 89 >; 90 voltage-tolerance = <5>; 91 }; 92 }; 93 94 pmu: pmu { 95 compatible = "arm,cortex-a8-pmu"; 96 interrupt-parent = <&tzic>; 97 interrupts = <77>; 98 }; 99 100 usbphy0: usbphy0 { 101 compatible = "usb-nop-xceiv"; 102 clocks = <&clks IMX5_CLK_USB_PHY_GATE>; 103 clock-names = "main_clk"; 104 #phy-cells = <0>; 105 }; 106 107 display-subsystem { 108 compatible = "fsl,imx-display-subsystem"; 109 ports = <&ipu_di0>, <&ipu_di1>; 110 }; 111 112 soc { 113 #address-cells = <1>; 114 #size-cells = <1>; 115 compatible = "simple-bus"; 116 interrupt-parent = <&tzic>; 117 ranges; 118 119 iram: iram@1ffe0000 { 120 compatible = "mmio-sram"; 121 reg = <0x1ffe0000 0x20000>; 122 }; 123 124 ipu: ipu@40000000 { 125 #address-cells = <1>; 126 #size-cells = <0>; 127 compatible = "fsl,imx51-ipu"; 128 reg = <0x40000000 0x20000000>; 129 interrupts = <11 10>; 130 clocks = <&clks IMX5_CLK_IPU_GATE>, 131 <&clks IMX5_CLK_IPU_DI0_GATE>, 132 <&clks IMX5_CLK_IPU_DI1_GATE>; 133 clock-names = "bus", "di0", "di1"; 134 resets = <&src 2>; 135 136 ipu_di0: port@2 { 137 reg = <2>; 138 139 ipu_di0_disp1: endpoint { 140 }; 141 }; 142 143 ipu_di1: port@3 { 144 reg = <3>; 145 146 ipu_di1_disp2: endpoint { 147 }; 148 }; 149 }; 150 151 aips@70000000 { /* AIPS1 */ 152 compatible = "fsl,aips-bus", "simple-bus"; 153 #address-cells = <1>; 154 #size-cells = <1>; 155 reg = <0x70000000 0x10000000>; 156 ranges; 157 158 spba@70000000 { 159 compatible = "fsl,spba-bus", "simple-bus"; 160 #address-cells = <1>; 161 #size-cells = <1>; 162 reg = <0x70000000 0x40000>; 163 ranges; 164 165 esdhc1: esdhc@70004000 { 166 compatible = "fsl,imx51-esdhc"; 167 reg = <0x70004000 0x4000>; 168 interrupts = <1>; 169 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, 170 <&clks IMX5_CLK_DUMMY>, 171 <&clks IMX5_CLK_ESDHC1_PER_GATE>; 172 clock-names = "ipg", "ahb", "per"; 173 status = "disabled"; 174 }; 175 176 esdhc2: esdhc@70008000 { 177 compatible = "fsl,imx51-esdhc"; 178 reg = <0x70008000 0x4000>; 179 interrupts = <2>; 180 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, 181 <&clks IMX5_CLK_DUMMY>, 182 <&clks IMX5_CLK_ESDHC2_PER_GATE>; 183 clock-names = "ipg", "ahb", "per"; 184 bus-width = <4>; 185 status = "disabled"; 186 }; 187 188 uart3: serial@7000c000 { 189 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 190 reg = <0x7000c000 0x4000>; 191 interrupts = <33>; 192 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, 193 <&clks IMX5_CLK_UART3_PER_GATE>; 194 clock-names = "ipg", "per"; 195 status = "disabled"; 196 }; 197 198 ecspi1: ecspi@70010000 { 199 #address-cells = <1>; 200 #size-cells = <0>; 201 compatible = "fsl,imx51-ecspi"; 202 reg = <0x70010000 0x4000>; 203 interrupts = <36>; 204 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, 205 <&clks IMX5_CLK_ECSPI1_PER_GATE>; 206 clock-names = "ipg", "per"; 207 status = "disabled"; 208 }; 209 210 ssi2: ssi@70014000 { 211 #sound-dai-cells = <0>; 212 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 213 reg = <0x70014000 0x4000>; 214 interrupts = <30>; 215 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, 216 <&clks IMX5_CLK_SSI2_ROOT_GATE>; 217 clock-names = "ipg", "baud"; 218 dmas = <&sdma 24 1 0>, 219 <&sdma 25 1 0>; 220 dma-names = "rx", "tx"; 221 fsl,fifo-depth = <15>; 222 status = "disabled"; 223 }; 224 225 esdhc3: esdhc@70020000 { 226 compatible = "fsl,imx51-esdhc"; 227 reg = <0x70020000 0x4000>; 228 interrupts = <3>; 229 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, 230 <&clks IMX5_CLK_DUMMY>, 231 <&clks IMX5_CLK_ESDHC3_PER_GATE>; 232 clock-names = "ipg", "ahb", "per"; 233 bus-width = <4>; 234 status = "disabled"; 235 }; 236 237 esdhc4: esdhc@70024000 { 238 compatible = "fsl,imx51-esdhc"; 239 reg = <0x70024000 0x4000>; 240 interrupts = <4>; 241 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, 242 <&clks IMX5_CLK_DUMMY>, 243 <&clks IMX5_CLK_ESDHC4_PER_GATE>; 244 clock-names = "ipg", "ahb", "per"; 245 bus-width = <4>; 246 status = "disabled"; 247 }; 248 }; 249 250 aipstz1: bridge@73f00000 { 251 compatible = "fsl,imx51-aipstz"; 252 reg = <0x73f00000 0x60>; 253 }; 254 255 usbotg: usb@73f80000 { 256 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 257 reg = <0x73f80000 0x0200>; 258 interrupts = <18>; 259 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 260 fsl,usbmisc = <&usbmisc 0>; 261 fsl,usbphy = <&usbphy0>; 262 status = "disabled"; 263 }; 264 265 usbh1: usb@73f80200 { 266 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 267 reg = <0x73f80200 0x0200>; 268 interrupts = <14>; 269 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 270 fsl,usbmisc = <&usbmisc 1>; 271 dr_mode = "host"; 272 status = "disabled"; 273 }; 274 275 usbh2: usb@73f80400 { 276 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 277 reg = <0x73f80400 0x0200>; 278 interrupts = <16>; 279 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 280 fsl,usbmisc = <&usbmisc 2>; 281 dr_mode = "host"; 282 status = "disabled"; 283 }; 284 285 usbh3: usb@73f80600 { 286 compatible = "fsl,imx51-usb", "fsl,imx27-usb"; 287 reg = <0x73f80600 0x0200>; 288 interrupts = <17>; 289 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 290 fsl,usbmisc = <&usbmisc 3>; 291 dr_mode = "host"; 292 status = "disabled"; 293 }; 294 295 usbmisc: usbmisc@73f80800 { 296 #index-cells = <1>; 297 compatible = "fsl,imx51-usbmisc"; 298 reg = <0x73f80800 0x200>; 299 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 300 }; 301 302 gpio1: gpio@73f84000 { 303 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; 304 reg = <0x73f84000 0x4000>; 305 interrupts = <50 51>; 306 gpio-controller; 307 #gpio-cells = <2>; 308 interrupt-controller; 309 #interrupt-cells = <2>; 310 }; 311 312 gpio2: gpio@73f88000 { 313 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; 314 reg = <0x73f88000 0x4000>; 315 interrupts = <52 53>; 316 gpio-controller; 317 #gpio-cells = <2>; 318 interrupt-controller; 319 #interrupt-cells = <2>; 320 }; 321 322 gpio3: gpio@73f8c000 { 323 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; 324 reg = <0x73f8c000 0x4000>; 325 interrupts = <54 55>; 326 gpio-controller; 327 #gpio-cells = <2>; 328 interrupt-controller; 329 #interrupt-cells = <2>; 330 }; 331 332 gpio4: gpio@73f90000 { 333 compatible = "fsl,imx51-gpio", "fsl,imx35-gpio"; 334 reg = <0x73f90000 0x4000>; 335 interrupts = <56 57>; 336 gpio-controller; 337 #gpio-cells = <2>; 338 interrupt-controller; 339 #interrupt-cells = <2>; 340 }; 341 342 kpp: kpp@73f94000 { 343 compatible = "fsl,imx51-kpp", "fsl,imx21-kpp"; 344 reg = <0x73f94000 0x4000>; 345 interrupts = <60>; 346 clocks = <&clks IMX5_CLK_DUMMY>; 347 status = "disabled"; 348 }; 349 350 wdog1: wdog@73f98000 { 351 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 352 reg = <0x73f98000 0x4000>; 353 interrupts = <58>; 354 clocks = <&clks IMX5_CLK_DUMMY>; 355 }; 356 357 wdog2: wdog@73f9c000 { 358 compatible = "fsl,imx51-wdt", "fsl,imx21-wdt"; 359 reg = <0x73f9c000 0x4000>; 360 interrupts = <59>; 361 clocks = <&clks IMX5_CLK_DUMMY>; 362 status = "disabled"; 363 }; 364 365 gpt: timer@73fa0000 { 366 compatible = "fsl,imx51-gpt", "fsl,imx31-gpt"; 367 reg = <0x73fa0000 0x4000>; 368 interrupts = <39>; 369 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, 370 <&clks IMX5_CLK_GPT_HF_GATE>; 371 clock-names = "ipg", "per"; 372 }; 373 374 iomuxc: iomuxc@73fa8000 { 375 compatible = "fsl,imx51-iomuxc"; 376 reg = <0x73fa8000 0x4000>; 377 }; 378 379 pwm1: pwm@73fb4000 { 380 #pwm-cells = <2>; 381 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; 382 reg = <0x73fb4000 0x4000>; 383 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, 384 <&clks IMX5_CLK_PWM1_HF_GATE>; 385 clock-names = "ipg", "per"; 386 interrupts = <61>; 387 }; 388 389 pwm2: pwm@73fb8000 { 390 #pwm-cells = <2>; 391 compatible = "fsl,imx51-pwm", "fsl,imx27-pwm"; 392 reg = <0x73fb8000 0x4000>; 393 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, 394 <&clks IMX5_CLK_PWM2_HF_GATE>; 395 clock-names = "ipg", "per"; 396 interrupts = <94>; 397 }; 398 399 uart1: serial@73fbc000 { 400 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 401 reg = <0x73fbc000 0x4000>; 402 interrupts = <31>; 403 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, 404 <&clks IMX5_CLK_UART1_PER_GATE>; 405 clock-names = "ipg", "per"; 406 status = "disabled"; 407 }; 408 409 uart2: serial@73fc0000 { 410 compatible = "fsl,imx51-uart", "fsl,imx21-uart"; 411 reg = <0x73fc0000 0x4000>; 412 interrupts = <32>; 413 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, 414 <&clks IMX5_CLK_UART2_PER_GATE>; 415 clock-names = "ipg", "per"; 416 status = "disabled"; 417 }; 418 419 src: src@73fd0000 { 420 compatible = "fsl,imx51-src"; 421 reg = <0x73fd0000 0x4000>; 422 #reset-cells = <1>; 423 }; 424 425 clks: ccm@73fd4000{ 426 compatible = "fsl,imx51-ccm"; 427 reg = <0x73fd4000 0x4000>; 428 interrupts = <0 71 0x04 0 72 0x04>; 429 #clock-cells = <1>; 430 }; 431 }; 432 433 aips@80000000 { /* AIPS2 */ 434 compatible = "fsl,aips-bus", "simple-bus"; 435 #address-cells = <1>; 436 #size-cells = <1>; 437 reg = <0x80000000 0x10000000>; 438 ranges; 439 440 aipstz2: bridge@83f00000 { 441 compatible = "fsl,imx51-aipstz"; 442 reg = <0x83f00000 0x60>; 443 }; 444 445 iim: iim@83f98000 { 446 compatible = "fsl,imx51-iim", "fsl,imx27-iim"; 447 reg = <0x83f98000 0x4000>; 448 interrupts = <69>; 449 clocks = <&clks IMX5_CLK_IIM_GATE>; 450 }; 451 452 tigerp: tigerp@83fa0000 { 453 compatible = "fsl,imx51-tigerp"; 454 reg = <0x83fa0000 0x28>; 455 }; 456 457 owire: owire@83fa4000 { 458 compatible = "fsl,imx51-owire", "fsl,imx21-owire"; 459 reg = <0x83fa4000 0x4000>; 460 interrupts = <88>; 461 clocks = <&clks IMX5_CLK_OWIRE_GATE>; 462 status = "disabled"; 463 }; 464 465 ecspi2: ecspi@83fac000 { 466 #address-cells = <1>; 467 #size-cells = <0>; 468 compatible = "fsl,imx51-ecspi"; 469 reg = <0x83fac000 0x4000>; 470 interrupts = <37>; 471 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, 472 <&clks IMX5_CLK_ECSPI2_PER_GATE>; 473 clock-names = "ipg", "per"; 474 status = "disabled"; 475 }; 476 477 sdma: sdma@83fb0000 { 478 compatible = "fsl,imx51-sdma", "fsl,imx35-sdma"; 479 reg = <0x83fb0000 0x4000>; 480 interrupts = <6>; 481 clocks = <&clks IMX5_CLK_SDMA_GATE>, 482 <&clks IMX5_CLK_AHB>; 483 clock-names = "ipg", "ahb"; 484 #dma-cells = <3>; 485 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx51.bin"; 486 }; 487 488 cspi: cspi@83fc0000 { 489 #address-cells = <1>; 490 #size-cells = <0>; 491 compatible = "fsl,imx51-cspi", "fsl,imx35-cspi"; 492 reg = <0x83fc0000 0x4000>; 493 interrupts = <38>; 494 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, 495 <&clks IMX5_CLK_CSPI_IPG_GATE>; 496 clock-names = "ipg", "per"; 497 status = "disabled"; 498 }; 499 500 i2c2: i2c@83fc4000 { 501 #address-cells = <1>; 502 #size-cells = <0>; 503 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; 504 reg = <0x83fc4000 0x4000>; 505 interrupts = <63>; 506 clocks = <&clks IMX5_CLK_I2C2_GATE>; 507 status = "disabled"; 508 }; 509 510 i2c1: i2c@83fc8000 { 511 #address-cells = <1>; 512 #size-cells = <0>; 513 compatible = "fsl,imx51-i2c", "fsl,imx21-i2c"; 514 reg = <0x83fc8000 0x4000>; 515 interrupts = <62>; 516 clocks = <&clks IMX5_CLK_I2C1_GATE>; 517 status = "disabled"; 518 }; 519 520 ssi1: ssi@83fcc000 { 521 #sound-dai-cells = <0>; 522 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 523 reg = <0x83fcc000 0x4000>; 524 interrupts = <29>; 525 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, 526 <&clks IMX5_CLK_SSI1_ROOT_GATE>; 527 clock-names = "ipg", "baud"; 528 dmas = <&sdma 28 0 0>, 529 <&sdma 29 0 0>; 530 dma-names = "rx", "tx"; 531 fsl,fifo-depth = <15>; 532 status = "disabled"; 533 }; 534 535 audmux: audmux@83fd0000 { 536 compatible = "fsl,imx51-audmux", "fsl,imx31-audmux"; 537 reg = <0x83fd0000 0x4000>; 538 clocks = <&clks IMX5_CLK_DUMMY>; 539 clock-names = "audmux"; 540 status = "disabled"; 541 }; 542 543 m4if: m4if@83fd8000 { 544 compatible = "fsl,imx51-m4if"; 545 reg = <0x83fd8000 0x1000>; 546 }; 547 548 weim: weim@83fda000 { 549 #address-cells = <2>; 550 #size-cells = <1>; 551 compatible = "fsl,imx51-weim"; 552 reg = <0x83fda000 0x1000>; 553 clocks = <&clks IMX5_CLK_EMI_SLOW_GATE>; 554 ranges = < 555 0 0 0xb0000000 0x08000000 556 1 0 0xb8000000 0x08000000 557 2 0 0xc0000000 0x08000000 558 3 0 0xc8000000 0x04000000 559 4 0 0xcc000000 0x02000000 560 5 0 0xce000000 0x02000000 561 >; 562 status = "disabled"; 563 }; 564 565 nfc: nand@83fdb000 { 566 #address-cells = <1>; 567 #size-cells = <1>; 568 compatible = "fsl,imx51-nand"; 569 reg = <0x83fdb000 0x1000 0xcfff0000 0x10000>; 570 interrupts = <8>; 571 clocks = <&clks IMX5_CLK_NFC_GATE>; 572 status = "disabled"; 573 }; 574 575 pata: pata@83fe0000 { 576 compatible = "fsl,imx51-pata", "fsl,imx27-pata"; 577 reg = <0x83fe0000 0x4000>; 578 interrupts = <70>; 579 clocks = <&clks IMX5_CLK_PATA_GATE>; 580 status = "disabled"; 581 }; 582 583 ssi3: ssi@83fe8000 { 584 #sound-dai-cells = <0>; 585 compatible = "fsl,imx51-ssi", "fsl,imx21-ssi"; 586 reg = <0x83fe8000 0x4000>; 587 interrupts = <96>; 588 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, 589 <&clks IMX5_CLK_SSI3_ROOT_GATE>; 590 clock-names = "ipg", "baud"; 591 dmas = <&sdma 46 0 0>, 592 <&sdma 47 0 0>; 593 dma-names = "rx", "tx"; 594 fsl,fifo-depth = <15>; 595 status = "disabled"; 596 }; 597 598 fec: ethernet@83fec000 { 599 compatible = "fsl,imx51-fec", "fsl,imx27-fec"; 600 reg = <0x83fec000 0x4000>; 601 interrupts = <87>; 602 clocks = <&clks IMX5_CLK_FEC_GATE>, 603 <&clks IMX5_CLK_FEC_GATE>, 604 <&clks IMX5_CLK_FEC_GATE>; 605 clock-names = "ipg", "ahb", "ptp"; 606 status = "disabled"; 607 }; 608 609 vpu@83ff4000 { 610 compatible = "fsl,imx51-vpu", "cnm,codahx4"; 611 reg = <0x83ff4000 0x1000>; 612 interrupts = <9>; 613 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, 614 <&clks IMX5_CLK_VPU_GATE>; 615 clock-names = "per", "ahb"; 616 resets = <&src 1>; 617 iram = <&iram>; 618 }; 619 620 sahara: crypto@83ff8000 { 621 compatible = "fsl,imx53-sahara", "fsl,imx51-sahara"; 622 reg = <0x83ff8000 0x4000>; 623 interrupts = <19 20>; 624 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, 625 <&clks IMX5_CLK_SAHARA_IPG_GATE>; 626 clock-names = "ipg", "ahb"; 627 }; 628 }; 629 }; 630}; 631