1/* 2 * Copyright 2011 Freescale Semiconductor, Inc. 3 * Copyright 2011 Linaro Ltd. 4 * 5 * The code contained herein is licensed under the GNU General Public 6 * License. You may obtain a copy of the GNU General Public License 7 * Version 2 or later at the following locations: 8 * 9 * http://www.opensource.org/licenses/gpl-license.html 10 * http://www.gnu.org/copyleft/gpl.html 11 */ 12 13#include "imx53-pinfunc.h" 14#include <dt-bindings/clock/imx5-clock.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/input/input.h> 17#include <dt-bindings/interrupt-controller/irq.h> 18 19/ { 20 #address-cells = <1>; 21 #size-cells = <1>; 22 /* 23 * The decompressor and also some bootloaders rely on a 24 * pre-existing /chosen node to be available to insert the 25 * command line and merge other ATAGS info. 26 */ 27 chosen {}; 28 29 aliases { 30 ethernet0 = &fec; 31 gpio0 = &gpio1; 32 gpio1 = &gpio2; 33 gpio2 = &gpio3; 34 gpio3 = &gpio4; 35 gpio4 = &gpio5; 36 gpio5 = &gpio6; 37 gpio6 = &gpio7; 38 i2c0 = &i2c1; 39 i2c1 = &i2c2; 40 i2c2 = &i2c3; 41 mmc0 = &esdhc1; 42 mmc1 = &esdhc2; 43 mmc2 = &esdhc3; 44 mmc3 = &esdhc4; 45 serial0 = &uart1; 46 serial1 = &uart2; 47 serial2 = &uart3; 48 serial3 = &uart4; 49 serial4 = &uart5; 50 spi0 = &ecspi1; 51 spi1 = &ecspi2; 52 spi2 = &cspi; 53 }; 54 55 cpus { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 cpu0: cpu@0 { 59 device_type = "cpu"; 60 compatible = "arm,cortex-a8"; 61 reg = <0x0>; 62 clocks = <&clks IMX5_CLK_ARM>; 63 clock-latency = <61036>; 64 voltage-tolerance = <5>; 65 operating-points = < 66 /* kHz */ 67 166666 850000 68 400000 900000 69 800000 1050000 70 1000000 1200000 71 1200000 1300000 72 >; 73 }; 74 }; 75 76 display-subsystem { 77 compatible = "fsl,imx-display-subsystem"; 78 ports = <&ipu_di0>, <&ipu_di1>; 79 }; 80 81 tzic: tz-interrupt-controller@fffc000 { 82 compatible = "fsl,imx53-tzic", "fsl,tzic"; 83 interrupt-controller; 84 #interrupt-cells = <1>; 85 reg = <0x0fffc000 0x4000>; 86 }; 87 88 clocks { 89 ckil { 90 compatible = "fsl,imx-ckil", "fixed-clock"; 91 #clock-cells = <0>; 92 clock-frequency = <32768>; 93 }; 94 95 ckih1 { 96 compatible = "fsl,imx-ckih1", "fixed-clock"; 97 #clock-cells = <0>; 98 clock-frequency = <22579200>; 99 }; 100 101 ckih2 { 102 compatible = "fsl,imx-ckih2", "fixed-clock"; 103 #clock-cells = <0>; 104 clock-frequency = <0>; 105 }; 106 107 osc { 108 compatible = "fsl,imx-osc", "fixed-clock"; 109 #clock-cells = <0>; 110 clock-frequency = <24000000>; 111 }; 112 }; 113 114 pmu: pmu { 115 compatible = "arm,cortex-a8-pmu"; 116 interrupt-parent = <&tzic>; 117 interrupts = <77>; 118 }; 119 120 usbphy0: usbphy-0 { 121 compatible = "usb-nop-xceiv"; 122 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>; 123 clock-names = "main_clk"; 124 #phy-cells = <0>; 125 status = "okay"; 126 }; 127 128 usbphy1: usbphy-1 { 129 compatible = "usb-nop-xceiv"; 130 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>; 131 clock-names = "main_clk"; 132 #phy-cells = <0>; 133 status = "okay"; 134 }; 135 136 soc { 137 #address-cells = <1>; 138 #size-cells = <1>; 139 compatible = "simple-bus"; 140 interrupt-parent = <&tzic>; 141 ranges; 142 143 sata: sata@10000000 { 144 compatible = "fsl,imx53-ahci"; 145 reg = <0x10000000 0x1000>; 146 interrupts = <28>; 147 clocks = <&clks IMX5_CLK_SATA_GATE>, 148 <&clks IMX5_CLK_SATA_REF>, 149 <&clks IMX5_CLK_AHB>; 150 clock-names = "sata", "sata_ref", "ahb"; 151 status = "disabled"; 152 }; 153 154 ipu: ipu@18000000 { 155 #address-cells = <1>; 156 #size-cells = <0>; 157 compatible = "fsl,imx53-ipu"; 158 reg = <0x18000000 0x08000000>; 159 interrupts = <11 10>; 160 clocks = <&clks IMX5_CLK_IPU_GATE>, 161 <&clks IMX5_CLK_IPU_DI0_GATE>, 162 <&clks IMX5_CLK_IPU_DI1_GATE>; 163 clock-names = "bus", "di0", "di1"; 164 resets = <&src 2>; 165 166 ipu_csi0: port@0 { 167 reg = <0>; 168 }; 169 170 ipu_csi1: port@1 { 171 reg = <1>; 172 }; 173 174 ipu_di0: port@2 { 175 #address-cells = <1>; 176 #size-cells = <0>; 177 reg = <2>; 178 179 ipu_di0_disp0: endpoint@0 { 180 reg = <0>; 181 }; 182 183 ipu_di0_lvds0: endpoint@1 { 184 reg = <1>; 185 remote-endpoint = <&lvds0_in>; 186 }; 187 }; 188 189 ipu_di1: port@3 { 190 #address-cells = <1>; 191 #size-cells = <0>; 192 reg = <3>; 193 194 ipu_di1_disp1: endpoint@0 { 195 reg = <0>; 196 }; 197 198 ipu_di1_lvds1: endpoint@1 { 199 reg = <1>; 200 remote-endpoint = <&lvds1_in>; 201 }; 202 203 ipu_di1_tve: endpoint@2 { 204 reg = <2>; 205 remote-endpoint = <&tve_in>; 206 }; 207 }; 208 }; 209 210 aips@50000000 { /* AIPS1 */ 211 compatible = "fsl,aips-bus", "simple-bus"; 212 #address-cells = <1>; 213 #size-cells = <1>; 214 reg = <0x50000000 0x10000000>; 215 ranges; 216 217 spba@50000000 { 218 compatible = "fsl,spba-bus", "simple-bus"; 219 #address-cells = <1>; 220 #size-cells = <1>; 221 reg = <0x50000000 0x40000>; 222 ranges; 223 224 esdhc1: esdhc@50004000 { 225 compatible = "fsl,imx53-esdhc"; 226 reg = <0x50004000 0x4000>; 227 interrupts = <1>; 228 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>, 229 <&clks IMX5_CLK_DUMMY>, 230 <&clks IMX5_CLK_ESDHC1_PER_GATE>; 231 clock-names = "ipg", "ahb", "per"; 232 bus-width = <4>; 233 status = "disabled"; 234 }; 235 236 esdhc2: esdhc@50008000 { 237 compatible = "fsl,imx53-esdhc"; 238 reg = <0x50008000 0x4000>; 239 interrupts = <2>; 240 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>, 241 <&clks IMX5_CLK_DUMMY>, 242 <&clks IMX5_CLK_ESDHC2_PER_GATE>; 243 clock-names = "ipg", "ahb", "per"; 244 bus-width = <4>; 245 status = "disabled"; 246 }; 247 248 uart3: serial@5000c000 { 249 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 250 reg = <0x5000c000 0x4000>; 251 interrupts = <33>; 252 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>, 253 <&clks IMX5_CLK_UART3_PER_GATE>; 254 clock-names = "ipg", "per"; 255 dmas = <&sdma 42 4 0>, <&sdma 43 4 0>; 256 dma-names = "rx", "tx"; 257 status = "disabled"; 258 }; 259 260 ecspi1: ecspi@50010000 { 261 #address-cells = <1>; 262 #size-cells = <0>; 263 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; 264 reg = <0x50010000 0x4000>; 265 interrupts = <36>; 266 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>, 267 <&clks IMX5_CLK_ECSPI1_PER_GATE>; 268 clock-names = "ipg", "per"; 269 status = "disabled"; 270 }; 271 272 ssi2: ssi@50014000 { 273 #sound-dai-cells = <0>; 274 compatible = "fsl,imx53-ssi", 275 "fsl,imx51-ssi", 276 "fsl,imx21-ssi"; 277 reg = <0x50014000 0x4000>; 278 interrupts = <30>; 279 clocks = <&clks IMX5_CLK_SSI2_IPG_GATE>, 280 <&clks IMX5_CLK_SSI2_ROOT_GATE>; 281 clock-names = "ipg", "baud"; 282 dmas = <&sdma 24 1 0>, 283 <&sdma 25 1 0>; 284 dma-names = "rx", "tx"; 285 fsl,fifo-depth = <15>; 286 status = "disabled"; 287 }; 288 289 esdhc3: esdhc@50020000 { 290 compatible = "fsl,imx53-esdhc"; 291 reg = <0x50020000 0x4000>; 292 interrupts = <3>; 293 clocks = <&clks IMX5_CLK_ESDHC3_IPG_GATE>, 294 <&clks IMX5_CLK_DUMMY>, 295 <&clks IMX5_CLK_ESDHC3_PER_GATE>; 296 clock-names = "ipg", "ahb", "per"; 297 bus-width = <4>; 298 status = "disabled"; 299 }; 300 301 esdhc4: esdhc@50024000 { 302 compatible = "fsl,imx53-esdhc"; 303 reg = <0x50024000 0x4000>; 304 interrupts = <4>; 305 clocks = <&clks IMX5_CLK_ESDHC4_IPG_GATE>, 306 <&clks IMX5_CLK_DUMMY>, 307 <&clks IMX5_CLK_ESDHC4_PER_GATE>; 308 clock-names = "ipg", "ahb", "per"; 309 bus-width = <4>; 310 status = "disabled"; 311 }; 312 }; 313 314 aipstz1: bridge@53f00000 { 315 compatible = "fsl,imx53-aipstz"; 316 reg = <0x53f00000 0x60>; 317 }; 318 319 usbotg: usb@53f80000 { 320 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 321 reg = <0x53f80000 0x0200>; 322 interrupts = <18>; 323 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 324 fsl,usbmisc = <&usbmisc 0>; 325 fsl,usbphy = <&usbphy0>; 326 status = "disabled"; 327 }; 328 329 usbh1: usb@53f80200 { 330 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 331 reg = <0x53f80200 0x0200>; 332 interrupts = <14>; 333 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 334 fsl,usbmisc = <&usbmisc 1>; 335 fsl,usbphy = <&usbphy1>; 336 dr_mode = "host"; 337 status = "disabled"; 338 }; 339 340 usbh2: usb@53f80400 { 341 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 342 reg = <0x53f80400 0x0200>; 343 interrupts = <16>; 344 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 345 fsl,usbmisc = <&usbmisc 2>; 346 dr_mode = "host"; 347 status = "disabled"; 348 }; 349 350 usbh3: usb@53f80600 { 351 compatible = "fsl,imx53-usb", "fsl,imx27-usb"; 352 reg = <0x53f80600 0x0200>; 353 interrupts = <17>; 354 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 355 fsl,usbmisc = <&usbmisc 3>; 356 dr_mode = "host"; 357 status = "disabled"; 358 }; 359 360 usbmisc: usbmisc@53f80800 { 361 #index-cells = <1>; 362 compatible = "fsl,imx53-usbmisc"; 363 reg = <0x53f80800 0x200>; 364 clocks = <&clks IMX5_CLK_USBOH3_GATE>; 365 }; 366 367 gpio1: gpio@53f84000 { 368 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 369 reg = <0x53f84000 0x4000>; 370 interrupts = <50 51>; 371 gpio-controller; 372 #gpio-cells = <2>; 373 interrupt-controller; 374 #interrupt-cells = <2>; 375 }; 376 377 gpio2: gpio@53f88000 { 378 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 379 reg = <0x53f88000 0x4000>; 380 interrupts = <52 53>; 381 gpio-controller; 382 #gpio-cells = <2>; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 }; 386 387 gpio3: gpio@53f8c000 { 388 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 389 reg = <0x53f8c000 0x4000>; 390 interrupts = <54 55>; 391 gpio-controller; 392 #gpio-cells = <2>; 393 interrupt-controller; 394 #interrupt-cells = <2>; 395 }; 396 397 gpio4: gpio@53f90000 { 398 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 399 reg = <0x53f90000 0x4000>; 400 interrupts = <56 57>; 401 gpio-controller; 402 #gpio-cells = <2>; 403 interrupt-controller; 404 #interrupt-cells = <2>; 405 }; 406 407 kpp: kpp@53f94000 { 408 compatible = "fsl,imx53-kpp", "fsl,imx21-kpp"; 409 reg = <0x53f94000 0x4000>; 410 interrupts = <60>; 411 clocks = <&clks IMX5_CLK_DUMMY>; 412 status = "disabled"; 413 }; 414 415 wdog1: wdog@53f98000 { 416 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; 417 reg = <0x53f98000 0x4000>; 418 interrupts = <58>; 419 clocks = <&clks IMX5_CLK_DUMMY>; 420 }; 421 422 wdog2: wdog@53f9c000 { 423 compatible = "fsl,imx53-wdt", "fsl,imx21-wdt"; 424 reg = <0x53f9c000 0x4000>; 425 interrupts = <59>; 426 clocks = <&clks IMX5_CLK_DUMMY>; 427 status = "disabled"; 428 }; 429 430 gpt: timer@53fa0000 { 431 compatible = "fsl,imx53-gpt", "fsl,imx31-gpt"; 432 reg = <0x53fa0000 0x4000>; 433 interrupts = <39>; 434 clocks = <&clks IMX5_CLK_GPT_IPG_GATE>, 435 <&clks IMX5_CLK_GPT_HF_GATE>; 436 clock-names = "ipg", "per"; 437 }; 438 439 srtc: rtc@53fa4000 { 440 compatible = "fsl,imx53-rtc"; 441 reg = <0x53fa4000 0x4000>; 442 interrupts = <24>; 443 clocks = <&clks IMX5_CLK_SRTC_GATE>; 444 }; 445 446 iomuxc: iomuxc@53fa8000 { 447 compatible = "fsl,imx53-iomuxc"; 448 reg = <0x53fa8000 0x4000>; 449 }; 450 451 gpr: iomuxc-gpr@53fa8000 { 452 compatible = "fsl,imx53-iomuxc-gpr", "syscon"; 453 reg = <0x53fa8000 0xc>; 454 }; 455 456 ldb: ldb@53fa8008 { 457 #address-cells = <1>; 458 #size-cells = <0>; 459 compatible = "fsl,imx53-ldb"; 460 reg = <0x53fa8008 0x4>; 461 gpr = <&gpr>; 462 clocks = <&clks IMX5_CLK_LDB_DI0_SEL>, 463 <&clks IMX5_CLK_LDB_DI1_SEL>, 464 <&clks IMX5_CLK_IPU_DI0_SEL>, 465 <&clks IMX5_CLK_IPU_DI1_SEL>, 466 <&clks IMX5_CLK_LDB_DI0_GATE>, 467 <&clks IMX5_CLK_LDB_DI1_GATE>; 468 clock-names = "di0_pll", "di1_pll", 469 "di0_sel", "di1_sel", 470 "di0", "di1"; 471 status = "disabled"; 472 473 lvds-channel@0 { 474 #address-cells = <1>; 475 #size-cells = <0>; 476 reg = <0>; 477 status = "disabled"; 478 479 port@0 { 480 reg = <0>; 481 482 lvds0_in: endpoint { 483 remote-endpoint = <&ipu_di0_lvds0>; 484 }; 485 }; 486 487 port@2 { 488 reg = <2>; 489 }; 490 }; 491 492 lvds-channel@1 { 493 #address-cells = <1>; 494 #size-cells = <0>; 495 reg = <1>; 496 status = "disabled"; 497 498 port@1 { 499 reg = <1>; 500 501 lvds1_in: endpoint { 502 remote-endpoint = <&ipu_di1_lvds1>; 503 }; 504 }; 505 506 port@2 { 507 reg = <2>; 508 }; 509 }; 510 }; 511 512 pwm1: pwm@53fb4000 { 513 #pwm-cells = <2>; 514 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; 515 reg = <0x53fb4000 0x4000>; 516 clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, 517 <&clks IMX5_CLK_PWM1_HF_GATE>; 518 clock-names = "ipg", "per"; 519 interrupts = <61>; 520 }; 521 522 pwm2: pwm@53fb8000 { 523 #pwm-cells = <2>; 524 compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; 525 reg = <0x53fb8000 0x4000>; 526 clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, 527 <&clks IMX5_CLK_PWM2_HF_GATE>; 528 clock-names = "ipg", "per"; 529 interrupts = <94>; 530 }; 531 532 uart1: serial@53fbc000 { 533 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 534 reg = <0x53fbc000 0x4000>; 535 interrupts = <31>; 536 clocks = <&clks IMX5_CLK_UART1_IPG_GATE>, 537 <&clks IMX5_CLK_UART1_PER_GATE>; 538 clock-names = "ipg", "per"; 539 dmas = <&sdma 18 4 0>, <&sdma 19 4 0>; 540 dma-names = "rx", "tx"; 541 status = "disabled"; 542 }; 543 544 uart2: serial@53fc0000 { 545 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 546 reg = <0x53fc0000 0x4000>; 547 interrupts = <32>; 548 clocks = <&clks IMX5_CLK_UART2_IPG_GATE>, 549 <&clks IMX5_CLK_UART2_PER_GATE>; 550 clock-names = "ipg", "per"; 551 dmas = <&sdma 12 4 0>, <&sdma 13 4 0>; 552 dma-names = "rx", "tx"; 553 status = "disabled"; 554 }; 555 556 can1: can@53fc8000 { 557 compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; 558 reg = <0x53fc8000 0x4000>; 559 interrupts = <82>; 560 clocks = <&clks IMX5_CLK_CAN1_IPG_GATE>, 561 <&clks IMX5_CLK_CAN1_SERIAL_GATE>; 562 clock-names = "ipg", "per"; 563 status = "disabled"; 564 }; 565 566 can2: can@53fcc000 { 567 compatible = "fsl,imx53-flexcan", "fsl,imx25-flexcan"; 568 reg = <0x53fcc000 0x4000>; 569 interrupts = <83>; 570 clocks = <&clks IMX5_CLK_CAN2_IPG_GATE>, 571 <&clks IMX5_CLK_CAN2_SERIAL_GATE>; 572 clock-names = "ipg", "per"; 573 status = "disabled"; 574 }; 575 576 src: src@53fd0000 { 577 compatible = "fsl,imx53-src", "fsl,imx51-src"; 578 reg = <0x53fd0000 0x4000>; 579 #reset-cells = <1>; 580 }; 581 582 clks: ccm@53fd4000{ 583 compatible = "fsl,imx53-ccm"; 584 reg = <0x53fd4000 0x4000>; 585 interrupts = <0 71 0x04 0 72 0x04>; 586 #clock-cells = <1>; 587 }; 588 589 gpio5: gpio@53fdc000 { 590 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 591 reg = <0x53fdc000 0x4000>; 592 interrupts = <103 104>; 593 gpio-controller; 594 #gpio-cells = <2>; 595 interrupt-controller; 596 #interrupt-cells = <2>; 597 }; 598 599 gpio6: gpio@53fe0000 { 600 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 601 reg = <0x53fe0000 0x4000>; 602 interrupts = <105 106>; 603 gpio-controller; 604 #gpio-cells = <2>; 605 interrupt-controller; 606 #interrupt-cells = <2>; 607 }; 608 609 gpio7: gpio@53fe4000 { 610 compatible = "fsl,imx53-gpio", "fsl,imx35-gpio"; 611 reg = <0x53fe4000 0x4000>; 612 interrupts = <107 108>; 613 gpio-controller; 614 #gpio-cells = <2>; 615 interrupt-controller; 616 #interrupt-cells = <2>; 617 }; 618 619 i2c3: i2c@53fec000 { 620 #address-cells = <1>; 621 #size-cells = <0>; 622 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 623 reg = <0x53fec000 0x4000>; 624 interrupts = <64>; 625 clocks = <&clks IMX5_CLK_I2C3_GATE>; 626 status = "disabled"; 627 }; 628 629 uart4: serial@53ff0000 { 630 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 631 reg = <0x53ff0000 0x4000>; 632 interrupts = <13>; 633 clocks = <&clks IMX5_CLK_UART4_IPG_GATE>, 634 <&clks IMX5_CLK_UART4_PER_GATE>; 635 clock-names = "ipg", "per"; 636 dmas = <&sdma 2 4 0>, <&sdma 3 4 0>; 637 dma-names = "rx", "tx"; 638 status = "disabled"; 639 }; 640 }; 641 642 aips@60000000 { /* AIPS2 */ 643 compatible = "fsl,aips-bus", "simple-bus"; 644 #address-cells = <1>; 645 #size-cells = <1>; 646 reg = <0x60000000 0x10000000>; 647 ranges; 648 649 aipstz2: bridge@63f00000 { 650 compatible = "fsl,imx53-aipstz"; 651 reg = <0x63f00000 0x60>; 652 }; 653 654 iim: iim@63f98000 { 655 compatible = "fsl,imx53-iim", "fsl,imx27-iim"; 656 reg = <0x63f98000 0x4000>; 657 interrupts = <69>; 658 clocks = <&clks IMX5_CLK_IIM_GATE>; 659 }; 660 661 uart5: serial@63f90000 { 662 compatible = "fsl,imx53-uart", "fsl,imx21-uart"; 663 reg = <0x63f90000 0x4000>; 664 interrupts = <86>; 665 clocks = <&clks IMX5_CLK_UART5_IPG_GATE>, 666 <&clks IMX5_CLK_UART5_PER_GATE>; 667 clock-names = "ipg", "per"; 668 dmas = <&sdma 16 4 0>, <&sdma 17 4 0>; 669 dma-names = "rx", "tx"; 670 status = "disabled"; 671 }; 672 673 tigerp: tigerp@63fa0000 { 674 compatible = "fsl,imx53-tigerp", "fsl,imx51-tigerp"; 675 reg = <0x63fa0000 0x28>; 676 }; 677 678 owire: owire@63fa4000 { 679 compatible = "fsl,imx53-owire", "fsl,imx21-owire"; 680 reg = <0x63fa4000 0x4000>; 681 clocks = <&clks IMX5_CLK_OWIRE_GATE>; 682 status = "disabled"; 683 }; 684 685 ecspi2: ecspi@63fac000 { 686 #address-cells = <1>; 687 #size-cells = <0>; 688 compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; 689 reg = <0x63fac000 0x4000>; 690 interrupts = <37>; 691 clocks = <&clks IMX5_CLK_ECSPI2_IPG_GATE>, 692 <&clks IMX5_CLK_ECSPI2_PER_GATE>; 693 clock-names = "ipg", "per"; 694 status = "disabled"; 695 }; 696 697 sdma: sdma@63fb0000 { 698 compatible = "fsl,imx53-sdma", "fsl,imx35-sdma"; 699 reg = <0x63fb0000 0x4000>; 700 interrupts = <6>; 701 clocks = <&clks IMX5_CLK_SDMA_GATE>, 702 <&clks IMX5_CLK_AHB>; 703 clock-names = "ipg", "ahb"; 704 #dma-cells = <3>; 705 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; 706 }; 707 708 cspi: cspi@63fc0000 { 709 #address-cells = <1>; 710 #size-cells = <0>; 711 compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; 712 reg = <0x63fc0000 0x4000>; 713 interrupts = <38>; 714 clocks = <&clks IMX5_CLK_CSPI_IPG_GATE>, 715 <&clks IMX5_CLK_CSPI_IPG_GATE>; 716 clock-names = "ipg", "per"; 717 status = "disabled"; 718 }; 719 720 i2c2: i2c@63fc4000 { 721 #address-cells = <1>; 722 #size-cells = <0>; 723 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 724 reg = <0x63fc4000 0x4000>; 725 interrupts = <63>; 726 clocks = <&clks IMX5_CLK_I2C2_GATE>; 727 status = "disabled"; 728 }; 729 730 i2c1: i2c@63fc8000 { 731 #address-cells = <1>; 732 #size-cells = <0>; 733 compatible = "fsl,imx53-i2c", "fsl,imx21-i2c"; 734 reg = <0x63fc8000 0x4000>; 735 interrupts = <62>; 736 clocks = <&clks IMX5_CLK_I2C1_GATE>; 737 status = "disabled"; 738 }; 739 740 ssi1: ssi@63fcc000 { 741 #sound-dai-cells = <0>; 742 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", 743 "fsl,imx21-ssi"; 744 reg = <0x63fcc000 0x4000>; 745 interrupts = <29>; 746 clocks = <&clks IMX5_CLK_SSI1_IPG_GATE>, 747 <&clks IMX5_CLK_SSI1_ROOT_GATE>; 748 clock-names = "ipg", "baud"; 749 dmas = <&sdma 28 0 0>, 750 <&sdma 29 0 0>; 751 dma-names = "rx", "tx"; 752 fsl,fifo-depth = <15>; 753 status = "disabled"; 754 }; 755 756 audmux: audmux@63fd0000 { 757 compatible = "fsl,imx53-audmux", "fsl,imx31-audmux"; 758 reg = <0x63fd0000 0x4000>; 759 status = "disabled"; 760 }; 761 762 nfc: nand@63fdb000 { 763 compatible = "fsl,imx53-nand"; 764 reg = <0x63fdb000 0x1000 0xf7ff0000 0x10000>; 765 interrupts = <8>; 766 clocks = <&clks IMX5_CLK_NFC_GATE>; 767 status = "disabled"; 768 }; 769 770 ssi3: ssi@63fe8000 { 771 #sound-dai-cells = <0>; 772 compatible = "fsl,imx53-ssi", "fsl,imx51-ssi", 773 "fsl,imx21-ssi"; 774 reg = <0x63fe8000 0x4000>; 775 interrupts = <96>; 776 clocks = <&clks IMX5_CLK_SSI3_IPG_GATE>, 777 <&clks IMX5_CLK_SSI3_ROOT_GATE>; 778 clock-names = "ipg", "baud"; 779 dmas = <&sdma 46 0 0>, 780 <&sdma 47 0 0>; 781 dma-names = "rx", "tx"; 782 fsl,fifo-depth = <15>; 783 status = "disabled"; 784 }; 785 786 fec: ethernet@63fec000 { 787 compatible = "fsl,imx53-fec", "fsl,imx25-fec"; 788 reg = <0x63fec000 0x4000>; 789 interrupts = <87>; 790 clocks = <&clks IMX5_CLK_FEC_GATE>, 791 <&clks IMX5_CLK_FEC_GATE>, 792 <&clks IMX5_CLK_FEC_GATE>; 793 clock-names = "ipg", "ahb", "ptp"; 794 status = "disabled"; 795 }; 796 797 tve: tve@63ff0000 { 798 compatible = "fsl,imx53-tve"; 799 reg = <0x63ff0000 0x1000>; 800 interrupts = <92>; 801 clocks = <&clks IMX5_CLK_TVE_GATE>, 802 <&clks IMX5_CLK_IPU_DI1_SEL>; 803 clock-names = "tve", "di_sel"; 804 status = "disabled"; 805 806 port { 807 tve_in: endpoint { 808 remote-endpoint = <&ipu_di1_tve>; 809 }; 810 }; 811 }; 812 813 vpu: vpu@63ff4000 { 814 compatible = "fsl,imx53-vpu", "cnm,coda7541"; 815 reg = <0x63ff4000 0x1000>; 816 interrupts = <9>; 817 clocks = <&clks IMX5_CLK_VPU_REFERENCE_GATE>, 818 <&clks IMX5_CLK_VPU_GATE>; 819 clock-names = "per", "ahb"; 820 resets = <&src 1>; 821 iram = <&ocram>; 822 }; 823 824 sahara: crypto@63ff8000 { 825 compatible = "fsl,imx53-sahara"; 826 reg = <0x63ff8000 0x4000>; 827 interrupts = <19 20>; 828 clocks = <&clks IMX5_CLK_SAHARA_IPG_GATE>, 829 <&clks IMX5_CLK_SAHARA_IPG_GATE>; 830 clock-names = "ipg", "ahb"; 831 }; 832 }; 833 834 ocram: sram@f8000000 { 835 compatible = "mmio-sram"; 836 reg = <0xf8000000 0x20000>; 837 clocks = <&clks IMX5_CLK_OCRAM>; 838 }; 839 }; 840}; 841