1/* 2 * Copyright 2017 Gateworks Corporation 3 * 4 * This file is dual-licensed: you can use it either under the terms 5 * of the GPL or the X11 license, at your option. Note that this dual 6 * licensing only applies to this file, and not this project as a 7 * whole. 8 * 9 * a) This file is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This file is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public 20 * License along with this file; if not, write to the Free 21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, 22 * MA 02110-1301 USA 23 * 24 * Or, alternatively, 25 * 26 * b) Permission is hereby granted, free of charge, to any person 27 * obtaining a copy of this software and associated documentation 28 * files (the "Software"), to deal in the Software without 29 * restriction, including without limitation the rights to use, 30 * copy, modify, merge, publish, distribute, sublicense, and/or 31 * sell copies of the Software, and to permit persons to whom the 32 * Software is furnished to do so, subject to the following 33 * conditions: 34 * 35 * The above copyright notice and this permission notice shall be 36 * included in all copies or substantial portions of the Software. 37 * 38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, 43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 45 * OTHER DEALINGS IN THE SOFTWARE. 46 */ 47 48#include <dt-bindings/gpio/gpio.h> 49 50/ { 51 /* these are used by bootloader for disabling nodes */ 52 aliases { 53 led0 = &led0; 54 led1 = &led1; 55 led2 = &led2; 56 usb0 = &usbh1; 57 usb1 = &usbotg; 58 }; 59 60 chosen { 61 stdout-path = &uart2; 62 }; 63 64 backlight { 65 compatible = "pwm-backlight"; 66 pwms = <&pwm4 0 5000000>; 67 brightness-levels = <0 4 8 16 32 64 128 255>; 68 default-brightness-level = <7>; 69 }; 70 71 leds { 72 compatible = "gpio-leds"; 73 pinctrl-names = "default"; 74 pinctrl-0 = <&pinctrl_gpio_leds>; 75 76 led0: user1 { 77 label = "user1"; 78 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ 79 default-state = "on"; 80 linux,default-trigger = "heartbeat"; 81 }; 82 83 led1: user2 { 84 label = "user2"; 85 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ 86 default-state = "off"; 87 }; 88 89 led2: user3 { 90 label = "user3"; 91 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ 92 default-state = "off"; 93 }; 94 }; 95 96 memory@10000000 { 97 reg = <0x10000000 0x40000000>; 98 }; 99 100 pps { 101 compatible = "pps-gpio"; 102 pinctrl-names = "default"; 103 pinctrl-0 = <&pinctrl_pps>; 104 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>; 105 }; 106 107 reg_1p0v: regulator-1p0v { 108 compatible = "regulator-fixed"; 109 regulator-name = "1P0V"; 110 regulator-min-microvolt = <1000000>; 111 regulator-max-microvolt = <1000000>; 112 regulator-always-on; 113 }; 114 115 reg_3p3v: regulator-3p3v { 116 compatible = "regulator-fixed"; 117 regulator-name = "3P3V"; 118 regulator-min-microvolt = <3300000>; 119 regulator-max-microvolt = <3300000>; 120 regulator-always-on; 121 }; 122 123 reg_usb_h1_vbus: regulator-usb-h1-vbus { 124 compatible = "regulator-fixed"; 125 regulator-name = "usb_h1_vbus"; 126 regulator-min-microvolt = <5000000>; 127 regulator-max-microvolt = <5000000>; 128 regulator-always-on; 129 }; 130 131 reg_usb_otg_vbus: regulator-usb-otg-vbus { 132 compatible = "regulator-fixed"; 133 regulator-name = "usb_otg_vbus"; 134 regulator-min-microvolt = <5000000>; 135 regulator-max-microvolt = <5000000>; 136 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>; 137 enable-active-high; 138 }; 139}; 140 141&clks { 142 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, 143 <&clks IMX6QDL_CLK_LDB_DI1_SEL>; 144 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, 145 <&clks IMX6QDL_CLK_PLL3_USB_OTG>; 146}; 147 148&fec { 149 pinctrl-names = "default"; 150 pinctrl-0 = <&pinctrl_enet>; 151 phy-mode = "rgmii-id"; 152 status = "okay"; 153 154 fixed-link { 155 speed = <1000>; 156 full-duplex; 157 }; 158 159 mdio { 160 #address-cells = <1>; 161 #size-cells = <0>; 162 163 switch@0 { 164 compatible = "marvell,mv88e6085"; 165 reg = <0>; 166 167 ports { 168 #address-cells = <1>; 169 #size-cells = <0>; 170 171 port@0 { 172 reg = <0>; 173 label = "lan4"; 174 }; 175 176 port@1 { 177 reg = <1>; 178 label = "lan3"; 179 }; 180 181 port@2 { 182 reg = <2>; 183 label = "lan2"; 184 }; 185 186 port@3 { 187 reg = <3>; 188 label = "lan1"; 189 }; 190 191 port@5 { 192 reg = <5>; 193 label = "cpu"; 194 ethernet = <&fec>; 195 }; 196 }; 197 }; 198 }; 199}; 200 201&i2c1 { 202 clock-frequency = <100000>; 203 pinctrl-names = "default"; 204 pinctrl-0 = <&pinctrl_i2c1>; 205 status = "okay"; 206 207 pca9555: gpio@23 { 208 compatible = "nxp,pca9555"; 209 reg = <0x23>; 210 gpio-controller; 211 #gpio-cells = <2>; 212 }; 213 214 eeprom1: eeprom@50 { 215 compatible = "atmel,24c02"; 216 reg = <0x50>; 217 pagesize = <16>; 218 }; 219 220 eeprom2: eeprom@51 { 221 compatible = "atmel,24c02"; 222 reg = <0x51>; 223 pagesize = <16>; 224 }; 225 226 eeprom3: eeprom@52 { 227 compatible = "atmel,24c02"; 228 reg = <0x52>; 229 pagesize = <16>; 230 }; 231 232 eeprom4: eeprom@53 { 233 compatible = "atmel,24c02"; 234 reg = <0x53>; 235 pagesize = <16>; 236 }; 237 238 dts1672: rtc@68 { 239 compatible = "dallas,ds1672"; 240 reg = <0x68>; 241 }; 242}; 243 244&i2c2 { 245 clock-frequency = <100000>; 246 pinctrl-names = "default"; 247 pinctrl-0 = <&pinctrl_i2c2>; 248 status = "okay"; 249 250 ltc3676: pmic@3c { 251 compatible = "lltc,ltc3676"; 252 reg = <0x3c>; 253 interrupt-parent = <&gpio1>; 254 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 255 256 regulators { 257 /* VDD_SOC (1+R1/R2 = 1.635) */ 258 reg_vdd_soc: sw1 { 259 regulator-name = "vddsoc"; 260 regulator-min-microvolt = <674400>; 261 regulator-max-microvolt = <1308000>; 262 lltc,fb-voltage-divider = <127000 200000>; 263 regulator-ramp-delay = <7000>; 264 regulator-boot-on; 265 regulator-always-on; 266 }; 267 268 /* VDD_1P8 (1+R1/R2 = 2.505): GbE switch */ 269 reg_1p8v: sw2 { 270 regulator-name = "vdd1p8"; 271 regulator-min-microvolt = <1033310>; 272 regulator-max-microvolt = <2004000>; 273 lltc,fb-voltage-divider = <301000 200000>; 274 regulator-ramp-delay = <7000>; 275 regulator-boot-on; 276 regulator-always-on; 277 }; 278 279 /* VDD_ARM (1+R1/R2 = 1.635) */ 280 reg_vdd_arm: sw3 { 281 regulator-name = "vddarm"; 282 regulator-min-microvolt = <674400>; 283 regulator-max-microvolt = <1308000>; 284 lltc,fb-voltage-divider = <127000 200000>; 285 regulator-ramp-delay = <7000>; 286 regulator-boot-on; 287 regulator-always-on; 288 }; 289 290 /* VDD_DDR (1+R1/R2 = 2.105) */ 291 reg_vdd_ddr: sw4 { 292 regulator-name = "vddddr"; 293 regulator-min-microvolt = <868310>; 294 regulator-max-microvolt = <1684000>; 295 lltc,fb-voltage-divider = <221000 200000>; 296 regulator-ramp-delay = <7000>; 297 regulator-boot-on; 298 regulator-always-on; 299 }; 300 301 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */ 302 reg_2p5v: ldo2 { 303 regulator-name = "vdd2p5"; 304 regulator-min-microvolt = <2490375>; 305 regulator-max-microvolt = <2490375>; 306 lltc,fb-voltage-divider = <487000 200000>; 307 regulator-boot-on; 308 regulator-always-on; 309 }; 310 311 /* VDD_HIGH (1+R1/R2 = 4.17) */ 312 reg_3p0v: ldo4 { 313 regulator-name = "vdd3p0"; 314 regulator-min-microvolt = <3023250>; 315 regulator-max-microvolt = <3023250>; 316 lltc,fb-voltage-divider = <634000 200000>; 317 regulator-boot-on; 318 regulator-always-on; 319 }; 320 }; 321 }; 322}; 323 324&i2c3 { 325 clock-frequency = <100000>; 326 pinctrl-names = "default"; 327 pinctrl-0 = <&pinctrl_i2c3>; 328 status = "okay"; 329 330 egalax_ts: touchscreen@4 { 331 compatible = "eeti,egalax_ts"; 332 reg = <0x04>; 333 interrupt-parent = <&gpio1>; 334 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 335 wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>; 336 }; 337}; 338 339&ldb { 340 status = "okay"; 341 342 lvds-channel@0 { 343 fsl,data-mapping = "spwg"; 344 fsl,data-width = <18>; 345 status = "okay"; 346 347 display-timings { 348 native-mode = <&timing0>; 349 timing0: hsd100pxn1 { 350 clock-frequency = <65000000>; 351 hactive = <1024>; 352 vactive = <768>; 353 hback-porch = <220>; 354 hfront-porch = <40>; 355 vback-porch = <21>; 356 vfront-porch = <7>; 357 hsync-len = <60>; 358 vsync-len = <10>; 359 }; 360 }; 361 }; 362}; 363 364&pcie { 365 pinctrl-names = "default"; 366 pinctrl-0 = <&pinctrl_pcie>; 367 reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; 368 status = "okay"; 369}; 370 371&pwm2 { 372 pinctrl-names = "default"; 373 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ 374 status = "disabled"; 375}; 376 377&pwm3 { 378 pinctrl-names = "default"; 379 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ 380 status = "disabled"; 381}; 382 383&pwm4 { 384 pinctrl-names = "default"; 385 pinctrl-0 = <&pinctrl_pwm4>; 386 status = "okay"; 387}; 388 389&uart1 { 390 pinctrl-names = "default"; 391 pinctrl-0 = <&pinctrl_uart1>; 392 status = "okay"; 393}; 394 395&uart2 { 396 pinctrl-names = "default"; 397 pinctrl-0 = <&pinctrl_uart2>; 398 status = "okay"; 399}; 400 401&uart3 { 402 pinctrl-names = "default"; 403 pinctrl-0 = <&pinctrl_uart3>; 404 uart-has-rtscts; 405 status = "okay"; 406}; 407 408&uart4 { 409 pinctrl-names = "default"; 410 pinctrl-0 = <&pinctrl_uart4>; 411 uart-has-rtscts; 412 status = "okay"; 413}; 414 415&uart5 { 416 pinctrl-names = "default"; 417 pinctrl-0 = <&pinctrl_uart5>; 418 status = "okay"; 419}; 420 421&usbotg { 422 vbus-supply = <®_usb_otg_vbus>; 423 pinctrl-names = "default"; 424 pinctrl-0 = <&pinctrl_usbotg>; 425 disable-over-current; 426 status = "okay"; 427}; 428 429&usbh1 { 430 vbus-supply = <®_usb_h1_vbus>; 431 status = "okay"; 432}; 433 434&usdhc3 { 435 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 436 pinctrl-0 = <&pinctrl_usdhc3>; 437 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 438 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 439 non-removable; 440 vmmc-supply = <®_3p3v>; 441 keep-power-in-suspend; 442 status = "okay"; 443}; 444 445&wdog1 { 446 pinctrl-names = "default"; 447 pinctrl-0 = <&pinctrl_wdog>; 448 fsl,ext-reset-output; 449}; 450 451&iomuxc { 452 pinctrl_enet: enetgrp { 453 fsl,pins = < 454 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030 455 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030 456 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030 457 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030 458 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030 459 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030 460 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030 461 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030 462 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030 463 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030 464 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030 465 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030 466 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 467 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 468 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 469 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8 470 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x4001b0b0 /* PHY_RST# */ 471 >; 472 }; 473 474 pinctrl_gpio_leds: gpioledsgrp { 475 fsl,pins = < 476 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0 477 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 478 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0 479 >; 480 }; 481 482 pinctrl_i2c1: i2c1grp { 483 fsl,pins = < 484 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 485 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 486 >; 487 }; 488 489 pinctrl_i2c2: i2c2grp { 490 fsl,pins = < 491 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 492 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 493 >; 494 }; 495 496 pinctrl_i2c3: i2c3grp { 497 fsl,pins = < 498 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 499 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 500 >; 501 }; 502 503 pinctrl_pcie: pciegrp { 504 fsl,pins = < 505 MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ 506 >; 507 }; 508 509 pinctrl_pmic: pmicgrp { 510 fsl,pins = < 511 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x1b0b0 /* PMIC_IRQ# */ 512 >; 513 }; 514 515 pinctrl_pps: ppsgrp { 516 fsl,pins = < 517 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1 518 >; 519 }; 520 521 pinctrl_pwm2: pwm2grp { 522 fsl,pins = < 523 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 524 >; 525 }; 526 527 pinctrl_pwm3: pwm3grp { 528 fsl,pins = < 529 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 530 >; 531 }; 532 533 pinctrl_pwm4: pwm4grp { 534 fsl,pins = < 535 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 536 >; 537 }; 538 539 pinctrl_uart1: uart1grp { 540 fsl,pins = < 541 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 542 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 543 >; 544 }; 545 546 pinctrl_uart2: uart2grp { 547 fsl,pins = < 548 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 549 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 550 >; 551 }; 552 553 pinctrl_uart3: uart3grp { 554 fsl,pins = < 555 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 556 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 557 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 558 MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 559 >; 560 }; 561 562 pinctrl_uart4: uart4grp { 563 fsl,pins = < 564 MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1 565 MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1 566 MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1 567 MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1 568 >; 569 }; 570 571 pinctrl_uart5: uart5grp { 572 fsl,pins = < 573 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 574 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 575 >; 576 }; 577 578 pinctrl_usbotg: usbotggrp { 579 fsl,pins = < 580 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 581 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */ 582 MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x1b0b0 /* OC */ 583 >; 584 }; 585 586 pinctrl_usdhc3: usdhc3grp { 587 fsl,pins = < 588 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059 589 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059 590 MX6QDL_PAD_SD3_RST__SD3_RESET 0x10059 591 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059 592 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059 593 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059 594 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059 595 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059 596 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059 597 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059 598 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059 599 >; 600 }; 601 602 pinctrl_usdhc3_100mhz: usdhc3grp100mhz { 603 fsl,pins = < 604 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9 605 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9 606 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100b9 607 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9 608 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9 609 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9 610 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9 611 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170b9 612 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170b9 613 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170b9 614 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170b9 615 >; 616 }; 617 618 pinctrl_usdhc3_200mhz: usdhc3grp200mhz { 619 fsl,pins = < 620 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9 621 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9 622 MX6QDL_PAD_SD3_RST__SD3_RESET 0x100f9 623 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9 624 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9 625 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9 626 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9 627 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x170f9 628 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x170f9 629 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x170f9 630 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x170f9 631 >; 632 }; 633 634 pinctrl_wdog: wdoggrp { 635 fsl,pins = < 636 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0 637 >; 638 }; 639}; 640