1// SPDX-License-Identifier: GPL-2.0 2// 3// Copyright 2013 Freescale Semiconductor, Inc. 4 5#include <dt-bindings/interrupt-controller/irq.h> 6#include "imx6sl-pinfunc.h" 7#include <dt-bindings/clock/imx6sl-clock.h> 8 9/ { 10 #address-cells = <1>; 11 #size-cells = <1>; 12 /* 13 * The decompressor and also some bootloaders rely on a 14 * pre-existing /chosen node to be available to insert the 15 * command line and merge other ATAGS info. 16 */ 17 chosen {}; 18 19 aliases { 20 ethernet0 = &fec; 21 gpio0 = &gpio1; 22 gpio1 = &gpio2; 23 gpio2 = &gpio3; 24 gpio3 = &gpio4; 25 gpio4 = &gpio5; 26 serial0 = &uart1; 27 serial1 = &uart2; 28 serial2 = &uart3; 29 serial3 = &uart4; 30 serial4 = &uart5; 31 spi0 = &ecspi1; 32 spi1 = &ecspi2; 33 spi2 = &ecspi3; 34 spi3 = &ecspi4; 35 usbphy0 = &usbphy1; 36 usbphy1 = &usbphy2; 37 }; 38 39 cpus { 40 #address-cells = <1>; 41 #size-cells = <0>; 42 43 cpu@0 { 44 compatible = "arm,cortex-a9"; 45 device_type = "cpu"; 46 reg = <0x0>; 47 next-level-cache = <&L2>; 48 operating-points = < 49 /* kHz uV */ 50 996000 1275000 51 792000 1175000 52 396000 975000 53 >; 54 fsl,soc-operating-points = < 55 /* ARM kHz SOC-PU uV */ 56 996000 1225000 57 792000 1175000 58 396000 1175000 59 >; 60 clock-latency = <61036>; /* two CLK32 periods */ 61 #cooling-cells = <2>; 62 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>, 63 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>, 64 <&clks IMX6SL_CLK_PLL1_SYS>; 65 clock-names = "arm", "pll2_pfd2_396m", "step", 66 "pll1_sw", "pll1_sys"; 67 arm-supply = <®_arm>; 68 pu-supply = <®_pu>; 69 soc-supply = <®_soc>; 70 }; 71 }; 72 73 intc: interrupt-controller@a01000 { 74 compatible = "arm,cortex-a9-gic"; 75 #interrupt-cells = <3>; 76 interrupt-controller; 77 reg = <0x00a01000 0x1000>, 78 <0x00a00100 0x100>; 79 interrupt-parent = <&intc>; 80 }; 81 82 clocks { 83 ckil { 84 compatible = "fixed-clock"; 85 #clock-cells = <0>; 86 clock-frequency = <32768>; 87 }; 88 89 osc { 90 compatible = "fixed-clock"; 91 #clock-cells = <0>; 92 clock-frequency = <24000000>; 93 }; 94 }; 95 96 tempmon: tempmon { 97 compatible = "fsl,imx6q-tempmon"; 98 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>; 99 interrupt-parent = <&gpc>; 100 fsl,tempmon = <&anatop>; 101 fsl,tempmon-data = <&ocotp>; 102 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>; 103 }; 104 105 pmu { 106 compatible = "arm,cortex-a9-pmu"; 107 interrupt-parent = <&gpc>; 108 interrupts = <0 94 IRQ_TYPE_LEVEL_HIGH>; 109 }; 110 111 soc { 112 #address-cells = <1>; 113 #size-cells = <1>; 114 compatible = "simple-bus"; 115 interrupt-parent = <&gpc>; 116 ranges; 117 118 ocram: sram@900000 { 119 compatible = "mmio-sram"; 120 reg = <0x00900000 0x20000>; 121 clocks = <&clks IMX6SL_CLK_OCRAM>; 122 }; 123 124 L2: l2-cache@a02000 { 125 compatible = "arm,pl310-cache"; 126 reg = <0x00a02000 0x1000>; 127 interrupts = <0 92 IRQ_TYPE_LEVEL_HIGH>; 128 cache-unified; 129 cache-level = <2>; 130 arm,tag-latency = <4 2 3>; 131 arm,data-latency = <4 2 3>; 132 }; 133 134 aips1: aips-bus@2000000 { 135 compatible = "fsl,aips-bus", "simple-bus"; 136 #address-cells = <1>; 137 #size-cells = <1>; 138 reg = <0x02000000 0x100000>; 139 ranges; 140 141 spba: spba-bus@2000000 { 142 compatible = "fsl,spba-bus", "simple-bus"; 143 #address-cells = <1>; 144 #size-cells = <1>; 145 reg = <0x02000000 0x40000>; 146 ranges; 147 148 spdif: spdif@2004000 { 149 compatible = "fsl,imx6sl-spdif", 150 "fsl,imx35-spdif"; 151 reg = <0x02004000 0x4000>; 152 interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>; 153 dmas = <&sdma 14 18 0>, 154 <&sdma 15 18 0>; 155 dma-names = "rx", "tx"; 156 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>, 157 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>, 158 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>, 159 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>, 160 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>; 161 clock-names = "core", "rxtx0", 162 "rxtx1", "rxtx2", 163 "rxtx3", "rxtx4", 164 "rxtx5", "rxtx6", 165 "rxtx7", "spba"; 166 status = "disabled"; 167 }; 168 169 ecspi1: ecspi@2008000 { 170 #address-cells = <1>; 171 #size-cells = <0>; 172 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; 173 reg = <0x02008000 0x4000>; 174 interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>; 175 clocks = <&clks IMX6SL_CLK_ECSPI1>, 176 <&clks IMX6SL_CLK_ECSPI1>; 177 clock-names = "ipg", "per"; 178 status = "disabled"; 179 }; 180 181 ecspi2: ecspi@200c000 { 182 #address-cells = <1>; 183 #size-cells = <0>; 184 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; 185 reg = <0x0200c000 0x4000>; 186 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&clks IMX6SL_CLK_ECSPI2>, 188 <&clks IMX6SL_CLK_ECSPI2>; 189 clock-names = "ipg", "per"; 190 status = "disabled"; 191 }; 192 193 ecspi3: ecspi@2010000 { 194 #address-cells = <1>; 195 #size-cells = <0>; 196 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; 197 reg = <0x02010000 0x4000>; 198 interrupts = <0 33 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&clks IMX6SL_CLK_ECSPI3>, 200 <&clks IMX6SL_CLK_ECSPI3>; 201 clock-names = "ipg", "per"; 202 status = "disabled"; 203 }; 204 205 ecspi4: ecspi@2014000 { 206 #address-cells = <1>; 207 #size-cells = <0>; 208 compatible = "fsl,imx6sl-ecspi", "fsl,imx51-ecspi"; 209 reg = <0x02014000 0x4000>; 210 interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; 211 clocks = <&clks IMX6SL_CLK_ECSPI4>, 212 <&clks IMX6SL_CLK_ECSPI4>; 213 clock-names = "ipg", "per"; 214 status = "disabled"; 215 }; 216 217 uart5: serial@2018000 { 218 compatible = "fsl,imx6sl-uart", 219 "fsl,imx6q-uart", "fsl,imx21-uart"; 220 reg = <0x02018000 0x4000>; 221 interrupts = <0 30 IRQ_TYPE_LEVEL_HIGH>; 222 clocks = <&clks IMX6SL_CLK_UART>, 223 <&clks IMX6SL_CLK_UART_SERIAL>; 224 clock-names = "ipg", "per"; 225 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>; 226 dma-names = "rx", "tx"; 227 status = "disabled"; 228 }; 229 230 uart1: serial@2020000 { 231 compatible = "fsl,imx6sl-uart", 232 "fsl,imx6q-uart", "fsl,imx21-uart"; 233 reg = <0x02020000 0x4000>; 234 interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>; 235 clocks = <&clks IMX6SL_CLK_UART>, 236 <&clks IMX6SL_CLK_UART_SERIAL>; 237 clock-names = "ipg", "per"; 238 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>; 239 dma-names = "rx", "tx"; 240 status = "disabled"; 241 }; 242 243 uart2: serial@2024000 { 244 compatible = "fsl,imx6sl-uart", 245 "fsl,imx6q-uart", "fsl,imx21-uart"; 246 reg = <0x02024000 0x4000>; 247 interrupts = <0 27 IRQ_TYPE_LEVEL_HIGH>; 248 clocks = <&clks IMX6SL_CLK_UART>, 249 <&clks IMX6SL_CLK_UART_SERIAL>; 250 clock-names = "ipg", "per"; 251 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>; 252 dma-names = "rx", "tx"; 253 status = "disabled"; 254 }; 255 256 ssi1: ssi@2028000 { 257 #sound-dai-cells = <0>; 258 compatible = "fsl,imx6sl-ssi", 259 "fsl,imx51-ssi"; 260 reg = <0x02028000 0x4000>; 261 interrupts = <0 46 IRQ_TYPE_LEVEL_HIGH>; 262 clocks = <&clks IMX6SL_CLK_SSI1_IPG>, 263 <&clks IMX6SL_CLK_SSI1>; 264 clock-names = "ipg", "baud"; 265 dmas = <&sdma 37 1 0>, 266 <&sdma 38 1 0>; 267 dma-names = "rx", "tx"; 268 fsl,fifo-depth = <15>; 269 status = "disabled"; 270 }; 271 272 ssi2: ssi@202c000 { 273 #sound-dai-cells = <0>; 274 compatible = "fsl,imx6sl-ssi", 275 "fsl,imx51-ssi"; 276 reg = <0x0202c000 0x4000>; 277 interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>; 278 clocks = <&clks IMX6SL_CLK_SSI2_IPG>, 279 <&clks IMX6SL_CLK_SSI2>; 280 clock-names = "ipg", "baud"; 281 dmas = <&sdma 41 1 0>, 282 <&sdma 42 1 0>; 283 dma-names = "rx", "tx"; 284 fsl,fifo-depth = <15>; 285 status = "disabled"; 286 }; 287 288 ssi3: ssi@2030000 { 289 #sound-dai-cells = <0>; 290 compatible = "fsl,imx6sl-ssi", 291 "fsl,imx51-ssi"; 292 reg = <0x02030000 0x4000>; 293 interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>; 294 clocks = <&clks IMX6SL_CLK_SSI3_IPG>, 295 <&clks IMX6SL_CLK_SSI3>; 296 clock-names = "ipg", "baud"; 297 dmas = <&sdma 45 1 0>, 298 <&sdma 46 1 0>; 299 dma-names = "rx", "tx"; 300 fsl,fifo-depth = <15>; 301 status = "disabled"; 302 }; 303 304 uart3: serial@2034000 { 305 compatible = "fsl,imx6sl-uart", 306 "fsl,imx6q-uart", "fsl,imx21-uart"; 307 reg = <0x02034000 0x4000>; 308 interrupts = <0 28 IRQ_TYPE_LEVEL_HIGH>; 309 clocks = <&clks IMX6SL_CLK_UART>, 310 <&clks IMX6SL_CLK_UART_SERIAL>; 311 clock-names = "ipg", "per"; 312 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>; 313 dma-names = "rx", "tx"; 314 status = "disabled"; 315 }; 316 317 uart4: serial@2038000 { 318 compatible = "fsl,imx6sl-uart", 319 "fsl,imx6q-uart", "fsl,imx21-uart"; 320 reg = <0x02038000 0x4000>; 321 interrupts = <0 29 IRQ_TYPE_LEVEL_HIGH>; 322 clocks = <&clks IMX6SL_CLK_UART>, 323 <&clks IMX6SL_CLK_UART_SERIAL>; 324 clock-names = "ipg", "per"; 325 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>; 326 dma-names = "rx", "tx"; 327 status = "disabled"; 328 }; 329 }; 330 331 pwm1: pwm@2080000 { 332 #pwm-cells = <2>; 333 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; 334 reg = <0x02080000 0x4000>; 335 interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&clks IMX6SL_CLK_PWM1>, 337 <&clks IMX6SL_CLK_PWM1>; 338 clock-names = "ipg", "per"; 339 }; 340 341 pwm2: pwm@2084000 { 342 #pwm-cells = <2>; 343 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; 344 reg = <0x02084000 0x4000>; 345 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; 346 clocks = <&clks IMX6SL_CLK_PWM2>, 347 <&clks IMX6SL_CLK_PWM2>; 348 clock-names = "ipg", "per"; 349 }; 350 351 pwm3: pwm@2088000 { 352 #pwm-cells = <2>; 353 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; 354 reg = <0x02088000 0x4000>; 355 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; 356 clocks = <&clks IMX6SL_CLK_PWM3>, 357 <&clks IMX6SL_CLK_PWM3>; 358 clock-names = "ipg", "per"; 359 }; 360 361 pwm4: pwm@208c000 { 362 #pwm-cells = <2>; 363 compatible = "fsl,imx6sl-pwm", "fsl,imx27-pwm"; 364 reg = <0x0208c000 0x4000>; 365 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 366 clocks = <&clks IMX6SL_CLK_PWM4>, 367 <&clks IMX6SL_CLK_PWM4>; 368 clock-names = "ipg", "per"; 369 }; 370 371 gpt: gpt@2098000 { 372 compatible = "fsl,imx6sl-gpt"; 373 reg = <0x02098000 0x4000>; 374 interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&clks IMX6SL_CLK_GPT>, 376 <&clks IMX6SL_CLK_GPT_SERIAL>; 377 clock-names = "ipg", "per"; 378 }; 379 380 gpio1: gpio@209c000 { 381 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; 382 reg = <0x0209c000 0x4000>; 383 interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>, 384 <0 67 IRQ_TYPE_LEVEL_HIGH>; 385 gpio-controller; 386 #gpio-cells = <2>; 387 interrupt-controller; 388 #interrupt-cells = <2>; 389 gpio-ranges = <&iomuxc 0 22 1>, <&iomuxc 1 20 2>, 390 <&iomuxc 3 23 1>, <&iomuxc 4 25 1>, 391 <&iomuxc 5 24 1>, <&iomuxc 6 19 1>, 392 <&iomuxc 7 36 2>, <&iomuxc 9 44 8>, 393 <&iomuxc 17 38 6>, <&iomuxc 23 68 4>, 394 <&iomuxc 27 64 4>, <&iomuxc 31 52 1>; 395 }; 396 397 gpio2: gpio@20a0000 { 398 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; 399 reg = <0x020a0000 0x4000>; 400 interrupts = <0 68 IRQ_TYPE_LEVEL_HIGH>, 401 <0 69 IRQ_TYPE_LEVEL_HIGH>; 402 gpio-controller; 403 #gpio-cells = <2>; 404 interrupt-controller; 405 #interrupt-cells = <2>; 406 gpio-ranges = <&iomuxc 0 53 3>, <&iomuxc 3 72 2>, 407 <&iomuxc 5 34 2>, <&iomuxc 7 57 4>, 408 <&iomuxc 11 56 1>, <&iomuxc 12 61 3>, 409 <&iomuxc 15 107 1>, <&iomuxc 16 132 2>, 410 <&iomuxc 18 135 1>, <&iomuxc 19 134 1>, 411 <&iomuxc 20 108 2>, <&iomuxc 22 120 1>, 412 <&iomuxc 23 125 7>, <&iomuxc 30 110 2>; 413 }; 414 415 gpio3: gpio@20a4000 { 416 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; 417 reg = <0x020a4000 0x4000>; 418 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>, 419 <0 71 IRQ_TYPE_LEVEL_HIGH>; 420 gpio-controller; 421 #gpio-cells = <2>; 422 interrupt-controller; 423 #interrupt-cells = <2>; 424 gpio-ranges = <&iomuxc 0 112 8>, <&iomuxc 8 121 4>, 425 <&iomuxc 12 97 4>, <&iomuxc 16 166 3>, 426 <&iomuxc 19 85 2>, <&iomuxc 21 137 2>, 427 <&iomuxc 23 136 1>, <&iomuxc 24 91 1>, 428 <&iomuxc 25 99 1>, <&iomuxc 26 92 1>, 429 <&iomuxc 27 100 1>, <&iomuxc 28 93 1>, 430 <&iomuxc 29 101 1>, <&iomuxc 30 94 1>, 431 <&iomuxc 31 102 1>; 432 }; 433 434 gpio4: gpio@20a8000 { 435 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; 436 reg = <0x020a8000 0x4000>; 437 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>, 438 <0 73 IRQ_TYPE_LEVEL_HIGH>; 439 gpio-controller; 440 #gpio-cells = <2>; 441 interrupt-controller; 442 #interrupt-cells = <2>; 443 gpio-ranges = <&iomuxc 0 95 1>, <&iomuxc 1 103 1>, 444 <&iomuxc 2 96 1>, <&iomuxc 3 104 1>, 445 <&iomuxc 4 97 1>, <&iomuxc 5 105 1>, 446 <&iomuxc 6 98 1>, <&iomuxc 7 106 1>, 447 <&iomuxc 8 28 1>, <&iomuxc 9 27 1>, 448 <&iomuxc 10 26 1>, <&iomuxc 11 29 1>, 449 <&iomuxc 12 32 1>, <&iomuxc 13 31 1>, 450 <&iomuxc 14 30 1>, <&iomuxc 15 33 1>, 451 <&iomuxc 16 84 1>, <&iomuxc 17 79 2>, 452 <&iomuxc 19 78 1>, <&iomuxc 20 76 1>, 453 <&iomuxc 21 81 2>, <&iomuxc 23 75 1>, 454 <&iomuxc 24 83 1>, <&iomuxc 25 74 1>, 455 <&iomuxc 26 77 1>, <&iomuxc 27 159 1>, 456 <&iomuxc 28 154 1>, <&iomuxc 29 157 1>, 457 <&iomuxc 30 152 1>, <&iomuxc 31 156 1>; 458 }; 459 460 gpio5: gpio@20ac000 { 461 compatible = "fsl,imx6sl-gpio", "fsl,imx35-gpio"; 462 reg = <0x020ac000 0x4000>; 463 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>, 464 <0 75 IRQ_TYPE_LEVEL_HIGH>; 465 gpio-controller; 466 #gpio-cells = <2>; 467 interrupt-controller; 468 #interrupt-cells = <2>; 469 gpio-ranges = <&iomuxc 0 158 1>, <&iomuxc 1 151 1>, 470 <&iomuxc 2 155 1>, <&iomuxc 3 153 1>, 471 <&iomuxc 4 150 1>, <&iomuxc 5 149 1>, 472 <&iomuxc 6 144 1>, <&iomuxc 7 147 1>, 473 <&iomuxc 8 142 1>, <&iomuxc 9 146 1>, 474 <&iomuxc 10 148 1>, <&iomuxc 11 141 1>, 475 <&iomuxc 12 145 1>, <&iomuxc 13 143 1>, 476 <&iomuxc 14 140 1>, <&iomuxc 15 139 1>, 477 <&iomuxc 16 164 2>, <&iomuxc 18 160 1>, 478 <&iomuxc 19 162 1>, <&iomuxc 20 163 1>, 479 <&iomuxc 21 161 1>; 480 }; 481 482 kpp: kpp@20b8000 { 483 compatible = "fsl,imx6sl-kpp", "fsl,imx21-kpp"; 484 reg = <0x020b8000 0x4000>; 485 interrupts = <0 82 IRQ_TYPE_LEVEL_HIGH>; 486 clocks = <&clks IMX6SL_CLK_DUMMY>; 487 status = "disabled"; 488 }; 489 490 wdog1: wdog@20bc000 { 491 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; 492 reg = <0x020bc000 0x4000>; 493 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&clks IMX6SL_CLK_DUMMY>; 495 }; 496 497 wdog2: wdog@20c0000 { 498 compatible = "fsl,imx6sl-wdt", "fsl,imx21-wdt"; 499 reg = <0x020c0000 0x4000>; 500 interrupts = <0 81 IRQ_TYPE_LEVEL_HIGH>; 501 clocks = <&clks IMX6SL_CLK_DUMMY>; 502 status = "disabled"; 503 }; 504 505 clks: ccm@20c4000 { 506 compatible = "fsl,imx6sl-ccm"; 507 reg = <0x020c4000 0x4000>; 508 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>, 509 <0 88 IRQ_TYPE_LEVEL_HIGH>; 510 #clock-cells = <1>; 511 }; 512 513 anatop: anatop@20c8000 { 514 compatible = "fsl,imx6sl-anatop", 515 "fsl,imx6q-anatop", 516 "syscon", "simple-bus"; 517 reg = <0x020c8000 0x1000>; 518 interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>, 519 <0 54 IRQ_TYPE_LEVEL_HIGH>, 520 <0 127 IRQ_TYPE_LEVEL_HIGH>; 521 522 regulator-1p1 { 523 compatible = "fsl,anatop-regulator"; 524 regulator-name = "vdd1p1"; 525 regulator-min-microvolt = <1000000>; 526 regulator-max-microvolt = <1200000>; 527 regulator-always-on; 528 anatop-reg-offset = <0x110>; 529 anatop-vol-bit-shift = <8>; 530 anatop-vol-bit-width = <5>; 531 anatop-min-bit-val = <4>; 532 anatop-min-voltage = <800000>; 533 anatop-max-voltage = <1375000>; 534 anatop-enable-bit = <0>; 535 }; 536 537 regulator-3p0 { 538 compatible = "fsl,anatop-regulator"; 539 regulator-name = "vdd3p0"; 540 regulator-min-microvolt = <2800000>; 541 regulator-max-microvolt = <3150000>; 542 regulator-always-on; 543 anatop-reg-offset = <0x120>; 544 anatop-vol-bit-shift = <8>; 545 anatop-vol-bit-width = <5>; 546 anatop-min-bit-val = <0>; 547 anatop-min-voltage = <2625000>; 548 anatop-max-voltage = <3400000>; 549 anatop-enable-bit = <0>; 550 }; 551 552 regulator-2p5 { 553 compatible = "fsl,anatop-regulator"; 554 regulator-name = "vdd2p5"; 555 regulator-min-microvolt = <2250000>; 556 regulator-max-microvolt = <2750000>; 557 regulator-always-on; 558 anatop-reg-offset = <0x130>; 559 anatop-vol-bit-shift = <8>; 560 anatop-vol-bit-width = <5>; 561 anatop-min-bit-val = <0>; 562 anatop-min-voltage = <2100000>; 563 anatop-max-voltage = <2850000>; 564 anatop-enable-bit = <0>; 565 }; 566 567 reg_arm: regulator-vddcore { 568 compatible = "fsl,anatop-regulator"; 569 regulator-name = "vddarm"; 570 regulator-min-microvolt = <725000>; 571 regulator-max-microvolt = <1450000>; 572 regulator-always-on; 573 anatop-reg-offset = <0x140>; 574 anatop-vol-bit-shift = <0>; 575 anatop-vol-bit-width = <5>; 576 anatop-delay-reg-offset = <0x170>; 577 anatop-delay-bit-shift = <24>; 578 anatop-delay-bit-width = <2>; 579 anatop-min-bit-val = <1>; 580 anatop-min-voltage = <725000>; 581 anatop-max-voltage = <1450000>; 582 }; 583 584 reg_pu: regulator-vddpu { 585 compatible = "fsl,anatop-regulator"; 586 regulator-name = "vddpu"; 587 regulator-min-microvolt = <725000>; 588 regulator-max-microvolt = <1450000>; 589 regulator-always-on; 590 anatop-reg-offset = <0x140>; 591 anatop-vol-bit-shift = <9>; 592 anatop-vol-bit-width = <5>; 593 anatop-delay-reg-offset = <0x170>; 594 anatop-delay-bit-shift = <26>; 595 anatop-delay-bit-width = <2>; 596 anatop-min-bit-val = <1>; 597 anatop-min-voltage = <725000>; 598 anatop-max-voltage = <1450000>; 599 }; 600 601 reg_soc: regulator-vddsoc { 602 compatible = "fsl,anatop-regulator"; 603 regulator-name = "vddsoc"; 604 regulator-min-microvolt = <725000>; 605 regulator-max-microvolt = <1450000>; 606 regulator-always-on; 607 anatop-reg-offset = <0x140>; 608 anatop-vol-bit-shift = <18>; 609 anatop-vol-bit-width = <5>; 610 anatop-delay-reg-offset = <0x170>; 611 anatop-delay-bit-shift = <28>; 612 anatop-delay-bit-width = <2>; 613 anatop-min-bit-val = <1>; 614 anatop-min-voltage = <725000>; 615 anatop-max-voltage = <1450000>; 616 }; 617 }; 618 619 usbphy1: usbphy@20c9000 { 620 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; 621 reg = <0x020c9000 0x1000>; 622 interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; 623 clocks = <&clks IMX6SL_CLK_USBPHY1>; 624 fsl,anatop = <&anatop>; 625 }; 626 627 usbphy2: usbphy@20ca000 { 628 compatible = "fsl,imx6sl-usbphy", "fsl,imx23-usbphy"; 629 reg = <0x020ca000 0x1000>; 630 interrupts = <0 45 IRQ_TYPE_LEVEL_HIGH>; 631 clocks = <&clks IMX6SL_CLK_USBPHY2>; 632 fsl,anatop = <&anatop>; 633 }; 634 635 snvs: snvs@20cc000 { 636 compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; 637 reg = <0x020cc000 0x4000>; 638 639 snvs_rtc: snvs-rtc-lp { 640 compatible = "fsl,sec-v4.0-mon-rtc-lp"; 641 regmap = <&snvs>; 642 offset = <0x34>; 643 interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>, 644 <0 20 IRQ_TYPE_LEVEL_HIGH>; 645 }; 646 647 snvs_poweroff: snvs-poweroff { 648 compatible = "syscon-poweroff"; 649 regmap = <&snvs>; 650 offset = <0x38>; 651 value = <0x60>; 652 mask = <0x60>; 653 status = "disabled"; 654 }; 655 }; 656 657 epit1: epit@20d0000 { 658 reg = <0x020d0000 0x4000>; 659 interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; 660 }; 661 662 epit2: epit@20d4000 { 663 reg = <0x020d4000 0x4000>; 664 interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; 665 }; 666 667 src: src@20d8000 { 668 compatible = "fsl,imx6sl-src", "fsl,imx51-src"; 669 reg = <0x020d8000 0x4000>; 670 interrupts = <0 91 IRQ_TYPE_LEVEL_HIGH>, 671 <0 96 IRQ_TYPE_LEVEL_HIGH>; 672 #reset-cells = <1>; 673 }; 674 675 gpc: gpc@20dc000 { 676 compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc"; 677 reg = <0x020dc000 0x4000>; 678 interrupt-controller; 679 #interrupt-cells = <3>; 680 interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>; 681 interrupt-parent = <&intc>; 682 clocks = <&clks IMX6SL_CLK_IPG>; 683 clock-names = "ipg"; 684 685 pgc { 686 #address-cells = <1>; 687 #size-cells = <0>; 688 689 power-domain@0 { 690 reg = <0>; 691 #power-domain-cells = <0>; 692 }; 693 694 pd_pu: power-domain@1 { 695 reg = <1>; 696 #power-domain-cells = <0>; 697 power-supply = <®_pu>; 698 clocks = <&clks IMX6SL_CLK_GPU2D_OVG>, 699 <&clks IMX6SL_CLK_GPU2D_PODF>; 700 }; 701 702 pd_disp: power-domain@2 { 703 reg = <2>; 704 #power-domain-cells = <0>; 705 clocks = <&clks IMX6SL_CLK_LCDIF_AXI>, 706 <&clks IMX6SL_CLK_LCDIF_PIX>, 707 <&clks IMX6SL_CLK_EPDC_AXI>, 708 <&clks IMX6SL_CLK_EPDC_PIX>, 709 <&clks IMX6SL_CLK_PXP_AXI>; 710 }; 711 }; 712 }; 713 714 gpr: iomuxc-gpr@20e0000 { 715 compatible = "fsl,imx6sl-iomuxc-gpr", 716 "fsl,imx6q-iomuxc-gpr", "syscon"; 717 reg = <0x020e0000 0x38>; 718 }; 719 720 iomuxc: iomuxc@20e0000 { 721 compatible = "fsl,imx6sl-iomuxc"; 722 reg = <0x020e0000 0x4000>; 723 }; 724 725 csi: csi@20e4000 { 726 reg = <0x020e4000 0x4000>; 727 interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>; 728 }; 729 730 spdc: spdc@20e8000 { 731 reg = <0x020e8000 0x4000>; 732 interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>; 733 }; 734 735 sdma: sdma@20ec000 { 736 compatible = "fsl,imx6sl-sdma", "fsl,imx6q-sdma"; 737 reg = <0x020ec000 0x4000>; 738 interrupts = <0 2 IRQ_TYPE_LEVEL_HIGH>; 739 clocks = <&clks IMX6SL_CLK_SDMA>, 740 <&clks IMX6SL_CLK_AHB>; 741 clock-names = "ipg", "ahb"; 742 #dma-cells = <3>; 743 /* imx6sl reuses imx6q sdma firmware */ 744 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; 745 }; 746 747 pxp: pxp@20f0000 { 748 reg = <0x020f0000 0x4000>; 749 interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; 750 }; 751 752 epdc: epdc@20f4000 { 753 reg = <0x020f4000 0x4000>; 754 interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; 755 }; 756 757 lcdif: lcdif@20f8000 { 758 compatible = "fsl,imx6sl-lcdif", "fsl,imx28-lcdif"; 759 reg = <0x020f8000 0x4000>; 760 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; 761 clocks = <&clks IMX6SL_CLK_LCDIF_PIX>, 762 <&clks IMX6SL_CLK_LCDIF_AXI>, 763 <&clks IMX6SL_CLK_DUMMY>; 764 clock-names = "pix", "axi", "disp_axi"; 765 status = "disabled"; 766 power-domains = <&pd_disp>; 767 }; 768 769 dcp: dcp@20fc000 { 770 compatible = "fsl,imx6sl-dcp", "fsl,imx28-dcp"; 771 reg = <0x020fc000 0x4000>; 772 interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>, 773 <0 100 IRQ_TYPE_LEVEL_HIGH>, 774 <0 101 IRQ_TYPE_LEVEL_HIGH>; 775 }; 776 }; 777 778 aips2: aips-bus@2100000 { 779 compatible = "fsl,aips-bus", "simple-bus"; 780 #address-cells = <1>; 781 #size-cells = <1>; 782 reg = <0x02100000 0x100000>; 783 ranges; 784 785 usbotg1: usb@2184000 { 786 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; 787 reg = <0x02184000 0x200>; 788 interrupts = <0 43 IRQ_TYPE_LEVEL_HIGH>; 789 clocks = <&clks IMX6SL_CLK_USBOH3>; 790 fsl,usbphy = <&usbphy1>; 791 fsl,usbmisc = <&usbmisc 0>; 792 ahb-burst-config = <0x0>; 793 tx-burst-size-dword = <0x10>; 794 rx-burst-size-dword = <0x10>; 795 status = "disabled"; 796 }; 797 798 usbotg2: usb@2184200 { 799 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; 800 reg = <0x02184200 0x200>; 801 interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>; 802 clocks = <&clks IMX6SL_CLK_USBOH3>; 803 fsl,usbphy = <&usbphy2>; 804 fsl,usbmisc = <&usbmisc 1>; 805 ahb-burst-config = <0x0>; 806 tx-burst-size-dword = <0x10>; 807 rx-burst-size-dword = <0x10>; 808 status = "disabled"; 809 }; 810 811 usbh: usb@2184400 { 812 compatible = "fsl,imx6sl-usb", "fsl,imx27-usb"; 813 reg = <0x02184400 0x200>; 814 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&clks IMX6SL_CLK_USBOH3>; 816 fsl,usbmisc = <&usbmisc 2>; 817 dr_mode = "host"; 818 ahb-burst-config = <0x0>; 819 tx-burst-size-dword = <0x10>; 820 rx-burst-size-dword = <0x10>; 821 status = "disabled"; 822 }; 823 824 usbmisc: usbmisc@2184800 { 825 #index-cells = <1>; 826 compatible = "fsl,imx6sl-usbmisc", "fsl,imx6q-usbmisc"; 827 reg = <0x02184800 0x200>; 828 clocks = <&clks IMX6SL_CLK_USBOH3>; 829 }; 830 831 fec: ethernet@2188000 { 832 compatible = "fsl,imx6sl-fec", "fsl,imx25-fec"; 833 reg = <0x02188000 0x4000>; 834 interrupts = <0 114 IRQ_TYPE_LEVEL_HIGH>; 835 clocks = <&clks IMX6SL_CLK_ENET>, 836 <&clks IMX6SL_CLK_ENET_REF>; 837 clock-names = "ipg", "ahb"; 838 status = "disabled"; 839 }; 840 841 usdhc1: usdhc@2190000 { 842 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; 843 reg = <0x02190000 0x4000>; 844 interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>; 845 clocks = <&clks IMX6SL_CLK_USDHC1>, 846 <&clks IMX6SL_CLK_USDHC1>, 847 <&clks IMX6SL_CLK_USDHC1>; 848 clock-names = "ipg", "ahb", "per"; 849 bus-width = <4>; 850 status = "disabled"; 851 }; 852 853 usdhc2: usdhc@2194000 { 854 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; 855 reg = <0x02194000 0x4000>; 856 interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>; 857 clocks = <&clks IMX6SL_CLK_USDHC2>, 858 <&clks IMX6SL_CLK_USDHC2>, 859 <&clks IMX6SL_CLK_USDHC2>; 860 clock-names = "ipg", "ahb", "per"; 861 bus-width = <4>; 862 status = "disabled"; 863 }; 864 865 usdhc3: usdhc@2198000 { 866 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; 867 reg = <0x02198000 0x4000>; 868 interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>; 869 clocks = <&clks IMX6SL_CLK_USDHC3>, 870 <&clks IMX6SL_CLK_USDHC3>, 871 <&clks IMX6SL_CLK_USDHC3>; 872 clock-names = "ipg", "ahb", "per"; 873 bus-width = <4>; 874 status = "disabled"; 875 }; 876 877 usdhc4: usdhc@219c000 { 878 compatible = "fsl,imx6sl-usdhc", "fsl,imx6q-usdhc"; 879 reg = <0x0219c000 0x4000>; 880 interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>; 881 clocks = <&clks IMX6SL_CLK_USDHC4>, 882 <&clks IMX6SL_CLK_USDHC4>, 883 <&clks IMX6SL_CLK_USDHC4>; 884 clock-names = "ipg", "ahb", "per"; 885 bus-width = <4>; 886 status = "disabled"; 887 }; 888 889 i2c1: i2c@21a0000 { 890 #address-cells = <1>; 891 #size-cells = <0>; 892 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; 893 reg = <0x021a0000 0x4000>; 894 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; 895 clocks = <&clks IMX6SL_CLK_I2C1>; 896 status = "disabled"; 897 }; 898 899 i2c2: i2c@21a4000 { 900 #address-cells = <1>; 901 #size-cells = <0>; 902 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; 903 reg = <0x021a4000 0x4000>; 904 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; 905 clocks = <&clks IMX6SL_CLK_I2C2>; 906 status = "disabled"; 907 }; 908 909 i2c3: i2c@21a8000 { 910 #address-cells = <1>; 911 #size-cells = <0>; 912 compatible = "fsl,imx6sl-i2c", "fsl,imx21-i2c"; 913 reg = <0x021a8000 0x4000>; 914 interrupts = <0 38 IRQ_TYPE_LEVEL_HIGH>; 915 clocks = <&clks IMX6SL_CLK_I2C3>; 916 status = "disabled"; 917 }; 918 919 mmdc: mmdc@21b0000 { 920 compatible = "fsl,imx6sl-mmdc", "fsl,imx6q-mmdc"; 921 reg = <0x021b0000 0x4000>; 922 }; 923 924 rngb: rngb@21b4000 { 925 compatible = "fsl,imx6sl-rngb", "fsl,imx25-rngb"; 926 reg = <0x021b4000 0x4000>; 927 interrupts = <0 5 IRQ_TYPE_LEVEL_HIGH>; 928 clocks = <&clks IMX6SL_CLK_DUMMY>; 929 }; 930 931 weim: weim@21b8000 { 932 #address-cells = <2>; 933 #size-cells = <1>; 934 reg = <0x021b8000 0x4000>; 935 interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>; 936 fsl,weim-cs-gpr = <&gpr>; 937 status = "disabled"; 938 }; 939 940 ocotp: ocotp@21bc000 { 941 compatible = "fsl,imx6sl-ocotp", "syscon"; 942 reg = <0x021bc000 0x4000>; 943 clocks = <&clks IMX6SL_CLK_OCOTP>; 944 }; 945 946 audmux: audmux@21d8000 { 947 compatible = "fsl,imx6sl-audmux", "fsl,imx31-audmux"; 948 reg = <0x021d8000 0x4000>; 949 status = "disabled"; 950 }; 951 }; 952 953 gpu_2d: gpu@2200000 { 954 compatible = "vivante,gc"; 955 reg = <0x02200000 0x4000>; 956 interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>; 957 clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, 958 <&clks IMX6SL_CLK_GPU2D_OVG>; 959 clock-names = "bus", "core"; 960 power-domains = <&pd_pu>; 961 }; 962 963 gpu_vg: gpu@2204000 { 964 compatible = "vivante,gc"; 965 reg = <0x02204000 0x4000>; 966 interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>; 967 clocks = <&clks IMX6SL_CLK_MMDC_ROOT>, 968 <&clks IMX6SL_CLK_GPU2D_OVG>; 969 clock-names = "bus", "core"; 970 power-domains = <&pd_pu>; 971 }; 972 }; 973}; 974