1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Copyright (C) 2015 Freescale Semiconductor, Inc. 4 5/dts-v1/; 6 7#include "imx7d.dtsi" 8 9/ { 10 model = "Freescale i.MX7 SabreSD Board"; 11 compatible = "fsl,imx7d-sdb", "fsl,imx7d"; 12 13 chosen { 14 stdout-path = &uart1; 15 }; 16 17 memory@80000000 { 18 device_type = "memory"; 19 reg = <0x80000000 0x80000000>; 20 }; 21 22 gpio-keys { 23 compatible = "gpio-keys"; 24 pinctrl-names = "default"; 25 pinctrl-0 = <&pinctrl_gpio_keys>; 26 27 volume-up { 28 label = "Volume Up"; 29 gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 30 linux,code = <KEY_VOLUMEUP>; 31 }; 32 33 volume-down { 34 label = "Volume Down"; 35 gpios = <&gpio5 10 GPIO_ACTIVE_LOW>; 36 linux,code = <KEY_VOLUMEDOWN>; 37 }; 38 }; 39 40 spi4 { 41 compatible = "spi-gpio"; 42 pinctrl-names = "default"; 43 pinctrl-0 = <&pinctrl_spi4>; 44 gpio-sck = <&gpio1 13 GPIO_ACTIVE_HIGH>; 45 gpio-mosi = <&gpio1 9 GPIO_ACTIVE_HIGH>; 46 cs-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; 47 num-chipselects = <1>; 48 #address-cells = <1>; 49 #size-cells = <0>; 50 51 extended_io: gpio-expander@0 { 52 compatible = "fairchild,74hc595"; 53 gpio-controller; 54 #gpio-cells = <2>; 55 reg = <0>; 56 registers-number = <1>; 57 spi-max-frequency = <100000>; 58 }; 59 }; 60 61 reg_usb_otg1_vbus: regulator-usb-otg1-vbus { 62 compatible = "regulator-fixed"; 63 regulator-name = "usb_otg1_vbus"; 64 regulator-min-microvolt = <5000000>; 65 regulator-max-microvolt = <5000000>; 66 gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>; 67 enable-active-high; 68 }; 69 70 reg_usb_otg2_vbus: regulator-usb-otg2-vbus { 71 compatible = "regulator-fixed"; 72 regulator-name = "usb_otg2_vbus"; 73 regulator-min-microvolt = <5000000>; 74 regulator-max-microvolt = <5000000>; 75 gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; 76 enable-active-high; 77 }; 78 79 reg_vref_1v8: regulator-vref-1v8 { 80 compatible = "regulator-fixed"; 81 regulator-name = "vref-1v8"; 82 regulator-min-microvolt = <1800000>; 83 regulator-max-microvolt = <1800000>; 84 }; 85 86 reg_brcm: regulator-brcm { 87 compatible = "regulator-fixed"; 88 gpio = <&gpio4 21 GPIO_ACTIVE_HIGH>; 89 enable-active-high; 90 regulator-name = "brcm_reg"; 91 pinctrl-names = "default"; 92 pinctrl-0 = <&pinctrl_brcm_reg>; 93 regulator-min-microvolt = <3300000>; 94 regulator-max-microvolt = <3300000>; 95 startup-delay-us = <200000>; 96 }; 97 98 reg_lcd_3v3: regulator-lcd-3v3 { 99 compatible = "regulator-fixed"; 100 regulator-name = "lcd-3v3"; 101 regulator-min-microvolt = <3300000>; 102 regulator-max-microvolt = <3300000>; 103 gpio = <&extended_io 7 GPIO_ACTIVE_LOW>; 104 }; 105 106 reg_can2_3v3: regulator-can2-3v3 { 107 compatible = "regulator-fixed"; 108 regulator-name = "can2-3v3"; 109 pinctrl-names = "default"; 110 pinctrl-0 = <&pinctrl_flexcan2_reg>; 111 regulator-min-microvolt = <3300000>; 112 regulator-max-microvolt = <3300000>; 113 gpio = <&gpio2 14 GPIO_ACTIVE_LOW>; 114 }; 115 116 backlight: backlight { 117 compatible = "pwm-backlight"; 118 pwms = <&pwm1 0 5000000 0>; 119 brightness-levels = <0 4 8 16 32 64 128 255>; 120 default-brightness-level = <6>; 121 status = "okay"; 122 }; 123 124 panel { 125 compatible = "innolux,at043tn24"; 126 backlight = <&backlight>; 127 power-supply = <®_lcd_3v3>; 128 129 port { 130 panel_in: endpoint { 131 remote-endpoint = <&display_out>; 132 }; 133 }; 134 }; 135}; 136 137&adc1 { 138 vref-supply = <®_vref_1v8>; 139 status = "okay"; 140}; 141 142&adc2 { 143 vref-supply = <®_vref_1v8>; 144 status = "okay"; 145}; 146 147&cpu0 { 148 cpu-supply = <&sw1a_reg>; 149}; 150 151&ecspi3 { 152 pinctrl-names = "default"; 153 pinctrl-0 = <&pinctrl_ecspi3>; 154 cs-gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; 155 status = "okay"; 156 157 tsc2046@0 { 158 compatible = "ti,tsc2046"; 159 reg = <0>; 160 spi-max-frequency = <1000000>; 161 pinctrl-names ="default"; 162 pinctrl-0 = <&pinctrl_tsc2046_pendown>; 163 interrupt-parent = <&gpio2>; 164 interrupts = <29 0>; 165 pendown-gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; 166 ti,x-min = /bits/ 16 <0>; 167 ti,x-max = /bits/ 16 <0>; 168 ti,y-min = /bits/ 16 <0>; 169 ti,y-max = /bits/ 16 <0>; 170 ti,pressure-max = /bits/ 16 <0>; 171 ti,x-plate-ohms = /bits/ 16 <400>; 172 wakeup-source; 173 }; 174}; 175 176&fec1 { 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_enet1>; 179 assigned-clocks = <&clks IMX7D_ENET1_TIME_ROOT_SRC>, 180 <&clks IMX7D_ENET1_TIME_ROOT_CLK>; 181 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 182 assigned-clock-rates = <0>, <100000000>; 183 phy-mode = "rgmii"; 184 phy-handle = <ðphy0>; 185 fsl,magic-packet; 186 phy-reset-gpios = <&extended_io 5 GPIO_ACTIVE_LOW>; 187 status = "okay"; 188 189 mdio { 190 #address-cells = <1>; 191 #size-cells = <0>; 192 193 ethphy0: ethernet-phy@0 { 194 reg = <0>; 195 }; 196 197 ethphy1: ethernet-phy@1 { 198 reg = <1>; 199 }; 200 }; 201}; 202 203&fec2 { 204 pinctrl-names = "default"; 205 pinctrl-0 = <&pinctrl_enet2>; 206 assigned-clocks = <&clks IMX7D_ENET2_TIME_ROOT_SRC>, 207 <&clks IMX7D_ENET2_TIME_ROOT_CLK>; 208 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; 209 assigned-clock-rates = <0>, <100000000>; 210 phy-mode = "rgmii"; 211 phy-handle = <ðphy1>; 212 fsl,magic-packet; 213 status = "okay"; 214}; 215 216&flexcan2 { 217 pinctrl-names = "default"; 218 pinctrl-0 = <&pinctrl_flexcan2>; 219 xceiver-supply = <®_can2_3v3>; 220 status = "okay"; 221}; 222 223&i2c1 { 224 pinctrl-names = "default"; 225 pinctrl-0 = <&pinctrl_i2c1>; 226 status = "okay"; 227 228 pmic: pfuze3000@8 { 229 compatible = "fsl,pfuze3000"; 230 reg = <0x08>; 231 232 regulators { 233 sw1a_reg: sw1a { 234 regulator-min-microvolt = <700000>; 235 regulator-max-microvolt = <1475000>; 236 regulator-boot-on; 237 regulator-always-on; 238 regulator-ramp-delay = <6250>; 239 }; 240 241 /* use sw1c_reg to align with pfuze100/pfuze200 */ 242 sw1c_reg: sw1b { 243 regulator-min-microvolt = <700000>; 244 regulator-max-microvolt = <1475000>; 245 regulator-boot-on; 246 regulator-always-on; 247 regulator-ramp-delay = <6250>; 248 }; 249 250 sw2_reg: sw2 { 251 regulator-min-microvolt = <1500000>; 252 regulator-max-microvolt = <1850000>; 253 regulator-boot-on; 254 regulator-always-on; 255 }; 256 257 sw3a_reg: sw3 { 258 regulator-min-microvolt = <900000>; 259 regulator-max-microvolt = <1650000>; 260 regulator-boot-on; 261 regulator-always-on; 262 }; 263 264 swbst_reg: swbst { 265 regulator-min-microvolt = <5000000>; 266 regulator-max-microvolt = <5150000>; 267 }; 268 269 snvs_reg: vsnvs { 270 regulator-min-microvolt = <1000000>; 271 regulator-max-microvolt = <3000000>; 272 regulator-boot-on; 273 regulator-always-on; 274 }; 275 276 vref_reg: vrefddr { 277 regulator-boot-on; 278 regulator-always-on; 279 }; 280 281 vgen1_reg: vldo1 { 282 regulator-min-microvolt = <1800000>; 283 regulator-max-microvolt = <3300000>; 284 regulator-always-on; 285 }; 286 287 vgen2_reg: vldo2 { 288 regulator-min-microvolt = <800000>; 289 regulator-max-microvolt = <1550000>; 290 }; 291 292 vgen3_reg: vccsd { 293 regulator-min-microvolt = <2850000>; 294 regulator-max-microvolt = <3300000>; 295 regulator-always-on; 296 }; 297 298 vgen4_reg: v33 { 299 regulator-min-microvolt = <2850000>; 300 regulator-max-microvolt = <3300000>; 301 regulator-always-on; 302 }; 303 304 vgen5_reg: vldo3 { 305 regulator-min-microvolt = <1800000>; 306 regulator-max-microvolt = <3300000>; 307 regulator-always-on; 308 }; 309 310 vgen6_reg: vldo4 { 311 regulator-min-microvolt = <2800000>; 312 regulator-max-microvolt = <2800000>; 313 regulator-always-on; 314 }; 315 }; 316 }; 317}; 318 319&i2c2 { 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pinctrl_i2c2>; 322 status = "okay"; 323 324 mpl3115@60 { 325 compatible = "fsl,mpl3115"; 326 reg = <0x60>; 327 }; 328}; 329 330&i2c3 { 331 pinctrl-names = "default"; 332 pinctrl-0 = <&pinctrl_i2c3>; 333 status = "okay"; 334}; 335 336&i2c4 { 337 pinctrl-names = "default"; 338 pinctrl-0 = <&pinctrl_i2c4>; 339 status = "okay"; 340 341 codec: wm8960@1a { 342 compatible = "wlf,wm8960"; 343 reg = <0x1a>; 344 clocks = <&clks IMX7D_AUDIO_MCLK_ROOT_CLK>; 345 clock-names = "mclk"; 346 wlf,shared-lrclk; 347 }; 348}; 349 350&lcdif { 351 pinctrl-names = "default"; 352 pinctrl-0 = <&pinctrl_lcdif>; 353 status = "okay"; 354 355 port { 356 display_out: endpoint { 357 remote-endpoint = <&panel_in>; 358 }; 359 }; 360}; 361 362&pcie { 363 reset-gpio = <&extended_io 1 GPIO_ACTIVE_LOW>; 364 status = "okay"; 365}; 366 367&uart1 { 368 pinctrl-names = "default"; 369 pinctrl-0 = <&pinctrl_uart1>; 370 assigned-clocks = <&clks IMX7D_UART1_ROOT_SRC>; 371 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 372 status = "okay"; 373}; 374 375&uart6 { 376 pinctrl-names = "default"; 377 pinctrl-0 = <&pinctrl_uart6>; 378 assigned-clocks = <&clks IMX7D_UART6_ROOT_SRC>; 379 assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; 380 uart-has-rtscts; 381 status = "okay"; 382}; 383 384&usbotg1 { 385 vbus-supply = <®_usb_otg1_vbus>; 386 status = "okay"; 387}; 388 389&usbotg2 { 390 vbus-supply = <®_usb_otg2_vbus>; 391 dr_mode = "host"; 392 status = "okay"; 393}; 394 395&usdhc1 { 396 pinctrl-names = "default"; 397 pinctrl-0 = <&pinctrl_usdhc1>; 398 cd-gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; 399 wp-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; 400 wakeup-source; 401 keep-power-in-suspend; 402 status = "okay"; 403}; 404 405&usdhc2 { 406 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 407 pinctrl-0 = <&pinctrl_usdhc2>; 408 pinctrl-1 = <&pinctrl_usdhc2_100mhz>; 409 pinctrl-2 = <&pinctrl_usdhc2_200mhz>; 410 wakeup-source; 411 keep-power-in-suspend; 412 non-removable; 413 vmmc-supply = <®_brcm>; 414 fsl,tuning-step = <2>; 415 status = "okay"; 416}; 417 418&usdhc3 { 419 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 420 pinctrl-0 = <&pinctrl_usdhc3>; 421 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 422 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 423 assigned-clocks = <&clks IMX7D_USDHC3_ROOT_CLK>; 424 assigned-clock-rates = <400000000>; 425 bus-width = <8>; 426 fsl,tuning-step = <2>; 427 non-removable; 428 status = "okay"; 429}; 430 431&wdog1 { 432 pinctrl-names = "default"; 433 pinctrl-0 = <&pinctrl_wdog>; 434 fsl,ext-reset-output; 435}; 436 437&iomuxc { 438 pinctrl-names = "default"; 439 pinctrl-0 = <&pinctrl_hog>; 440 441 imx7d-sdb { 442 pinctrl_brcm_reg: brcmreggrp { 443 fsl,pins = < 444 MX7D_PAD_ECSPI2_MOSI__GPIO4_IO21 0x14 445 >; 446 }; 447 448 pinctrl_ecspi3: ecspi3grp { 449 fsl,pins = < 450 MX7D_PAD_SAI2_TX_SYNC__ECSPI3_MISO 0x2 451 MX7D_PAD_SAI2_TX_BCLK__ECSPI3_MOSI 0x2 452 MX7D_PAD_SAI2_RX_DATA__ECSPI3_SCLK 0x2 453 MX7D_PAD_SD2_CD_B__GPIO5_IO9 0x59 454 >; 455 }; 456 457 pinctrl_enet1: enet1grp { 458 fsl,pins = < 459 MX7D_PAD_GPIO1_IO10__ENET1_MDIO 0x3 460 MX7D_PAD_GPIO1_IO11__ENET1_MDC 0x3 461 MX7D_PAD_ENET1_RGMII_TXC__ENET1_RGMII_TXC 0x1 462 MX7D_PAD_ENET1_RGMII_TD0__ENET1_RGMII_TD0 0x1 463 MX7D_PAD_ENET1_RGMII_TD1__ENET1_RGMII_TD1 0x1 464 MX7D_PAD_ENET1_RGMII_TD2__ENET1_RGMII_TD2 0x1 465 MX7D_PAD_ENET1_RGMII_TD3__ENET1_RGMII_TD3 0x1 466 MX7D_PAD_ENET1_RGMII_TX_CTL__ENET1_RGMII_TX_CTL 0x1 467 MX7D_PAD_ENET1_RGMII_RXC__ENET1_RGMII_RXC 0x1 468 MX7D_PAD_ENET1_RGMII_RD0__ENET1_RGMII_RD0 0x1 469 MX7D_PAD_ENET1_RGMII_RD1__ENET1_RGMII_RD1 0x1 470 MX7D_PAD_ENET1_RGMII_RD2__ENET1_RGMII_RD2 0x1 471 MX7D_PAD_ENET1_RGMII_RD3__ENET1_RGMII_RD3 0x1 472 MX7D_PAD_ENET1_RGMII_RX_CTL__ENET1_RGMII_RX_CTL 0x1 473 >; 474 }; 475 476 pinctrl_enet2: enet2grp { 477 fsl,pins = < 478 MX7D_PAD_EPDC_GDSP__ENET2_RGMII_TXC 0x1 479 MX7D_PAD_EPDC_SDCE2__ENET2_RGMII_TD0 0x1 480 MX7D_PAD_EPDC_SDCE3__ENET2_RGMII_TD1 0x1 481 MX7D_PAD_EPDC_GDCLK__ENET2_RGMII_TD2 0x1 482 MX7D_PAD_EPDC_GDOE__ENET2_RGMII_TD3 0x1 483 MX7D_PAD_EPDC_GDRL__ENET2_RGMII_TX_CTL 0x1 484 MX7D_PAD_EPDC_SDCE1__ENET2_RGMII_RXC 0x1 485 MX7D_PAD_EPDC_SDCLK__ENET2_RGMII_RD0 0x1 486 MX7D_PAD_EPDC_SDLE__ENET2_RGMII_RD1 0x1 487 MX7D_PAD_EPDC_SDOE__ENET2_RGMII_RD2 0x1 488 MX7D_PAD_EPDC_SDSHR__ENET2_RGMII_RD3 0x1 489 MX7D_PAD_EPDC_SDCE0__ENET2_RGMII_RX_CTL 0x1 490 >; 491 }; 492 493 pinctrl_flexcan2: flexcan2grp { 494 fsl,pins = < 495 MX7D_PAD_GPIO1_IO14__FLEXCAN2_RX 0x59 496 MX7D_PAD_GPIO1_IO15__FLEXCAN2_TX 0x59 497 >; 498 }; 499 500 pinctrl_flexcan2_reg: flexcan2reggrp { 501 fsl,pins = < 502 MX7D_PAD_EPDC_DATA14__GPIO2_IO14 0x59 /* CAN_STBY */ 503 >; 504 }; 505 506 pinctrl_gpio_keys: gpio_keysgrp { 507 fsl,pins = < 508 MX7D_PAD_SD2_RESET_B__GPIO5_IO11 0x59 509 MX7D_PAD_SD2_WP__GPIO5_IO10 0x59 510 >; 511 }; 512 513 pinctrl_hog: hoggrp { 514 fsl,pins = < 515 MX7D_PAD_UART3_CTS_B__GPIO4_IO7 0x14 516 MX7D_PAD_ECSPI2_SS0__GPIO4_IO23 0x34 /* bt reg on */ 517 >; 518 }; 519 520 pinctrl_i2c1: i2c1grp { 521 fsl,pins = < 522 MX7D_PAD_I2C1_SDA__I2C1_SDA 0x4000007f 523 MX7D_PAD_I2C1_SCL__I2C1_SCL 0x4000007f 524 >; 525 }; 526 527 pinctrl_i2c2: i2c2grp { 528 fsl,pins = < 529 MX7D_PAD_I2C2_SDA__I2C2_SDA 0x4000007f 530 MX7D_PAD_I2C2_SCL__I2C2_SCL 0x4000007f 531 >; 532 }; 533 534 pinctrl_i2c3: i2c3grp { 535 fsl,pins = < 536 MX7D_PAD_I2C3_SDA__I2C3_SDA 0x4000007f 537 MX7D_PAD_I2C3_SCL__I2C3_SCL 0x4000007f 538 >; 539 }; 540 541 pinctrl_i2c4: i2c4grp { 542 fsl,pins = < 543 MX7D_PAD_SAI1_RX_BCLK__I2C4_SDA 0x4000007f 544 MX7D_PAD_SAI1_RX_SYNC__I2C4_SCL 0x4000007f 545 >; 546 }; 547 548 pinctrl_lcdif: lcdifgrp { 549 fsl,pins = < 550 MX7D_PAD_LCD_DATA00__LCD_DATA0 0x79 551 MX7D_PAD_LCD_DATA01__LCD_DATA1 0x79 552 MX7D_PAD_LCD_DATA02__LCD_DATA2 0x79 553 MX7D_PAD_LCD_DATA03__LCD_DATA3 0x79 554 MX7D_PAD_LCD_DATA04__LCD_DATA4 0x79 555 MX7D_PAD_LCD_DATA05__LCD_DATA5 0x79 556 MX7D_PAD_LCD_DATA06__LCD_DATA6 0x79 557 MX7D_PAD_LCD_DATA07__LCD_DATA7 0x79 558 MX7D_PAD_LCD_DATA08__LCD_DATA8 0x79 559 MX7D_PAD_LCD_DATA09__LCD_DATA9 0x79 560 MX7D_PAD_LCD_DATA10__LCD_DATA10 0x79 561 MX7D_PAD_LCD_DATA11__LCD_DATA11 0x79 562 MX7D_PAD_LCD_DATA12__LCD_DATA12 0x79 563 MX7D_PAD_LCD_DATA13__LCD_DATA13 0x79 564 MX7D_PAD_LCD_DATA14__LCD_DATA14 0x79 565 MX7D_PAD_LCD_DATA15__LCD_DATA15 0x79 566 MX7D_PAD_LCD_DATA16__LCD_DATA16 0x79 567 MX7D_PAD_LCD_DATA17__LCD_DATA17 0x79 568 MX7D_PAD_LCD_DATA18__LCD_DATA18 0x79 569 MX7D_PAD_LCD_DATA19__LCD_DATA19 0x79 570 MX7D_PAD_LCD_DATA20__LCD_DATA20 0x79 571 MX7D_PAD_LCD_DATA21__LCD_DATA21 0x79 572 MX7D_PAD_LCD_DATA22__LCD_DATA22 0x79 573 MX7D_PAD_LCD_DATA23__LCD_DATA23 0x79 574 MX7D_PAD_LCD_CLK__LCD_CLK 0x79 575 MX7D_PAD_LCD_ENABLE__LCD_ENABLE 0x79 576 MX7D_PAD_LCD_VSYNC__LCD_VSYNC 0x79 577 MX7D_PAD_LCD_HSYNC__LCD_HSYNC 0x79 578 MX7D_PAD_LCD_RESET__LCD_RESET 0x79 579 >; 580 }; 581 582 pinctrl_spi4: spi4grp { 583 fsl,pins = < 584 MX7D_PAD_GPIO1_IO09__GPIO1_IO9 0x59 585 MX7D_PAD_GPIO1_IO12__GPIO1_IO12 0x59 586 MX7D_PAD_GPIO1_IO13__GPIO1_IO13 0x59 587 >; 588 }; 589 590 pinctrl_tsc2046_pendown: tsc2046_pendown { 591 fsl,pins = < 592 MX7D_PAD_EPDC_BDR1__GPIO2_IO29 0x59 593 >; 594 }; 595 596 pinctrl_uart1: uart1grp { 597 fsl,pins = < 598 MX7D_PAD_UART1_TX_DATA__UART1_DCE_TX 0x79 599 MX7D_PAD_UART1_RX_DATA__UART1_DCE_RX 0x79 600 >; 601 }; 602 603 pinctrl_uart5: uart5grp { 604 fsl,pins = < 605 MX7D_PAD_SAI1_TX_BCLK__UART5_DCE_TX 0x79 606 MX7D_PAD_SAI1_RX_DATA__UART5_DCE_RX 0x79 607 MX7D_PAD_SAI1_TX_SYNC__UART5_DCE_CTS 0x79 608 MX7D_PAD_SAI1_TX_DATA__UART5_DCE_RTS 0x79 609 >; 610 }; 611 612 pinctrl_uart6: uart6grp { 613 fsl,pins = < 614 MX7D_PAD_ECSPI1_MOSI__UART6_DCE_TX 0x79 615 MX7D_PAD_ECSPI1_SCLK__UART6_DCE_RX 0x79 616 MX7D_PAD_ECSPI1_SS0__UART6_DCE_CTS 0x79 617 MX7D_PAD_ECSPI1_MISO__UART6_DCE_RTS 0x79 618 >; 619 }; 620 621 pinctrl_usdhc1: usdhc1grp { 622 fsl,pins = < 623 MX7D_PAD_SD1_CMD__SD1_CMD 0x59 624 MX7D_PAD_SD1_CLK__SD1_CLK 0x19 625 MX7D_PAD_SD1_DATA0__SD1_DATA0 0x59 626 MX7D_PAD_SD1_DATA1__SD1_DATA1 0x59 627 MX7D_PAD_SD1_DATA2__SD1_DATA2 0x59 628 MX7D_PAD_SD1_DATA3__SD1_DATA3 0x59 629 MX7D_PAD_SD1_CD_B__GPIO5_IO0 0x59 /* CD */ 630 MX7D_PAD_SD1_WP__GPIO5_IO1 0x59 /* WP */ 631 MX7D_PAD_SD1_RESET_B__GPIO5_IO2 0x59 /* vmmc */ 632 >; 633 }; 634 635 pinctrl_usdhc2: usdhc2grp { 636 fsl,pins = < 637 MX7D_PAD_SD2_CMD__SD2_CMD 0x59 638 MX7D_PAD_SD2_CLK__SD2_CLK 0x19 639 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x59 640 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x59 641 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x59 642 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x59 643 >; 644 }; 645 646 pinctrl_usdhc2_100mhz: usdhc2grp_100mhz { 647 fsl,pins = < 648 MX7D_PAD_SD2_CMD__SD2_CMD 0x5a 649 MX7D_PAD_SD2_CLK__SD2_CLK 0x1a 650 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5a 651 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5a 652 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5a 653 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5a 654 >; 655 }; 656 657 pinctrl_usdhc2_200mhz: usdhc2grp_200mhz { 658 fsl,pins = < 659 MX7D_PAD_SD2_CMD__SD2_CMD 0x5b 660 MX7D_PAD_SD2_CLK__SD2_CLK 0x1b 661 MX7D_PAD_SD2_DATA0__SD2_DATA0 0x5b 662 MX7D_PAD_SD2_DATA1__SD2_DATA1 0x5b 663 MX7D_PAD_SD2_DATA2__SD2_DATA2 0x5b 664 MX7D_PAD_SD2_DATA3__SD2_DATA3 0x5b 665 >; 666 }; 667 668 669 pinctrl_usdhc3: usdhc3grp { 670 fsl,pins = < 671 MX7D_PAD_SD3_CMD__SD3_CMD 0x59 672 MX7D_PAD_SD3_CLK__SD3_CLK 0x19 673 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x59 674 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x59 675 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x59 676 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x59 677 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x59 678 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x59 679 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x59 680 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x59 681 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x19 682 >; 683 }; 684 685 pinctrl_usdhc3_100mhz: usdhc3grp_100mhz { 686 fsl,pins = < 687 MX7D_PAD_SD3_CMD__SD3_CMD 0x5a 688 MX7D_PAD_SD3_CLK__SD3_CLK 0x1a 689 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5a 690 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5a 691 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5a 692 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5a 693 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5a 694 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5a 695 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5a 696 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5a 697 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1a 698 >; 699 }; 700 701 pinctrl_usdhc3_200mhz: usdhc3grp_200mhz { 702 fsl,pins = < 703 MX7D_PAD_SD3_CMD__SD3_CMD 0x5b 704 MX7D_PAD_SD3_CLK__SD3_CLK 0x1b 705 MX7D_PAD_SD3_DATA0__SD3_DATA0 0x5b 706 MX7D_PAD_SD3_DATA1__SD3_DATA1 0x5b 707 MX7D_PAD_SD3_DATA2__SD3_DATA2 0x5b 708 MX7D_PAD_SD3_DATA3__SD3_DATA3 0x5b 709 MX7D_PAD_SD3_DATA4__SD3_DATA4 0x5b 710 MX7D_PAD_SD3_DATA5__SD3_DATA5 0x5b 711 MX7D_PAD_SD3_DATA6__SD3_DATA6 0x5b 712 MX7D_PAD_SD3_DATA7__SD3_DATA7 0x5b 713 MX7D_PAD_SD3_STROBE__SD3_STROBE 0x1b 714 >; 715 }; 716 }; 717}; 718 719&pwm1 { 720 pinctrl-names = "default"; 721 pinctrl-0 = <&pinctrl_pwm1>; 722 status = "okay"; 723}; 724 725&iomuxc_lpsr { 726 pinctrl_wdog: wdoggrp { 727 fsl,pins = < 728 MX7D_PAD_LPSR_GPIO1_IO00__WDOG1_WDOG_B 0x74 729 >; 730 }; 731 732 pinctrl_pwm1: pwm1grp { 733 fsl,pins = < 734 MX7D_PAD_LPSR_GPIO1_IO01__PWM1_OUT 0x30 735 >; 736 }; 737}; 738