1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for Renesas r8a7779 4 * 5 * Copyright (C) 2013 Renesas Solutions Corp. 6 * Copyright (C) 2013 Simon Horman 7 */ 8 9#include <dt-bindings/clock/r8a7779-clock.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/interrupt-controller/irq.h> 12#include <dt-bindings/power/r8a7779-sysc.h> 13 14/ { 15 compatible = "renesas,r8a7779"; 16 interrupt-parent = <&gic>; 17 #address-cells = <1>; 18 #size-cells = <1>; 19 20 cpus { 21 #address-cells = <1>; 22 #size-cells = <0>; 23 24 cpu@0 { 25 device_type = "cpu"; 26 compatible = "arm,cortex-a9"; 27 reg = <0>; 28 clock-frequency = <1000000000>; 29 clocks = <&cpg_clocks R8A7779_CLK_Z>; 30 }; 31 cpu@1 { 32 device_type = "cpu"; 33 compatible = "arm,cortex-a9"; 34 reg = <1>; 35 clock-frequency = <1000000000>; 36 clocks = <&cpg_clocks R8A7779_CLK_Z>; 37 power-domains = <&sysc R8A7779_PD_ARM1>; 38 }; 39 cpu@2 { 40 device_type = "cpu"; 41 compatible = "arm,cortex-a9"; 42 reg = <2>; 43 clock-frequency = <1000000000>; 44 clocks = <&cpg_clocks R8A7779_CLK_Z>; 45 power-domains = <&sysc R8A7779_PD_ARM2>; 46 }; 47 cpu@3 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a9"; 50 reg = <3>; 51 clock-frequency = <1000000000>; 52 clocks = <&cpg_clocks R8A7779_CLK_Z>; 53 power-domains = <&sysc R8A7779_PD_ARM3>; 54 }; 55 }; 56 57 aliases { 58 spi0 = &hspi0; 59 spi1 = &hspi1; 60 spi2 = &hspi2; 61 }; 62 63 gic: interrupt-controller@f0001000 { 64 compatible = "arm,cortex-a9-gic"; 65 #interrupt-cells = <3>; 66 interrupt-controller; 67 reg = <0xf0001000 0x1000>, 68 <0xf0000100 0x100>; 69 }; 70 71 timer@f0000200 { 72 compatible = "arm,cortex-a9-global-timer"; 73 reg = <0xf0000200 0x100>; 74 interrupts = <GIC_PPI 11 75 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 76 clocks = <&cpg_clocks R8A7779_CLK_ZS>; 77 }; 78 79 timer@f0000600 { 80 compatible = "arm,cortex-a9-twd-timer"; 81 reg = <0xf0000600 0x20>; 82 interrupts = <GIC_PPI 13 83 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>; 84 clocks = <&cpg_clocks R8A7779_CLK_ZS>; 85 }; 86 87 gpio0: gpio@ffc40000 { 88 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; 89 reg = <0xffc40000 0x2c>; 90 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; 91 #gpio-cells = <2>; 92 gpio-controller; 93 gpio-ranges = <&pfc 0 0 32>; 94 #interrupt-cells = <2>; 95 interrupt-controller; 96 }; 97 98 gpio1: gpio@ffc41000 { 99 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; 100 reg = <0xffc41000 0x2c>; 101 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; 102 #gpio-cells = <2>; 103 gpio-controller; 104 gpio-ranges = <&pfc 0 32 32>; 105 #interrupt-cells = <2>; 106 interrupt-controller; 107 }; 108 109 gpio2: gpio@ffc42000 { 110 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; 111 reg = <0xffc42000 0x2c>; 112 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; 113 #gpio-cells = <2>; 114 gpio-controller; 115 gpio-ranges = <&pfc 0 64 32>; 116 #interrupt-cells = <2>; 117 interrupt-controller; 118 }; 119 120 gpio3: gpio@ffc43000 { 121 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; 122 reg = <0xffc43000 0x2c>; 123 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; 124 #gpio-cells = <2>; 125 gpio-controller; 126 gpio-ranges = <&pfc 0 96 32>; 127 #interrupt-cells = <2>; 128 interrupt-controller; 129 }; 130 131 gpio4: gpio@ffc44000 { 132 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; 133 reg = <0xffc44000 0x2c>; 134 interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; 135 #gpio-cells = <2>; 136 gpio-controller; 137 gpio-ranges = <&pfc 0 128 32>; 138 #interrupt-cells = <2>; 139 interrupt-controller; 140 }; 141 142 gpio5: gpio@ffc45000 { 143 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; 144 reg = <0xffc45000 0x2c>; 145 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; 146 #gpio-cells = <2>; 147 gpio-controller; 148 gpio-ranges = <&pfc 0 160 32>; 149 #interrupt-cells = <2>; 150 interrupt-controller; 151 }; 152 153 gpio6: gpio@ffc46000 { 154 compatible = "renesas,gpio-r8a7779", "renesas,rcar-gen1-gpio"; 155 reg = <0xffc46000 0x2c>; 156 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; 157 #gpio-cells = <2>; 158 gpio-controller; 159 gpio-ranges = <&pfc 0 192 9>; 160 #interrupt-cells = <2>; 161 interrupt-controller; 162 }; 163 164 irqpin0: interrupt-controller@fe78001c { 165 compatible = "renesas,intc-irqpin-r8a7779", "renesas,intc-irqpin"; 166 #interrupt-cells = <2>; 167 status = "disabled"; 168 interrupt-controller; 169 reg = <0xfe78001c 4>, 170 <0xfe780010 4>, 171 <0xfe780024 4>, 172 <0xfe780044 4>, 173 <0xfe780064 4>, 174 <0xfe780000 4>; 175 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 176 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 177 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH 178 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 179 sense-bitfield-width = <2>; 180 }; 181 182 i2c0: i2c@ffc70000 { 183 #address-cells = <1>; 184 #size-cells = <0>; 185 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; 186 reg = <0xffc70000 0x1000>; 187 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; 188 clocks = <&mstp0_clks R8A7779_CLK_I2C0>; 189 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 190 status = "disabled"; 191 }; 192 193 i2c1: i2c@ffc71000 { 194 #address-cells = <1>; 195 #size-cells = <0>; 196 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; 197 reg = <0xffc71000 0x1000>; 198 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 199 clocks = <&mstp0_clks R8A7779_CLK_I2C1>; 200 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 201 status = "disabled"; 202 }; 203 204 i2c2: i2c@ffc72000 { 205 #address-cells = <1>; 206 #size-cells = <0>; 207 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; 208 reg = <0xffc72000 0x1000>; 209 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 210 clocks = <&mstp0_clks R8A7779_CLK_I2C2>; 211 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 212 status = "disabled"; 213 }; 214 215 i2c3: i2c@ffc73000 { 216 #address-cells = <1>; 217 #size-cells = <0>; 218 compatible = "renesas,i2c-r8a7779", "renesas,rcar-gen1-i2c"; 219 reg = <0xffc73000 0x1000>; 220 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 221 clocks = <&mstp0_clks R8A7779_CLK_I2C3>; 222 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 223 status = "disabled"; 224 }; 225 226 scif0: serial@ffe40000 { 227 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", 228 "renesas,scif"; 229 reg = <0xffe40000 0x100>; 230 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; 231 clocks = <&mstp0_clks R8A7779_CLK_SCIF0>, 232 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; 233 clock-names = "fck", "brg_int", "scif_clk"; 234 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 235 status = "disabled"; 236 }; 237 238 scif1: serial@ffe41000 { 239 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", 240 "renesas,scif"; 241 reg = <0xffe41000 0x100>; 242 interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; 243 clocks = <&mstp0_clks R8A7779_CLK_SCIF1>, 244 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; 245 clock-names = "fck", "brg_int", "scif_clk"; 246 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 247 status = "disabled"; 248 }; 249 250 scif2: serial@ffe42000 { 251 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", 252 "renesas,scif"; 253 reg = <0xffe42000 0x100>; 254 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; 255 clocks = <&mstp0_clks R8A7779_CLK_SCIF2>, 256 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; 257 clock-names = "fck", "brg_int", "scif_clk"; 258 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 259 status = "disabled"; 260 }; 261 262 scif3: serial@ffe43000 { 263 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", 264 "renesas,scif"; 265 reg = <0xffe43000 0x100>; 266 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 267 clocks = <&mstp0_clks R8A7779_CLK_SCIF3>, 268 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; 269 clock-names = "fck", "brg_int", "scif_clk"; 270 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 271 status = "disabled"; 272 }; 273 274 scif4: serial@ffe44000 { 275 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", 276 "renesas,scif"; 277 reg = <0xffe44000 0x100>; 278 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; 279 clocks = <&mstp0_clks R8A7779_CLK_SCIF4>, 280 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; 281 clock-names = "fck", "brg_int", "scif_clk"; 282 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 283 status = "disabled"; 284 }; 285 286 scif5: serial@ffe45000 { 287 compatible = "renesas,scif-r8a7779", "renesas,rcar-gen1-scif", 288 "renesas,scif"; 289 reg = <0xffe45000 0x100>; 290 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 291 clocks = <&mstp0_clks R8A7779_CLK_SCIF5>, 292 <&cpg_clocks R8A7779_CLK_S1>, <&scif_clk>; 293 clock-names = "fck", "brg_int", "scif_clk"; 294 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 295 status = "disabled"; 296 }; 297 298 pfc: pin-controller@fffc0000 { 299 compatible = "renesas,pfc-r8a7779"; 300 reg = <0xfffc0000 0x23c>; 301 }; 302 303 thermal@ffc48000 { 304 compatible = "renesas,thermal-r8a7779", "renesas,rcar-thermal"; 305 reg = <0xffc48000 0x38>; 306 }; 307 308 tmu0: timer@ffd80000 { 309 compatible = "renesas,tmu-r8a7779", "renesas,tmu"; 310 reg = <0xffd80000 0x30>; 311 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 312 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 313 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 314 clocks = <&mstp0_clks R8A7779_CLK_TMU0>; 315 clock-names = "fck"; 316 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 317 318 #renesas,channels = <3>; 319 320 status = "disabled"; 321 }; 322 323 tmu1: timer@ffd81000 { 324 compatible = "renesas,tmu-r8a7779", "renesas,tmu"; 325 reg = <0xffd81000 0x30>; 326 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 327 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 328 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 329 clocks = <&mstp0_clks R8A7779_CLK_TMU1>; 330 clock-names = "fck"; 331 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 332 333 #renesas,channels = <3>; 334 335 status = "disabled"; 336 }; 337 338 tmu2: timer@ffd82000 { 339 compatible = "renesas,tmu-r8a7779", "renesas,tmu"; 340 reg = <0xffd82000 0x30>; 341 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 342 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 343 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 344 clocks = <&mstp0_clks R8A7779_CLK_TMU2>; 345 clock-names = "fck"; 346 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 347 348 #renesas,channels = <3>; 349 350 status = "disabled"; 351 }; 352 353 sata: sata@fc600000 { 354 compatible = "renesas,sata-r8a7779", "renesas,rcar-sata"; 355 reg = <0xfc600000 0x200000>; 356 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 357 clocks = <&mstp1_clks R8A7779_CLK_SATA>; 358 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 359 status = "disabled"; 360 }; 361 362 sdhi0: sd@ffe4c000 { 363 compatible = "renesas,sdhi-r8a7779", 364 "renesas,rcar-gen1-sdhi"; 365 reg = <0xffe4c000 0x100>; 366 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>; 367 clocks = <&mstp3_clks R8A7779_CLK_SDHI0>; 368 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 369 status = "disabled"; 370 }; 371 372 sdhi1: sd@ffe4d000 { 373 compatible = "renesas,sdhi-r8a7779", 374 "renesas,rcar-gen1-sdhi"; 375 reg = <0xffe4d000 0x100>; 376 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; 377 clocks = <&mstp3_clks R8A7779_CLK_SDHI1>; 378 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 379 status = "disabled"; 380 }; 381 382 sdhi2: sd@ffe4e000 { 383 compatible = "renesas,sdhi-r8a7779", 384 "renesas,rcar-gen1-sdhi"; 385 reg = <0xffe4e000 0x100>; 386 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; 387 clocks = <&mstp3_clks R8A7779_CLK_SDHI2>; 388 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 389 status = "disabled"; 390 }; 391 392 sdhi3: sd@ffe4f000 { 393 compatible = "renesas,sdhi-r8a7779", 394 "renesas,rcar-gen1-sdhi"; 395 reg = <0xffe4f000 0x100>; 396 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; 397 clocks = <&mstp3_clks R8A7779_CLK_SDHI3>; 398 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 399 status = "disabled"; 400 }; 401 402 hspi0: spi@fffc7000 { 403 compatible = "renesas,hspi-r8a7779", "renesas,hspi"; 404 reg = <0xfffc7000 0x18>; 405 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 clocks = <&mstp0_clks R8A7779_CLK_HSPI>; 409 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 410 status = "disabled"; 411 }; 412 413 hspi1: spi@fffc8000 { 414 compatible = "renesas,hspi-r8a7779", "renesas,hspi"; 415 reg = <0xfffc8000 0x18>; 416 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 417 #address-cells = <1>; 418 #size-cells = <0>; 419 clocks = <&mstp0_clks R8A7779_CLK_HSPI>; 420 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 421 status = "disabled"; 422 }; 423 424 hspi2: spi@fffc6000 { 425 compatible = "renesas,hspi-r8a7779", "renesas,hspi"; 426 reg = <0xfffc6000 0x18>; 427 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 clocks = <&mstp0_clks R8A7779_CLK_HSPI>; 431 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 432 status = "disabled"; 433 }; 434 435 du: display@fff80000 { 436 compatible = "renesas,du-r8a7779"; 437 reg = <0xfff80000 0x40000>; 438 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 439 clocks = <&mstp1_clks R8A7779_CLK_DU>; 440 power-domains = <&sysc R8A7779_PD_ALWAYS_ON>; 441 status = "disabled"; 442 443 ports { 444 #address-cells = <1>; 445 #size-cells = <0>; 446 447 port@0 { 448 reg = <0>; 449 du_out_rgb0: endpoint { 450 }; 451 }; 452 port@1 { 453 reg = <1>; 454 du_out_rgb1: endpoint { 455 }; 456 }; 457 }; 458 }; 459 460 clocks { 461 #address-cells = <1>; 462 #size-cells = <1>; 463 ranges; 464 465 /* External root clock */ 466 extal_clk: extal { 467 compatible = "fixed-clock"; 468 #clock-cells = <0>; 469 /* This value must be overriden by the board. */ 470 clock-frequency = <0>; 471 }; 472 473 /* External SCIF clock */ 474 scif_clk: scif { 475 compatible = "fixed-clock"; 476 #clock-cells = <0>; 477 /* This value must be overridden by the board. */ 478 clock-frequency = <0>; 479 }; 480 481 /* Special CPG clocks */ 482 cpg_clocks: clocks@ffc80000 { 483 compatible = "renesas,r8a7779-cpg-clocks"; 484 reg = <0xffc80000 0x30>; 485 clocks = <&extal_clk>; 486 #clock-cells = <1>; 487 clock-output-names = "plla", "z", "zs", "s", 488 "s1", "p", "b", "out"; 489 #power-domain-cells = <0>; 490 }; 491 492 /* Fixed factor clocks */ 493 i_clk: i { 494 compatible = "fixed-factor-clock"; 495 clocks = <&cpg_clocks R8A7779_CLK_PLLA>; 496 #clock-cells = <0>; 497 clock-div = <2>; 498 clock-mult = <1>; 499 }; 500 s3_clk: s3 { 501 compatible = "fixed-factor-clock"; 502 clocks = <&cpg_clocks R8A7779_CLK_PLLA>; 503 #clock-cells = <0>; 504 clock-div = <8>; 505 clock-mult = <1>; 506 }; 507 s4_clk: s4 { 508 compatible = "fixed-factor-clock"; 509 clocks = <&cpg_clocks R8A7779_CLK_PLLA>; 510 #clock-cells = <0>; 511 clock-div = <16>; 512 clock-mult = <1>; 513 }; 514 g_clk: g { 515 compatible = "fixed-factor-clock"; 516 clocks = <&cpg_clocks R8A7779_CLK_PLLA>; 517 #clock-cells = <0>; 518 clock-div = <24>; 519 clock-mult = <1>; 520 }; 521 522 /* Gate clocks */ 523 mstp0_clks: clocks@ffc80030 { 524 compatible = "renesas,r8a7779-mstp-clocks", 525 "renesas,cpg-mstp-clocks"; 526 reg = <0xffc80030 4>; 527 clocks = <&cpg_clocks R8A7779_CLK_S>, 528 <&cpg_clocks R8A7779_CLK_P>, 529 <&cpg_clocks R8A7779_CLK_P>, 530 <&cpg_clocks R8A7779_CLK_P>, 531 <&cpg_clocks R8A7779_CLK_S>, 532 <&cpg_clocks R8A7779_CLK_S>, 533 <&cpg_clocks R8A7779_CLK_P>, 534 <&cpg_clocks R8A7779_CLK_P>, 535 <&cpg_clocks R8A7779_CLK_P>, 536 <&cpg_clocks R8A7779_CLK_P>, 537 <&cpg_clocks R8A7779_CLK_P>, 538 <&cpg_clocks R8A7779_CLK_P>, 539 <&cpg_clocks R8A7779_CLK_P>, 540 <&cpg_clocks R8A7779_CLK_P>, 541 <&cpg_clocks R8A7779_CLK_P>, 542 <&cpg_clocks R8A7779_CLK_P>; 543 #clock-cells = <1>; 544 clock-indices = < 545 R8A7779_CLK_HSPI R8A7779_CLK_TMU2 546 R8A7779_CLK_TMU1 R8A7779_CLK_TMU0 547 R8A7779_CLK_HSCIF1 R8A7779_CLK_HSCIF0 548 R8A7779_CLK_SCIF5 R8A7779_CLK_SCIF4 549 R8A7779_CLK_SCIF3 R8A7779_CLK_SCIF2 550 R8A7779_CLK_SCIF1 R8A7779_CLK_SCIF0 551 R8A7779_CLK_I2C3 R8A7779_CLK_I2C2 552 R8A7779_CLK_I2C1 R8A7779_CLK_I2C0 553 >; 554 clock-output-names = 555 "hspi", "tmu2", "tmu1", "tmu0", "hscif1", 556 "hscif0", "scif5", "scif4", "scif3", "scif2", 557 "scif1", "scif0", "i2c3", "i2c2", "i2c1", 558 "i2c0"; 559 }; 560 mstp1_clks: clocks@ffc80034 { 561 compatible = "renesas,r8a7779-mstp-clocks", 562 "renesas,cpg-mstp-clocks"; 563 reg = <0xffc80034 4>, <0xffc80044 4>; 564 clocks = <&cpg_clocks R8A7779_CLK_P>, 565 <&cpg_clocks R8A7779_CLK_P>, 566 <&cpg_clocks R8A7779_CLK_S>, 567 <&cpg_clocks R8A7779_CLK_S>, 568 <&cpg_clocks R8A7779_CLK_S>, 569 <&cpg_clocks R8A7779_CLK_S>, 570 <&cpg_clocks R8A7779_CLK_P>, 571 <&cpg_clocks R8A7779_CLK_P>, 572 <&cpg_clocks R8A7779_CLK_P>, 573 <&cpg_clocks R8A7779_CLK_S>; 574 #clock-cells = <1>; 575 clock-indices = < 576 R8A7779_CLK_USB01 R8A7779_CLK_USB2 577 R8A7779_CLK_DU R8A7779_CLK_VIN2 578 R8A7779_CLK_VIN1 R8A7779_CLK_VIN0 579 R8A7779_CLK_ETHER R8A7779_CLK_SATA 580 R8A7779_CLK_PCIE R8A7779_CLK_VIN3 581 >; 582 clock-output-names = 583 "usb01", "usb2", 584 "du", "vin2", 585 "vin1", "vin0", 586 "ether", "sata", 587 "pcie", "vin3"; 588 }; 589 mstp3_clks: clocks@ffc8003c { 590 compatible = "renesas,r8a7779-mstp-clocks", 591 "renesas,cpg-mstp-clocks"; 592 reg = <0xffc8003c 4>; 593 clocks = <&s4_clk>, <&s4_clk>, <&s4_clk>, <&s4_clk>, 594 <&s4_clk>, <&s4_clk>; 595 #clock-cells = <1>; 596 clock-indices = < 597 R8A7779_CLK_SDHI3 R8A7779_CLK_SDHI2 598 R8A7779_CLK_SDHI1 R8A7779_CLK_SDHI0 599 R8A7779_CLK_MMC1 R8A7779_CLK_MMC0 600 >; 601 clock-output-names = 602 "sdhi3", "sdhi2", "sdhi1", "sdhi0", 603 "mmc1", "mmc0"; 604 }; 605 }; 606 607 prr: chipid@ff000044 { 608 compatible = "renesas,prr"; 609 reg = <0xff000044 4>; 610 }; 611 612 rst: reset-controller@ffcc0000 { 613 compatible = "renesas,r8a7779-reset-wdt"; 614 reg = <0xffcc0000 0x48>; 615 }; 616 617 sysc: system-controller@ffd85000 { 618 compatible = "renesas,r8a7779-sysc"; 619 reg = <0xffd85000 0x0200>; 620 #power-domain-cells = <1>; 621 }; 622}; 623