1/* 2 * Copyright (C) 2015 STMicroelectronics R&D Limited 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8#include <dt-bindings/clock/stih418-clks.h> 9/ { 10 /* 11 * Fixed 30MHz oscillator inputs to SoC 12 */ 13 clk_sysin: clk-sysin { 14 #clock-cells = <0>; 15 compatible = "fixed-clock"; 16 clock-frequency = <30000000>; 17 clock-output-names = "CLK_SYSIN"; 18 }; 19 20 clk_tmdsout_hdmi: clk-tmdsout-hdmi { 21 #clock-cells = <0>; 22 compatible = "fixed-clock"; 23 clock-frequency = <0>; 24 }; 25 26 clocks { 27 #address-cells = <1>; 28 #size-cells = <1>; 29 ranges; 30 31 compatible = "st,stih418-clk", "simple-bus"; 32 33 /* 34 * A9 PLL. 35 */ 36 clockgen-a9@92b0000 { 37 compatible = "st,clkgen-c32"; 38 reg = <0x92b0000 0xffff>; 39 40 clockgen_a9_pll: clockgen-a9-pll { 41 #clock-cells = <1>; 42 compatible = "st,stih418-clkgen-plla9"; 43 44 clocks = <&clk_sysin>; 45 46 clock-output-names = "clockgen-a9-pll-odf"; 47 }; 48 }; 49 50 /* 51 * ARM CPU related clocks. 52 */ 53 clk_m_a9: clk-m-a9@92b0000 { 54 #clock-cells = <0>; 55 compatible = "st,stih407-clkgen-a9-mux", "st,clkgen-mux"; 56 reg = <0x92b0000 0x10000>; 57 58 clocks = <&clockgen_a9_pll 0>, 59 <&clockgen_a9_pll 0>, 60 <&clk_s_c0_flexgen 13>, 61 <&clk_m_a9_ext2f_div2>; 62 63 /* 64 * ARM Peripheral clock for timers 65 */ 66 arm_periph_clk: clk-m-a9-periphs { 67 #clock-cells = <0>; 68 compatible = "fixed-factor-clock"; 69 clocks = <&clk_m_a9>; 70 clock-div = <2>; 71 clock-mult = <1>; 72 }; 73 }; 74 75 clockgen-a@90ff000 { 76 compatible = "st,clkgen-c32"; 77 reg = <0x90ff000 0x1000>; 78 79 clk_s_a0_pll: clk-s-a0-pll { 80 #clock-cells = <1>; 81 compatible = "st,clkgen-pll0"; 82 83 clocks = <&clk_sysin>; 84 85 clock-output-names = "clk-s-a0-pll-ofd-0"; 86 }; 87 88 clk_s_a0_flexgen: clk-s-a0-flexgen { 89 compatible = "st,flexgen"; 90 91 #clock-cells = <1>; 92 93 clocks = <&clk_s_a0_pll 0>, 94 <&clk_sysin>; 95 96 clock-output-names = "clk-ic-lmi0", 97 "clk-ic-lmi1"; 98 }; 99 }; 100 101 clk_s_c0_quadfs: clk-s-c0-quadfs@9103000 { 102 #clock-cells = <1>; 103 compatible = "st,quadfs-pll"; 104 reg = <0x9103000 0x1000>; 105 106 clocks = <&clk_sysin>; 107 108 clock-output-names = "clk-s-c0-fs0-ch0", 109 "clk-s-c0-fs0-ch1", 110 "clk-s-c0-fs0-ch2", 111 "clk-s-c0-fs0-ch3"; 112 }; 113 114 clk_s_c0: clockgen-c@9103000 { 115 compatible = "st,clkgen-c32"; 116 reg = <0x9103000 0x1000>; 117 118 clk_s_c0_pll0: clk-s-c0-pll0 { 119 #clock-cells = <1>; 120 compatible = "st,clkgen-pll0"; 121 122 clocks = <&clk_sysin>; 123 124 clock-output-names = "clk-s-c0-pll0-odf-0"; 125 }; 126 127 clk_s_c0_pll1: clk-s-c0-pll1 { 128 #clock-cells = <1>; 129 compatible = "st,clkgen-pll1"; 130 131 clocks = <&clk_sysin>; 132 133 clock-output-names = "clk-s-c0-pll1-odf-0"; 134 }; 135 136 clk_s_c0_flexgen: clk-s-c0-flexgen { 137 #clock-cells = <1>; 138 compatible = "st,flexgen"; 139 140 clocks = <&clk_s_c0_pll0 0>, 141 <&clk_s_c0_pll1 0>, 142 <&clk_s_c0_quadfs 0>, 143 <&clk_s_c0_quadfs 1>, 144 <&clk_s_c0_quadfs 2>, 145 <&clk_s_c0_quadfs 3>, 146 <&clk_sysin>; 147 148 clock-output-names = "clk-icn-gpu", 149 "clk-fdma", 150 "clk-nand", 151 "clk-hva", 152 "clk-proc-stfe", 153 "clk-tp", 154 "clk-rx-icn-dmu", 155 "clk-rx-icn-hva", 156 "clk-icn-cpu", 157 "clk-tx-icn-dmu", 158 "clk-mmc-0", 159 "clk-mmc-1", 160 "clk-jpegdec", 161 "clk-icn-reg", 162 "clk-proc-bdisp-0", 163 "clk-proc-bdisp-1", 164 "clk-pp-dmu", 165 "clk-vid-dmu", 166 "clk-dss-lpc", 167 "clk-st231-aud-0", 168 "clk-st231-gp-1", 169 "clk-st231-dmu", 170 "clk-icn-lmi", 171 "clk-tx-icn-1", 172 "clk-icn-sbc", 173 "clk-stfe-frc2", 174 "clk-eth-phyref", 175 "clk-eth-ref-phyclk", 176 "clk-flash-promip", 177 "clk-main-disp", 178 "clk-aux-disp", 179 "clk-compo-dvp", 180 "clk-tx-icn-hades", 181 "clk-rx-icn-hades", 182 "clk-icn-reg-16", 183 "clk-pp-hevc", 184 "clk-clust-hevc", 185 "clk-hwpe-hevc", 186 "clk-fc-hevc", 187 "clk-proc-mixer", 188 "clk-proc-sc", 189 "clk-avsp-hevc"; 190 191 /* 192 * ARM Peripheral clock for timers 193 */ 194 clk_m_a9_ext2f_div2: clk-m-a9-ext2f-div2s { 195 #clock-cells = <0>; 196 compatible = "fixed-factor-clock"; 197 198 clocks = <&clk_s_c0_flexgen 13>; 199 200 clock-output-names = "clk-m-a9-ext2f-div2"; 201 202 clock-div = <2>; 203 clock-mult = <1>; 204 }; 205 }; 206 }; 207 208 clk_s_d0_quadfs: clk-s-d0-quadfs@9104000 { 209 #clock-cells = <1>; 210 compatible = "st,quadfs"; 211 reg = <0x9104000 0x1000>; 212 213 clocks = <&clk_sysin>; 214 215 clock-output-names = "clk-s-d0-fs0-ch0", 216 "clk-s-d0-fs0-ch1", 217 "clk-s-d0-fs0-ch2", 218 "clk-s-d0-fs0-ch3"; 219 }; 220 221 clockgen-d0@9104000 { 222 compatible = "st,clkgen-c32"; 223 reg = <0x9104000 0x1000>; 224 225 clk_s_d0_flexgen: clk-s-d0-flexgen { 226 #clock-cells = <1>; 227 compatible = "st,flexgen-audio", "st,flexgen"; 228 229 clocks = <&clk_s_d0_quadfs 0>, 230 <&clk_s_d0_quadfs 1>, 231 <&clk_s_d0_quadfs 2>, 232 <&clk_s_d0_quadfs 3>, 233 <&clk_sysin>; 234 235 clock-output-names = "clk-pcm-0", 236 "clk-pcm-1", 237 "clk-pcm-2", 238 "clk-spdiff", 239 "clk-pcmr10-master", 240 "clk-usb2-phy"; 241 }; 242 }; 243 244 clk_s_d2_quadfs: clk-s-d2-quadfs@9106000 { 245 #clock-cells = <1>; 246 compatible = "st,quadfs"; 247 reg = <0x9106000 0x1000>; 248 249 clocks = <&clk_sysin>; 250 251 clock-output-names = "clk-s-d2-fs0-ch0", 252 "clk-s-d2-fs0-ch1", 253 "clk-s-d2-fs0-ch2", 254 "clk-s-d2-fs0-ch3"; 255 }; 256 257 clockgen-d2@9106000 { 258 compatible = "st,clkgen-c32"; 259 reg = <0x9106000 0x1000>; 260 261 clk_s_d2_flexgen: clk-s-d2-flexgen { 262 #clock-cells = <1>; 263 compatible = "st,flexgen-video", "st,flexgen"; 264 265 clocks = <&clk_s_d2_quadfs 0>, 266 <&clk_s_d2_quadfs 1>, 267 <&clk_s_d2_quadfs 2>, 268 <&clk_s_d2_quadfs 3>, 269 <&clk_sysin>, 270 <&clk_sysin>, 271 <&clk_tmdsout_hdmi>; 272 273 clock-output-names = "clk-pix-main-disp", 274 "", 275 "", 276 "", 277 "", 278 "clk-tmds-hdmi-div2", 279 "clk-pix-aux-disp", 280 "clk-denc", 281 "clk-pix-hddac", 282 "clk-hddac", 283 "clk-sddac", 284 "clk-pix-dvo", 285 "clk-dvo", 286 "clk-pix-hdmi", 287 "clk-tmds-hdmi", 288 "clk-ref-hdmiphy", 289 "", "", "", "", "", 290 "", "", "", "", "", 291 "", "", "", "", "", 292 "", "", "", "", "", 293 "", "", "", "", "", 294 "", "", "", "", "", 295 "", "clk-vp9"; 296 }; 297 }; 298 299 clk_s_d3_quadfs: clk-s-d3-quadfs@9107000 { 300 #clock-cells = <1>; 301 compatible = "st,quadfs"; 302 reg = <0x9107000 0x1000>; 303 304 clocks = <&clk_sysin>; 305 306 clock-output-names = "clk-s-d3-fs0-ch0", 307 "clk-s-d3-fs0-ch1", 308 "clk-s-d3-fs0-ch2", 309 "clk-s-d3-fs0-ch3"; 310 }; 311 312 clockgen-d3@9107000 { 313 compatible = "st,clkgen-c32"; 314 reg = <0x9107000 0x1000>; 315 316 clk_s_d3_flexgen: clk-s-d3-flexgen { 317 #clock-cells = <1>; 318 compatible = "st,flexgen"; 319 320 clocks = <&clk_s_d3_quadfs 0>, 321 <&clk_s_d3_quadfs 1>, 322 <&clk_s_d3_quadfs 2>, 323 <&clk_s_d3_quadfs 3>, 324 <&clk_sysin>; 325 326 clock-output-names = "clk-stfe-frc1", 327 "clk-tsout-0", 328 "clk-tsout-1", 329 "clk-mchi", 330 "clk-vsens-compo", 331 "clk-frc1-remote", 332 "clk-lpc-0", 333 "clk-lpc-1"; 334 }; 335 }; 336 }; 337}; 338