1// SPDX-License-Identifier: GPL-2.0+ OR MIT 2// 3// Device Tree Source for UniPhier LD4 SoC 4// 5// Copyright (C) 2015-2016 Socionext Inc. 6// Author: Masahiro Yamada <yamada.masahiro@socionext.com> 7 8#include <dt-bindings/gpio/uniphier-gpio.h> 9 10/ { 11 compatible = "socionext,uniphier-ld4"; 12 #address-cells = <1>; 13 #size-cells = <1>; 14 15 cpus { 16 #address-cells = <1>; 17 #size-cells = <0>; 18 19 cpu@0 { 20 device_type = "cpu"; 21 compatible = "arm,cortex-a9"; 22 reg = <0>; 23 enable-method = "psci"; 24 next-level-cache = <&l2>; 25 }; 26 }; 27 28 psci { 29 compatible = "arm,psci-0.2"; 30 method = "smc"; 31 }; 32 33 clocks { 34 refclk: ref { 35 compatible = "fixed-clock"; 36 #clock-cells = <0>; 37 clock-frequency = <24576000>; 38 }; 39 40 arm_timer_clk: arm-timer { 41 #clock-cells = <0>; 42 compatible = "fixed-clock"; 43 clock-frequency = <50000000>; 44 }; 45 }; 46 47 soc { 48 compatible = "simple-bus"; 49 #address-cells = <1>; 50 #size-cells = <1>; 51 ranges; 52 interrupt-parent = <&intc>; 53 54 l2: l2-cache@500c0000 { 55 compatible = "socionext,uniphier-system-cache"; 56 reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, 57 <0x506c0000 0x400>; 58 interrupts = <0 174 4>, <0 175 4>; 59 cache-unified; 60 cache-size = <(512 * 1024)>; 61 cache-sets = <256>; 62 cache-line-size = <128>; 63 cache-level = <2>; 64 }; 65 66 serial0: serial@54006800 { 67 compatible = "socionext,uniphier-uart"; 68 status = "disabled"; 69 reg = <0x54006800 0x40>; 70 interrupts = <0 33 4>; 71 pinctrl-names = "default"; 72 pinctrl-0 = <&pinctrl_uart0>; 73 clocks = <&peri_clk 0>; 74 resets = <&peri_rst 0>; 75 }; 76 77 serial1: serial@54006900 { 78 compatible = "socionext,uniphier-uart"; 79 status = "disabled"; 80 reg = <0x54006900 0x40>; 81 interrupts = <0 35 4>; 82 pinctrl-names = "default"; 83 pinctrl-0 = <&pinctrl_uart1>; 84 clocks = <&peri_clk 1>; 85 resets = <&peri_rst 1>; 86 }; 87 88 serial2: serial@54006a00 { 89 compatible = "socionext,uniphier-uart"; 90 status = "disabled"; 91 reg = <0x54006a00 0x40>; 92 interrupts = <0 37 4>; 93 pinctrl-names = "default"; 94 pinctrl-0 = <&pinctrl_uart2>; 95 clocks = <&peri_clk 2>; 96 resets = <&peri_rst 2>; 97 }; 98 99 serial3: serial@54006b00 { 100 compatible = "socionext,uniphier-uart"; 101 status = "disabled"; 102 reg = <0x54006b00 0x40>; 103 interrupts = <0 29 4>; 104 pinctrl-names = "default"; 105 pinctrl-0 = <&pinctrl_uart3>; 106 clocks = <&peri_clk 3>; 107 resets = <&peri_rst 3>; 108 }; 109 110 gpio: gpio@55000000 { 111 compatible = "socionext,uniphier-gpio"; 112 reg = <0x55000000 0x200>; 113 interrupt-parent = <&aidet>; 114 interrupt-controller; 115 #interrupt-cells = <2>; 116 gpio-controller; 117 #gpio-cells = <2>; 118 gpio-ranges = <&pinctrl 0 0 0>; 119 gpio-ranges-group-names = "gpio_range"; 120 ngpios = <136>; 121 socionext,interrupt-ranges = <0 48 13>, <14 62 2>; 122 }; 123 124 i2c0: i2c@58400000 { 125 compatible = "socionext,uniphier-i2c"; 126 status = "disabled"; 127 reg = <0x58400000 0x40>; 128 #address-cells = <1>; 129 #size-cells = <0>; 130 interrupts = <0 41 1>; 131 pinctrl-names = "default"; 132 pinctrl-0 = <&pinctrl_i2c0>; 133 clocks = <&peri_clk 4>; 134 resets = <&peri_rst 4>; 135 clock-frequency = <100000>; 136 }; 137 138 i2c1: i2c@58480000 { 139 compatible = "socionext,uniphier-i2c"; 140 status = "disabled"; 141 reg = <0x58480000 0x40>; 142 #address-cells = <1>; 143 #size-cells = <0>; 144 interrupts = <0 42 1>; 145 pinctrl-names = "default"; 146 pinctrl-0 = <&pinctrl_i2c1>; 147 clocks = <&peri_clk 5>; 148 resets = <&peri_rst 5>; 149 clock-frequency = <100000>; 150 }; 151 152 /* chip-internal connection for DMD */ 153 i2c2: i2c@58500000 { 154 compatible = "socionext,uniphier-i2c"; 155 reg = <0x58500000 0x40>; 156 #address-cells = <1>; 157 #size-cells = <0>; 158 interrupts = <0 43 1>; 159 pinctrl-names = "default"; 160 pinctrl-0 = <&pinctrl_i2c2>; 161 clocks = <&peri_clk 6>; 162 resets = <&peri_rst 6>; 163 clock-frequency = <400000>; 164 }; 165 166 i2c3: i2c@58580000 { 167 compatible = "socionext,uniphier-i2c"; 168 status = "disabled"; 169 reg = <0x58580000 0x40>; 170 #address-cells = <1>; 171 #size-cells = <0>; 172 interrupts = <0 44 1>; 173 pinctrl-names = "default"; 174 pinctrl-0 = <&pinctrl_i2c3>; 175 clocks = <&peri_clk 7>; 176 resets = <&peri_rst 7>; 177 clock-frequency = <100000>; 178 }; 179 180 system_bus: system-bus@58c00000 { 181 compatible = "socionext,uniphier-system-bus"; 182 status = "disabled"; 183 reg = <0x58c00000 0x400>; 184 #address-cells = <2>; 185 #size-cells = <1>; 186 pinctrl-names = "default"; 187 pinctrl-0 = <&pinctrl_system_bus>; 188 }; 189 190 smpctrl@59801000 { 191 compatible = "socionext,uniphier-smpctrl"; 192 reg = <0x59801000 0x400>; 193 }; 194 195 mioctrl@59810000 { 196 compatible = "socionext,uniphier-ld4-mioctrl", 197 "simple-mfd", "syscon"; 198 reg = <0x59810000 0x800>; 199 200 mio_clk: clock { 201 compatible = "socionext,uniphier-ld4-mio-clock"; 202 #clock-cells = <1>; 203 }; 204 205 mio_rst: reset { 206 compatible = "socionext,uniphier-ld4-mio-reset"; 207 #reset-cells = <1>; 208 }; 209 }; 210 211 perictrl@59820000 { 212 compatible = "socionext,uniphier-ld4-perictrl", 213 "simple-mfd", "syscon"; 214 reg = <0x59820000 0x200>; 215 216 peri_clk: clock { 217 compatible = "socionext,uniphier-ld4-peri-clock"; 218 #clock-cells = <1>; 219 }; 220 221 peri_rst: reset { 222 compatible = "socionext,uniphier-ld4-peri-reset"; 223 #reset-cells = <1>; 224 }; 225 }; 226 227 usb0: usb@5a800100 { 228 compatible = "socionext,uniphier-ehci", "generic-ehci"; 229 status = "disabled"; 230 reg = <0x5a800100 0x100>; 231 interrupts = <0 80 4>; 232 pinctrl-names = "default"; 233 pinctrl-0 = <&pinctrl_usb0>; 234 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 8>, 235 <&mio_clk 12>; 236 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 8>, 237 <&mio_rst 12>; 238 has-transaction-translator; 239 }; 240 241 usb1: usb@5a810100 { 242 compatible = "socionext,uniphier-ehci", "generic-ehci"; 243 status = "disabled"; 244 reg = <0x5a810100 0x100>; 245 interrupts = <0 81 4>; 246 pinctrl-names = "default"; 247 pinctrl-0 = <&pinctrl_usb1>; 248 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 9>, 249 <&mio_clk 13>; 250 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 9>, 251 <&mio_rst 13>; 252 has-transaction-translator; 253 }; 254 255 usb2: usb@5a820100 { 256 compatible = "socionext,uniphier-ehci", "generic-ehci"; 257 status = "disabled"; 258 reg = <0x5a820100 0x100>; 259 interrupts = <0 82 4>; 260 pinctrl-names = "default"; 261 pinctrl-0 = <&pinctrl_usb2>; 262 clocks = <&sys_clk 8>, <&mio_clk 7>, <&mio_clk 10>, 263 <&mio_clk 14>; 264 resets = <&sys_rst 8>, <&mio_rst 7>, <&mio_rst 10>, 265 <&mio_rst 14>; 266 has-transaction-translator; 267 }; 268 269 soc-glue@5f800000 { 270 compatible = "socionext,uniphier-ld4-soc-glue", 271 "simple-mfd", "syscon"; 272 reg = <0x5f800000 0x2000>; 273 274 pinctrl: pinctrl { 275 compatible = "socionext,uniphier-ld4-pinctrl"; 276 }; 277 }; 278 279 soc-glue@5f900000 { 280 compatible = "socionext,uniphier-ld4-soc-glue-debug", 281 "simple-mfd"; 282 #address-cells = <1>; 283 #size-cells = <1>; 284 ranges = <0 0x5f900000 0x2000>; 285 286 efuse@100 { 287 compatible = "socionext,uniphier-efuse"; 288 reg = <0x100 0x28>; 289 }; 290 291 efuse@130 { 292 compatible = "socionext,uniphier-efuse"; 293 reg = <0x130 0x8>; 294 }; 295 }; 296 297 timer@60000200 { 298 compatible = "arm,cortex-a9-global-timer"; 299 reg = <0x60000200 0x20>; 300 interrupts = <1 11 0x104>; 301 clocks = <&arm_timer_clk>; 302 }; 303 304 timer@60000600 { 305 compatible = "arm,cortex-a9-twd-timer"; 306 reg = <0x60000600 0x20>; 307 interrupts = <1 13 0x104>; 308 clocks = <&arm_timer_clk>; 309 }; 310 311 intc: interrupt-controller@60001000 { 312 compatible = "arm,cortex-a9-gic"; 313 reg = <0x60001000 0x1000>, 314 <0x60000100 0x100>; 315 #interrupt-cells = <3>; 316 interrupt-controller; 317 }; 318 319 aidet: aidet@61830000 { 320 compatible = "socionext,uniphier-ld4-aidet"; 321 reg = <0x61830000 0x200>; 322 interrupt-controller; 323 #interrupt-cells = <2>; 324 }; 325 326 sysctrl@61840000 { 327 compatible = "socionext,uniphier-ld4-sysctrl", 328 "simple-mfd", "syscon"; 329 reg = <0x61840000 0x10000>; 330 331 sys_clk: clock { 332 compatible = "socionext,uniphier-ld4-clock"; 333 #clock-cells = <1>; 334 }; 335 336 sys_rst: reset { 337 compatible = "socionext,uniphier-ld4-reset"; 338 #reset-cells = <1>; 339 }; 340 }; 341 342 nand: nand@68000000 { 343 compatible = "socionext,uniphier-denali-nand-v5a"; 344 status = "disabled"; 345 reg-names = "nand_data", "denali_reg"; 346 reg = <0x68000000 0x20>, <0x68100000 0x1000>; 347 interrupts = <0 65 4>; 348 pinctrl-names = "default"; 349 pinctrl-0 = <&pinctrl_nand2cs>; 350 clocks = <&sys_clk 2>; 351 resets = <&sys_rst 2>; 352 }; 353 }; 354}; 355 356#include "uniphier-pinctrl.dtsi" 357