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1/*
2 * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
3 *
4 * Based on an original 'vf610-twr.dts' which is Copyright 2015,
5 * Freescale Semiconductor, Inc.
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 *  a) This file is free software; you can redistribute it and/or
13 *     modify it under the terms of the GNU General Public License
14 *     version 2 as published by the Free Software Foundation.
15 *
16 *     This file is distributed in the hope that it will be useful,
17 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
18 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
19 *     GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 *  b) Permission is hereby granted, free of charge, to any person
24 *     obtaining a copy of this software and associated documentation
25 *     files (the "Software"), to deal in the Software without
26 *     restriction, including without limitation the rights to use,
27 *     copy, modify, merge, publish, distribute, sublicense, and/or
28 *     sell copies of the Software, and to permit persons to whom the
29 *     Software is furnished to do so, subject to the following
30 *     conditions:
31 *
32 *     The above copyright notice and this permission notice shall be
33 *     included in all copies or substantial portions of the Software.
34 *
35 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 *     OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45/dts-v1/;
46#include "vf610-zii-dev.dtsi"
47
48/ {
49	model = "ZII VF610 Development Board, Rev B";
50	compatible = "zii,vf610dev-b", "zii,vf610dev", "fsl,vf610";
51
52	mdio-mux {
53		compatible = "mdio-mux-gpio";
54		pinctrl-0 = <&pinctrl_mdio_mux>;
55		pinctrl-names = "default";
56		gpios = <&gpio0 8  GPIO_ACTIVE_HIGH
57			 &gpio0 9  GPIO_ACTIVE_HIGH
58			 &gpio0 24 GPIO_ACTIVE_HIGH
59			 &gpio0 25 GPIO_ACTIVE_HIGH>;
60		mdio-parent-bus = <&mdio1>;
61		#address-cells = <1>;
62		#size-cells = <0>;
63
64		mdio_mux_1: mdio@1 {
65			reg = <1>;
66			#address-cells = <1>;
67			#size-cells = <0>;
68
69			switch0: switch@0 {
70				compatible = "marvell,mv88e6085";
71				pinctrl-0 = <&pinctrl_gpio_switch0>;
72				pinctrl-names = "default";
73				reg = <0>;
74				dsa,member = <0 0>;
75				interrupt-parent = <&gpio0>;
76				interrupts = <27 IRQ_TYPE_LEVEL_LOW>;
77				interrupt-controller;
78				#interrupt-cells = <2>;
79				eeprom-length = <512>;
80
81				ports {
82					#address-cells = <1>;
83					#size-cells = <0>;
84
85					port@0 {
86						reg = <0>;
87						label = "lan0";
88						phy-handle = <&switch0phy0>;
89					};
90
91					port@1 {
92						reg = <1>;
93						label = "lan1";
94						phy-handle = <&switch0phy1>;
95					};
96
97					port@2 {
98						reg = <2>;
99						label = "lan2";
100						phy-handle = <&switch0phy2>;
101					};
102
103					switch0port5: port@5 {
104						reg = <5>;
105						label = "dsa";
106						phy-mode = "rgmii-txid";
107						link = <&switch1port6
108							&switch2port9>;
109						fixed-link {
110							speed = <1000>;
111							full-duplex;
112						};
113					};
114
115					port@6 {
116						reg = <6>;
117						label = "cpu";
118						ethernet = <&fec1>;
119
120						fixed-link {
121							speed = <100>;
122							full-duplex;
123						};
124					};
125				};
126				mdio {
127					#address-cells = <1>;
128					#size-cells = <0>;
129					switch0phy0: switch0phy0@0 {
130						reg = <0>;
131						interrupt-parent = <&switch0>;
132						interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
133					};
134					switch0phy1: switch1phy0@1 {
135						reg = <1>;
136						interrupt-parent = <&switch0>;
137						interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
138					};
139					switch0phy2: switch1phy0@2 {
140						reg = <2>;
141						interrupt-parent = <&switch0>;
142						interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
143					};
144				};
145			};
146		};
147
148		mdio_mux_2: mdio@2 {
149			reg = <2>;
150			#address-cells = <1>;
151			#size-cells = <0>;
152
153			switch1: switch@0 {
154				compatible = "marvell,mv88e6085";
155				pinctrl-0 = <&pinctrl_gpio_switch1>;
156				pinctrl-names = "default";
157				reg = <0>;
158				dsa,member = <0 1>;
159				interrupt-parent = <&gpio0>;
160				interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
161				interrupt-controller;
162				#interrupt-cells = <2>;
163				eeprom-length = <512>;
164
165				ports {
166					#address-cells = <1>;
167					#size-cells = <0>;
168
169					port@0 {
170						reg = <0>;
171						label = "lan3";
172						phy-handle = <&switch1phy0>;
173					};
174
175					port@1 {
176						reg = <1>;
177						label = "lan4";
178						phy-handle = <&switch1phy1>;
179					};
180
181					port@2 {
182						reg = <2>;
183						label = "lan5";
184						phy-handle = <&switch1phy2>;
185					};
186
187					switch1port5: port@5 {
188						reg = <5>;
189						label = "dsa";
190						link = <&switch2port9>;
191						phy-mode = "rgmii-txid";
192
193						fixed-link {
194							speed = <1000>;
195							full-duplex;
196						};
197					};
198
199					switch1port6: port@6 {
200						reg = <6>;
201						label = "dsa";
202						phy-mode = "rgmii-txid";
203						link = <&switch0port5>;
204						fixed-link {
205							speed = <1000>;
206							full-duplex;
207						};
208					};
209				};
210				mdio {
211					#address-cells = <1>;
212					#size-cells = <0>;
213
214					switch1phy0: switch1phy0@0 {
215						reg = <0>;
216						interrupt-parent = <&switch1>;
217						interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
218					};
219
220					switch1phy1: switch1phy0@1 {
221						reg = <1>;
222						interrupt-parent = <&switch1>;
223						interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
224					};
225
226					switch1phy2: switch1phy0@2 {
227						reg = <2>;
228						interrupt-parent = <&switch1>;
229						interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
230					};
231				};
232			};
233		};
234
235		mdio_mux_4: mdio@4 {
236			#address-cells = <1>;
237			#size-cells = <0>;
238			reg = <4>;
239
240			switch2: switch@0 {
241				compatible = "marvell,mv88e6085";
242				reg = <0>;
243				dsa,member = <0 2>;
244
245				ports {
246					#address-cells = <1>;
247					#size-cells = <0>;
248
249					port@0 {
250						reg = <0>;
251						label = "lan6";
252						phy-handle = <&switch2phy0>;
253					};
254
255					port@1 {
256						reg = <1>;
257						label = "lan7";
258						phy-handle = <&switch2phy1>;
259					};
260
261					port@2 {
262						reg = <2>;
263						label = "lan8";
264						phy-handle = <&switch2phy2>;
265					};
266
267					port@3 {
268						reg = <3>;
269						label = "optical3";
270
271						fixed-link {
272							speed = <1000>;
273							full-duplex;
274							link-gpios = <&gpio6 2
275							      GPIO_ACTIVE_HIGH>;
276						};
277					};
278
279					port@4 {
280						reg = <4>;
281						label = "optical4";
282
283						fixed-link {
284							speed = <1000>;
285							full-duplex;
286							link-gpios = <&gpio6 3
287							      GPIO_ACTIVE_HIGH>;
288						};
289					};
290
291					switch2port9: port@9 {
292						reg = <9>;
293						label = "dsa";
294						phy-mode = "rgmii-txid";
295						link = <&switch1port5
296							&switch0port5>;
297
298						fixed-link {
299							speed = <1000>;
300							full-duplex;
301						};
302					};
303				};
304				mdio {
305					#address-cells = <1>;
306					#size-cells = <0>;
307
308					switch2phy0: phy@0 {
309						reg = <0>;
310					};
311					switch2phy1: phy@1 {
312						reg = <1>;
313					};
314					switch2phy2: phy@2 {
315						reg = <2>;
316					};
317				};
318			};
319		};
320
321		mdio_mux_8: mdio@8 {
322			reg = <8>;
323			#address-cells = <1>;
324			#size-cells = <0>;
325		};
326	};
327
328	spi0 {
329		compatible = "spi-gpio";
330		pinctrl-0 = <&pinctrl_gpio_spi0>;
331		pinctrl-names = "default";
332		#address-cells = <1>;
333		#size-cells = <0>;
334		gpio-sck  = <&gpio1 12 GPIO_ACTIVE_HIGH>;
335		gpio-mosi = <&gpio1 11 GPIO_ACTIVE_HIGH>;
336		gpio-miso = <&gpio1 10 GPIO_ACTIVE_HIGH>;
337		cs-gpios  = <&gpio1  9 GPIO_ACTIVE_HIGH
338			     &gpio1  8 GPIO_ACTIVE_HIGH>;
339		num-chipselects = <2>;
340
341		m25p128@0 {
342			compatible = "m25p128", "jedec,spi-nor";
343			#address-cells = <1>;
344			#size-cells = <1>;
345			reg = <0>;
346			spi-max-frequency = <1000000>;
347		};
348
349		at93c46d@1 {
350			compatible = "atmel,at93c46d";
351			pinctrl-0 = <&pinctrl_gpio_e6185_eeprom_sel>;
352			pinctrl-names = "default";
353			#address-cells = <0>;
354			#size-cells = <0>;
355			reg = <1>;
356			spi-max-frequency = <500000>;
357			spi-cs-high;
358			data-size = <16>;
359			select-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
360		};
361	};
362};
363
364&i2c0 {
365	clock-frequency = <100000>;
366	pinctrl-names = "default";
367	pinctrl-0 = <&pinctrl_i2c0>;
368	status = "okay";
369
370	gpio5: pca9554@20 {
371		compatible = "nxp,pca9554";
372		reg = <0x20>;
373		gpio-controller;
374		#gpio-cells = <2>;
375
376	};
377
378	gpio6: pca9554@22 {
379		compatible = "nxp,pca9554";
380		pinctrl-names = "default";
381		pinctrl-0 = <&pinctrl_pca9554_22>;
382		reg = <0x22>;
383		gpio-controller;
384		#gpio-cells = <2>;
385		interrupt-controller;
386		interrupt-parent = <&gpio3>;
387		interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
388	};
389};
390
391&i2c2 {
392	clock-frequency = <100000>;
393	pinctrl-names = "default";
394	pinctrl-0 = <&pinctrl_i2c2>;
395	status = "okay";
396
397	tca9548@70 {
398		compatible = "nxp,pca9548";
399		pinctrl-0 = <&pinctrl_i2c_mux_reset>;
400		pinctrl-names = "default";
401		#address-cells = <1>;
402		#size-cells = <0>;
403		reg = <0x70>;
404		reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
405
406		i2c@0 {
407			#address-cells = <1>;
408			#size-cells = <0>;
409			reg = <0>;
410
411			sfp1: at24c04@50 {
412				compatible = "atmel,24c02";
413				reg = <0x50>;
414			};
415		};
416
417		i2c@1 {
418			#address-cells = <1>;
419			#size-cells = <0>;
420			reg = <1>;
421
422			sfp2: at24c04@50 {
423				compatible = "atmel,24c02";
424				reg = <0x50>;
425			};
426		};
427
428		i2c@2 {
429			#address-cells = <1>;
430			#size-cells = <0>;
431			reg = <2>;
432
433			sfp3: at24c04@50 {
434				compatible = "atmel,24c02";
435				reg = <0x50>;
436			};
437		};
438
439		i2c@3 {
440			#address-cells = <1>;
441			#size-cells = <0>;
442			reg = <3>;
443
444			sfp4: at24c04@50 {
445				compatible = "atmel,24c02";
446				reg = <0x50>;
447			};
448		};
449
450		i2c@4 {
451			#address-cells = <1>;
452			#size-cells = <0>;
453			reg = <4>;
454		};
455	};
456};
457
458
459&iomuxc {
460	pinctrl_gpio_e6185_eeprom_sel: pinctrl-gpio-e6185-eeprom-spi0 {
461		fsl,pins = <
462			VF610_PAD_PTE27__GPIO_132	0x33e2
463		>;
464	};
465
466	pinctrl_gpio_spi0: pinctrl-gpio-spi0 {
467		fsl,pins = <
468			VF610_PAD_PTB22__GPIO_44	0x33e2
469			VF610_PAD_PTB21__GPIO_43	0x33e2
470			VF610_PAD_PTB20__GPIO_42	0x33e1
471			VF610_PAD_PTB19__GPIO_41	0x33e2
472			VF610_PAD_PTB18__GPIO_40	0x33e2
473		>;
474	};
475
476	pinctrl_mdio_mux: pinctrl-mdio-mux {
477		fsl,pins = <
478			VF610_PAD_PTA18__GPIO_8		0x31c2
479			VF610_PAD_PTA19__GPIO_9		0x31c2
480			VF610_PAD_PTB2__GPIO_24		0x31c2
481			VF610_PAD_PTB3__GPIO_25		0x31c2
482		>;
483	};
484
485	pinctrl_pca9554_22: pinctrl-pca95540-22 {
486		fsl,pins = <
487			VF610_PAD_PTB28__GPIO_98	0x219d
488		>;
489	};
490};
491