1/* 2 * linux/arch/arm/kernel/head-nommu.S 3 * 4 * Copyright (C) 1994-2002 Russell King 5 * Copyright (C) 2003-2006 Hyok S. Choi 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 * 11 * Common kernel startup code (non-paged MM) 12 * 13 */ 14#include <linux/linkage.h> 15#include <linux/init.h> 16#include <linux/errno.h> 17 18#include <asm/assembler.h> 19#include <asm/ptrace.h> 20#include <asm/asm-offsets.h> 21#include <asm/memory.h> 22#include <asm/cp15.h> 23#include <asm/thread_info.h> 24#include <asm/v7m.h> 25#include <asm/mpu.h> 26#include <asm/page.h> 27 28/* 29 * Kernel startup entry point. 30 * --------------------------- 31 * 32 * This is normally called from the decompressor code. The requirements 33 * are: MMU = off, D-cache = off, I-cache = dont care, r0 = 0, 34 * r1 = machine nr. 35 * 36 * See linux/arch/arm/tools/mach-types for the complete list of machine 37 * numbers for r1. 38 * 39 */ 40 41 __HEAD 42 43#ifdef CONFIG_CPU_THUMBONLY 44 .thumb 45ENTRY(stext) 46#else 47 .arm 48ENTRY(stext) 49 50 THUMB( badr r9, 1f ) @ Kernel is always entered in ARM. 51 THUMB( bx r9 ) @ If this is a Thumb-2 kernel, 52 THUMB( .thumb ) @ switch to Thumb now. 53 THUMB(1: ) 54#endif 55 56#ifdef CONFIG_ARM_VIRT_EXT 57 bl __hyp_stub_install 58#endif 59 @ ensure svc mode and all interrupts masked 60 safe_svcmode_maskall r9 61 @ and irqs disabled 62#if defined(CONFIG_CPU_CP15) 63 mrc p15, 0, r9, c0, c0 @ get processor id 64#elif defined(CONFIG_CPU_V7M) 65 ldr r9, =BASEADDR_V7M_SCB 66 ldr r9, [r9, V7M_SCB_CPUID] 67#else 68 ldr r9, =CONFIG_PROCESSOR_ID 69#endif 70 bl __lookup_processor_type @ r5=procinfo r9=cpuid 71 movs r10, r5 @ invalid processor (r5=0)? 72 beq __error_p @ yes, error 'p' 73 74#ifdef CONFIG_ARM_MPU 75 bl __setup_mpu 76#endif 77 78 badr lr, 1f @ return (PIC) address 79 ldr r12, [r10, #PROCINFO_INITFUNC] 80 add r12, r12, r10 81 ret r12 821: ldr lr, =__mmap_switched 83 b __after_proc_init 84ENDPROC(stext) 85 86#ifdef CONFIG_SMP 87 .text 88ENTRY(secondary_startup) 89 /* 90 * Common entry point for secondary CPUs. 91 * 92 * Ensure that we're in SVC mode, and IRQs are disabled. Lookup 93 * the processor type - there is no need to check the machine type 94 * as it has already been validated by the primary processor. 95 */ 96#ifdef CONFIG_ARM_VIRT_EXT 97 bl __hyp_stub_install_secondary 98#endif 99 safe_svcmode_maskall r9 100 101#ifndef CONFIG_CPU_CP15 102 ldr r9, =CONFIG_PROCESSOR_ID 103#else 104 mrc p15, 0, r9, c0, c0 @ get processor id 105#endif 106 bl __lookup_processor_type @ r5=procinfo r9=cpuid 107 movs r10, r5 @ invalid processor? 108 beq __error_p @ yes, error 'p' 109 110 ldr r7, __secondary_data 111 112#ifdef CONFIG_ARM_MPU 113 bl __secondary_setup_mpu @ Initialize the MPU 114#endif 115 116 badr lr, 1f @ return (PIC) address 117 ldr r12, [r10, #PROCINFO_INITFUNC] 118 add r12, r12, r10 119 ret r12 1201: bl __after_proc_init 121 ldr sp, [r7, #12] @ set up the stack pointer 122 mov fp, #0 123 b secondary_start_kernel 124ENDPROC(secondary_startup) 125 126 .type __secondary_data, %object 127__secondary_data: 128 .long secondary_data 129#endif /* CONFIG_SMP */ 130 131/* 132 * Set the Control Register and Read the process ID. 133 */ 134 .text 135__after_proc_init: 136M_CLASS(movw r12, #:lower16:BASEADDR_V7M_SCB) 137M_CLASS(movt r12, #:upper16:BASEADDR_V7M_SCB) 138#ifdef CONFIG_ARM_MPU 139M_CLASS(ldr r3, [r12, 0x50]) 140AR_CLASS(mrc p15, 0, r3, c0, c1, 4) @ Read ID_MMFR0 141 and r3, r3, #(MMFR0_PMSA) @ PMSA field 142 teq r3, #(MMFR0_PMSAv7) @ PMSA v7 143 beq 1f 144 teq r3, #(MMFR0_PMSAv8) @ PMSA v8 145 /* 146 * Memory region attributes for PMSAv8: 147 * 148 * n = AttrIndx[2:0] 149 * n MAIR 150 * DEVICE_nGnRnE 000 00000000 151 * NORMAL 001 11111111 152 */ 153 ldreq r3, =PMSAv8_MAIR(0x00, PMSAv8_RGN_DEVICE_nGnRnE) | \ 154 PMSAv8_MAIR(0xff, PMSAv8_RGN_NORMAL) 155AR_CLASS(mcreq p15, 0, r3, c10, c2, 0) @ MAIR 0 156M_CLASS(streq r3, [r12, #PMSAv8_MAIR0]) 157 moveq r3, #0 158AR_CLASS(mcreq p15, 0, r3, c10, c2, 1) @ MAIR 1 159M_CLASS(streq r3, [r12, #PMSAv8_MAIR1]) 160 1611: 162#endif 163#ifdef CONFIG_CPU_CP15 164 /* 165 * CP15 system control register value returned in r0 from 166 * the CPU init function. 167 */ 168 169#ifdef CONFIG_ARM_MPU 170 biceq r0, r0, #CR_BR @ Disable the 'default mem-map' 171 orreq r0, r0, #CR_M @ Set SCTRL.M (MPU on) 172#endif 173#if defined(CONFIG_ALIGNMENT_TRAP) && __LINUX_ARM_ARCH__ < 6 174 orr r0, r0, #CR_A 175#else 176 bic r0, r0, #CR_A 177#endif 178#ifdef CONFIG_CPU_DCACHE_DISABLE 179 bic r0, r0, #CR_C 180#endif 181#ifdef CONFIG_CPU_BPREDICT_DISABLE 182 bic r0, r0, #CR_Z 183#endif 184#ifdef CONFIG_CPU_ICACHE_DISABLE 185 bic r0, r0, #CR_I 186#endif 187 mcr p15, 0, r0, c1, c0, 0 @ write control reg 188 instr_sync 189#elif defined (CONFIG_CPU_V7M) 190#ifdef CONFIG_ARM_MPU 191 ldreq r3, [r12, MPU_CTRL] 192 biceq r3, #MPU_CTRL_PRIVDEFENA 193 orreq r3, #MPU_CTRL_ENABLE 194 streq r3, [r12, MPU_CTRL] 195 isb 196#endif 197 /* For V7M systems we want to modify the CCR similarly to the SCTLR */ 198#ifdef CONFIG_CPU_DCACHE_DISABLE 199 bic r0, r0, #V7M_SCB_CCR_DC 200#endif 201#ifdef CONFIG_CPU_BPREDICT_DISABLE 202 bic r0, r0, #V7M_SCB_CCR_BP 203#endif 204#ifdef CONFIG_CPU_ICACHE_DISABLE 205 bic r0, r0, #V7M_SCB_CCR_IC 206#endif 207 str r0, [r12, V7M_SCB_CCR] 208 /* Pass exc_ret to __mmap_switched */ 209 mov r0, r10 210#endif /* CONFIG_CPU_CP15 elif CONFIG_CPU_V7M */ 211 ret lr 212ENDPROC(__after_proc_init) 213 .ltorg 214 215#ifdef CONFIG_ARM_MPU 216 217 218#ifndef CONFIG_CPU_V7M 219/* Set which MPU region should be programmed */ 220.macro set_region_nr tmp, rgnr, unused 221 mov \tmp, \rgnr @ Use static region numbers 222 mcr p15, 0, \tmp, c6, c2, 0 @ Write RGNR 223.endm 224 225/* Setup a single MPU region, either D or I side (D-side for unified) */ 226.macro setup_region bar, acr, sr, side = PMSAv7_DATA_SIDE, unused 227 mcr p15, 0, \bar, c6, c1, (0 + \side) @ I/DRBAR 228 mcr p15, 0, \acr, c6, c1, (4 + \side) @ I/DRACR 229 mcr p15, 0, \sr, c6, c1, (2 + \side) @ I/DRSR 230.endm 231#else 232.macro set_region_nr tmp, rgnr, base 233 mov \tmp, \rgnr 234 str \tmp, [\base, #PMSAv7_RNR] 235.endm 236 237.macro setup_region bar, acr, sr, unused, base 238 lsl \acr, \acr, #16 239 orr \acr, \acr, \sr 240 str \bar, [\base, #PMSAv7_RBAR] 241 str \acr, [\base, #PMSAv7_RASR] 242.endm 243 244#endif 245/* 246 * Setup the MPU and initial MPU Regions. We create the following regions: 247 * Region 0: Use this for probing the MPU details, so leave disabled. 248 * Region 1: Background region - covers the whole of RAM as strongly ordered 249 * Region 2: Normal, Shared, cacheable for RAM. From PHYS_OFFSET, size from r6 250 * Region 3: Normal, shared, inaccessible from PL0 to protect the vectors page 251 * 252 * r6: Value to be written to DRSR (and IRSR if required) for PMSAv7_RAM_REGION 253*/ 254 __HEAD 255 256ENTRY(__setup_mpu) 257 258 /* Probe for v7 PMSA compliance */ 259M_CLASS(movw r12, #:lower16:BASEADDR_V7M_SCB) 260M_CLASS(movt r12, #:upper16:BASEADDR_V7M_SCB) 261 262AR_CLASS(mrc p15, 0, r0, c0, c1, 4) @ Read ID_MMFR0 263M_CLASS(ldr r0, [r12, 0x50]) 264 and r0, r0, #(MMFR0_PMSA) @ PMSA field 265 teq r0, #(MMFR0_PMSAv7) @ PMSA v7 266 beq __setup_pmsa_v7 267 teq r0, #(MMFR0_PMSAv8) @ PMSA v8 268 beq __setup_pmsa_v8 269 270 ret lr 271ENDPROC(__setup_mpu) 272 273ENTRY(__setup_pmsa_v7) 274 /* Calculate the size of a region covering just the kernel */ 275 ldr r5, =PLAT_PHYS_OFFSET @ Region start: PHYS_OFFSET 276 ldr r6, =(_end) @ Cover whole kernel 277 sub r6, r6, r5 @ Minimum size of region to map 278 clz r6, r6 @ Region size must be 2^N... 279 rsb r6, r6, #31 @ ...so round up region size 280 lsl r6, r6, #PMSAv7_RSR_SZ @ Put size in right field 281 orr r6, r6, #(1 << PMSAv7_RSR_EN) @ Set region enabled bit 282 283 /* Determine whether the D/I-side memory map is unified. We set the 284 * flags here and continue to use them for the rest of this function */ 285AR_CLASS(mrc p15, 0, r0, c0, c0, 4) @ MPUIR 286M_CLASS(ldr r0, [r12, #MPU_TYPE]) 287 ands r5, r0, #MPUIR_DREGION_SZMASK @ 0 size d region => No MPU 288 bxeq lr 289 tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified 290 291 /* Setup second region first to free up r6 */ 292 set_region_nr r0, #PMSAv7_RAM_REGION, r12 293 isb 294 /* Full access from PL0, PL1, shared for CONFIG_SMP, cacheable */ 295 ldr r0, =PLAT_PHYS_OFFSET @ RAM starts at PHYS_OFFSET 296 ldr r5,=(PMSAv7_AP_PL1RW_PL0RW | PMSAv7_RGN_NORMAL) 297 298 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ PHYS_OFFSET, shared, enabled 299 beq 1f @ Memory-map not unified 300 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ PHYS_OFFSET, shared, enabled 3011: isb 302 303 /* First/background region */ 304 set_region_nr r0, #PMSAv7_BG_REGION, r12 305 isb 306 /* Execute Never, strongly ordered, inaccessible to PL0, rw PL1 */ 307 mov r0, #0 @ BG region starts at 0x0 308 ldr r5,=(PMSAv7_ACR_XN | PMSAv7_RGN_STRONGLY_ORDERED | PMSAv7_AP_PL1RW_PL0NA) 309 mov r6, #PMSAv7_RSR_ALL_MEM @ 4GB region, enabled 310 311 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ 0x0, BG region, enabled 312 beq 2f @ Memory-map not unified 313 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE r12 @ 0x0, BG region, enabled 3142: isb 315 316#ifdef CONFIG_XIP_KERNEL 317 set_region_nr r0, #PMSAv7_ROM_REGION, r12 318 isb 319 320 ldr r5,=(PMSAv7_AP_PL1RO_PL0NA | PMSAv7_RGN_NORMAL) 321 322 ldr r0, =CONFIG_XIP_PHYS_ADDR @ ROM start 323 ldr r6, =(_exiprom) @ ROM end 324 sub r6, r6, r0 @ Minimum size of region to map 325 clz r6, r6 @ Region size must be 2^N... 326 rsb r6, r6, #31 @ ...so round up region size 327 lsl r6, r6, #PMSAv7_RSR_SZ @ Put size in right field 328 orr r6, r6, #(1 << PMSAv7_RSR_EN) @ Set region enabled bit 329 330 setup_region r0, r5, r6, PMSAv7_DATA_SIDE, r12 @ XIP_PHYS_ADDR, shared, enabled 331 beq 3f @ Memory-map not unified 332 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE, r12 @ XIP_PHYS_ADDR, shared, enabled 3333: isb 334#endif 335 ret lr 336ENDPROC(__setup_pmsa_v7) 337 338ENTRY(__setup_pmsa_v8) 339 mov r0, #0 340AR_CLASS(mcr p15, 0, r0, c6, c2, 1) @ PRSEL 341M_CLASS(str r0, [r12, #PMSAv8_RNR]) 342 isb 343 344#ifdef CONFIG_XIP_KERNEL 345 ldr r5, =CONFIG_XIP_PHYS_ADDR @ ROM start 346 ldr r6, =(_exiprom) @ ROM end 347 sub r6, r6, #1 348 bic r6, r6, #(PMSAv8_MINALIGN - 1) 349 350 orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED) 351 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN) 352 353AR_CLASS(mcr p15, 0, r5, c6, c8, 0) @ PRBAR0 354AR_CLASS(mcr p15, 0, r6, c6, c8, 1) @ PRLAR0 355M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(0)]) 356M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(0)]) 357#endif 358 359 ldr r5, =KERNEL_START 360 ldr r6, =KERNEL_END 361 sub r6, r6, #1 362 bic r6, r6, #(PMSAv8_MINALIGN - 1) 363 364 orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED) 365 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_NORMAL) | PMSAv8_LAR_EN) 366 367AR_CLASS(mcr p15, 0, r5, c6, c8, 4) @ PRBAR1 368AR_CLASS(mcr p15, 0, r6, c6, c8, 5) @ PRLAR1 369M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(1)]) 370M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(1)]) 371 372 /* Setup Background: 0x0 - min(KERNEL_START, XIP_PHYS_ADDR) */ 373#ifdef CONFIG_XIP_KERNEL 374 ldr r6, =KERNEL_START 375 ldr r5, =CONFIG_XIP_PHYS_ADDR 376 cmp r6, r5 377 movcs r6, r5 378#else 379 ldr r6, =KERNEL_START 380#endif 381 cmp r6, #0 382 beq 1f 383 384 mov r5, #0 385 sub r6, r6, #1 386 bic r6, r6, #(PMSAv8_MINALIGN - 1) 387 388 orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN) 389 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN) 390 391AR_CLASS(mcr p15, 0, r5, c6, c9, 0) @ PRBAR2 392AR_CLASS(mcr p15, 0, r6, c6, c9, 1) @ PRLAR2 393M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(2)]) 394M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(2)]) 395 3961: 397 /* Setup Background: max(KERNEL_END, _exiprom) - 0xffffffff */ 398#ifdef CONFIG_XIP_KERNEL 399 ldr r5, =KERNEL_END 400 ldr r6, =(_exiprom) 401 cmp r5, r6 402 movcc r5, r6 403#else 404 ldr r5, =KERNEL_END 405#endif 406 mov r6, #0xffffffff 407 bic r6, r6, #(PMSAv8_MINALIGN - 1) 408 409 orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN) 410 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN) 411 412AR_CLASS(mcr p15, 0, r5, c6, c9, 4) @ PRBAR3 413AR_CLASS(mcr p15, 0, r6, c6, c9, 5) @ PRLAR3 414M_CLASS(str r5, [r12, #PMSAv8_RBAR_A(3)]) 415M_CLASS(str r6, [r12, #PMSAv8_RLAR_A(3)]) 416 417#ifdef CONFIG_XIP_KERNEL 418 /* Setup Background: min(_exiprom, KERNEL_END) - max(KERNEL_START, XIP_PHYS_ADDR) */ 419 ldr r5, =(_exiprom) 420 ldr r6, =KERNEL_END 421 cmp r5, r6 422 movcs r5, r6 423 424 ldr r6, =KERNEL_START 425 ldr r0, =CONFIG_XIP_PHYS_ADDR 426 cmp r6, r0 427 movcc r6, r0 428 429 sub r6, r6, #1 430 bic r6, r6, #(PMSAv8_MINALIGN - 1) 431 432 orr r5, r5, #(PMSAv8_AP_PL1RW_PL0NA | PMSAv8_RGN_SHARED | PMSAv8_BAR_XN) 433 orr r6, r6, #(PMSAv8_LAR_IDX(PMSAv8_RGN_DEVICE_nGnRnE) | PMSAv8_LAR_EN) 434 435#ifdef CONFIG_CPU_V7M 436 /* There is no alias for n == 4 */ 437 mov r0, #4 438 str r0, [r12, #PMSAv8_RNR] @ PRSEL 439 isb 440 441 str r5, [r12, #PMSAv8_RBAR_A(0)] 442 str r6, [r12, #PMSAv8_RLAR_A(0)] 443#else 444 mcr p15, 0, r5, c6, c10, 0 @ PRBAR4 445 mcr p15, 0, r6, c6, c10, 1 @ PRLAR4 446#endif 447#endif 448 ret lr 449ENDPROC(__setup_pmsa_v8) 450 451#ifdef CONFIG_SMP 452/* 453 * r6: pointer at mpu_rgn_info 454 */ 455 456 .text 457ENTRY(__secondary_setup_mpu) 458 /* Use MPU region info supplied by __cpu_up */ 459 ldr r6, [r7] @ get secondary_data.mpu_rgn_info 460 461 /* Probe for v7 PMSA compliance */ 462 mrc p15, 0, r0, c0, c1, 4 @ Read ID_MMFR0 463 and r0, r0, #(MMFR0_PMSA) @ PMSA field 464 teq r0, #(MMFR0_PMSAv7) @ PMSA v7 465 beq __secondary_setup_pmsa_v7 466 teq r0, #(MMFR0_PMSAv8) @ PMSA v8 467 beq __secondary_setup_pmsa_v8 468 b __error_p 469ENDPROC(__secondary_setup_mpu) 470 471/* 472 * r6: pointer at mpu_rgn_info 473 */ 474ENTRY(__secondary_setup_pmsa_v7) 475 /* Determine whether the D/I-side memory map is unified. We set the 476 * flags here and continue to use them for the rest of this function */ 477 mrc p15, 0, r0, c0, c0, 4 @ MPUIR 478 ands r5, r0, #MPUIR_DREGION_SZMASK @ 0 size d region => No MPU 479 beq __error_p 480 481 ldr r4, [r6, #MPU_RNG_INFO_USED] 482 mov r5, #MPU_RNG_SIZE 483 add r3, r6, #MPU_RNG_INFO_RNGS 484 mla r3, r4, r5, r3 485 4861: 487 tst r0, #MPUIR_nU @ MPUIR_nU = 0 for unified 488 sub r3, r3, #MPU_RNG_SIZE 489 sub r4, r4, #1 490 491 set_region_nr r0, r4 492 isb 493 494 ldr r0, [r3, #MPU_RGN_DRBAR] 495 ldr r6, [r3, #MPU_RGN_DRSR] 496 ldr r5, [r3, #MPU_RGN_DRACR] 497 498 setup_region r0, r5, r6, PMSAv7_DATA_SIDE 499 beq 2f 500 setup_region r0, r5, r6, PMSAv7_INSTR_SIDE 5012: isb 502 503 mrc p15, 0, r0, c0, c0, 4 @ Reevaluate the MPUIR 504 cmp r4, #0 505 bgt 1b 506 507 ret lr 508ENDPROC(__secondary_setup_pmsa_v7) 509 510ENTRY(__secondary_setup_pmsa_v8) 511 ldr r4, [r6, #MPU_RNG_INFO_USED] 512#ifndef CONFIG_XIP_KERNEL 513 add r4, r4, #1 514#endif 515 mov r5, #MPU_RNG_SIZE 516 add r3, r6, #MPU_RNG_INFO_RNGS 517 mla r3, r4, r5, r3 518 5191: 520 sub r3, r3, #MPU_RNG_SIZE 521 sub r4, r4, #1 522 523 mcr p15, 0, r4, c6, c2, 1 @ PRSEL 524 isb 525 526 ldr r5, [r3, #MPU_RGN_PRBAR] 527 ldr r6, [r3, #MPU_RGN_PRLAR] 528 529 mcr p15, 0, r5, c6, c3, 0 @ PRBAR 530 mcr p15, 0, r6, c6, c3, 1 @ PRLAR 531 532 cmp r4, #0 533 bgt 1b 534 535 ret lr 536ENDPROC(__secondary_setup_pmsa_v8) 537#endif /* CONFIG_SMP */ 538#endif /* CONFIG_ARM_MPU */ 539#include "head-common.S" 540