1// SPDX-License-Identifier: GPL-2.0 2/* 3 * SDM845 SoC device tree source 4 * 5 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 6 */ 7 8#include <dt-bindings/clock/qcom,gcc-sdm845.h> 9#include <dt-bindings/clock/qcom,rpmh.h> 10#include <dt-bindings/interrupt-controller/arm-gic.h> 11#include <dt-bindings/soc/qcom,rpmh-rsc.h> 12 13/ { 14 interrupt-parent = <&intc>; 15 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 aliases { 20 i2c0 = &i2c0; 21 i2c1 = &i2c1; 22 i2c2 = &i2c2; 23 i2c3 = &i2c3; 24 i2c4 = &i2c4; 25 i2c5 = &i2c5; 26 i2c6 = &i2c6; 27 i2c7 = &i2c7; 28 i2c8 = &i2c8; 29 i2c9 = &i2c9; 30 i2c10 = &i2c10; 31 i2c11 = &i2c11; 32 i2c12 = &i2c12; 33 i2c13 = &i2c13; 34 i2c14 = &i2c14; 35 i2c15 = &i2c15; 36 spi0 = &spi0; 37 spi1 = &spi1; 38 spi2 = &spi2; 39 spi3 = &spi3; 40 spi4 = &spi4; 41 spi5 = &spi5; 42 spi6 = &spi6; 43 spi7 = &spi7; 44 spi8 = &spi8; 45 spi9 = &spi9; 46 spi10 = &spi10; 47 spi11 = &spi11; 48 spi12 = &spi12; 49 spi13 = &spi13; 50 spi14 = &spi14; 51 spi15 = &spi15; 52 }; 53 54 chosen { }; 55 56 memory@80000000 { 57 device_type = "memory"; 58 /* We expect the bootloader to fill in the size */ 59 reg = <0 0x80000000 0 0>; 60 }; 61 62 reserved-memory { 63 #address-cells = <2>; 64 #size-cells = <2>; 65 ranges; 66 67 memory@85fc0000 { 68 reg = <0 0x85fc0000 0 0x20000>; 69 no-map; 70 }; 71 72 memory@85fe0000 { 73 compatible = "qcom,cmd-db"; 74 reg = <0x0 0x85fe0000 0x0 0x20000>; 75 no-map; 76 }; 77 78 smem_mem: memory@86000000 { 79 reg = <0x0 0x86000000 0x0 0x200000>; 80 no-map; 81 }; 82 83 memory@86200000 { 84 reg = <0 0x86200000 0 0x2d00000>; 85 no-map; 86 }; 87 }; 88 89 cpus { 90 #address-cells = <2>; 91 #size-cells = <0>; 92 93 CPU0: cpu@0 { 94 device_type = "cpu"; 95 compatible = "qcom,kryo385"; 96 reg = <0x0 0x0>; 97 enable-method = "psci"; 98 next-level-cache = <&L2_0>; 99 L2_0: l2-cache { 100 compatible = "cache"; 101 next-level-cache = <&L3_0>; 102 L3_0: l3-cache { 103 compatible = "cache"; 104 }; 105 }; 106 }; 107 108 CPU1: cpu@100 { 109 device_type = "cpu"; 110 compatible = "qcom,kryo385"; 111 reg = <0x0 0x100>; 112 enable-method = "psci"; 113 next-level-cache = <&L2_100>; 114 L2_100: l2-cache { 115 compatible = "cache"; 116 next-level-cache = <&L3_0>; 117 }; 118 }; 119 120 CPU2: cpu@200 { 121 device_type = "cpu"; 122 compatible = "qcom,kryo385"; 123 reg = <0x0 0x200>; 124 enable-method = "psci"; 125 next-level-cache = <&L2_200>; 126 L2_200: l2-cache { 127 compatible = "cache"; 128 next-level-cache = <&L3_0>; 129 }; 130 }; 131 132 CPU3: cpu@300 { 133 device_type = "cpu"; 134 compatible = "qcom,kryo385"; 135 reg = <0x0 0x300>; 136 enable-method = "psci"; 137 next-level-cache = <&L2_300>; 138 L2_300: l2-cache { 139 compatible = "cache"; 140 next-level-cache = <&L3_0>; 141 }; 142 }; 143 144 CPU4: cpu@400 { 145 device_type = "cpu"; 146 compatible = "qcom,kryo385"; 147 reg = <0x0 0x400>; 148 enable-method = "psci"; 149 next-level-cache = <&L2_400>; 150 L2_400: l2-cache { 151 compatible = "cache"; 152 next-level-cache = <&L3_0>; 153 }; 154 }; 155 156 CPU5: cpu@500 { 157 device_type = "cpu"; 158 compatible = "qcom,kryo385"; 159 reg = <0x0 0x500>; 160 enable-method = "psci"; 161 next-level-cache = <&L2_500>; 162 L2_500: l2-cache { 163 compatible = "cache"; 164 next-level-cache = <&L3_0>; 165 }; 166 }; 167 168 CPU6: cpu@600 { 169 device_type = "cpu"; 170 compatible = "qcom,kryo385"; 171 reg = <0x0 0x600>; 172 enable-method = "psci"; 173 next-level-cache = <&L2_600>; 174 L2_600: l2-cache { 175 compatible = "cache"; 176 next-level-cache = <&L3_0>; 177 }; 178 }; 179 180 CPU7: cpu@700 { 181 device_type = "cpu"; 182 compatible = "qcom,kryo385"; 183 reg = <0x0 0x700>; 184 enable-method = "psci"; 185 next-level-cache = <&L2_700>; 186 L2_700: l2-cache { 187 compatible = "cache"; 188 next-level-cache = <&L3_0>; 189 }; 190 }; 191 }; 192 193 pmu { 194 compatible = "arm,armv8-pmuv3"; 195 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>; 196 }; 197 198 timer { 199 compatible = "arm,armv8-timer"; 200 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>, 201 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>, 202 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>, 203 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>; 204 }; 205 206 clocks { 207 xo_board: xo-board { 208 compatible = "fixed-clock"; 209 #clock-cells = <0>; 210 clock-frequency = <38400000>; 211 clock-output-names = "xo_board"; 212 }; 213 214 sleep_clk: sleep-clk { 215 compatible = "fixed-clock"; 216 #clock-cells = <0>; 217 clock-frequency = <32764>; 218 }; 219 }; 220 221 tcsr_mutex: hwlock { 222 compatible = "qcom,tcsr-mutex"; 223 syscon = <&tcsr_mutex_regs 0 0x1000>; 224 #hwlock-cells = <1>; 225 }; 226 227 smem { 228 compatible = "qcom,smem"; 229 memory-region = <&smem_mem>; 230 hwlocks = <&tcsr_mutex 3>; 231 }; 232 233 psci { 234 compatible = "arm,psci-1.0"; 235 method = "smc"; 236 }; 237 238 soc: soc { 239 #address-cells = <1>; 240 #size-cells = <1>; 241 ranges = <0 0 0 0xffffffff>; 242 compatible = "simple-bus"; 243 244 gcc: clock-controller@100000 { 245 compatible = "qcom,gcc-sdm845"; 246 reg = <0x100000 0x1f0000>; 247 #clock-cells = <1>; 248 #reset-cells = <1>; 249 #power-domain-cells = <1>; 250 }; 251 252 qupv3_id_0: geniqup@8c0000 { 253 compatible = "qcom,geni-se-qup"; 254 reg = <0x8c0000 0x6000>; 255 clock-names = "m-ahb", "s-ahb"; 256 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 257 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 258 #address-cells = <1>; 259 #size-cells = <1>; 260 ranges; 261 status = "disabled"; 262 263 i2c0: i2c@880000 { 264 compatible = "qcom,geni-i2c"; 265 reg = <0x880000 0x4000>; 266 clock-names = "se"; 267 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 268 pinctrl-names = "default"; 269 pinctrl-0 = <&qup_i2c0_default>; 270 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 271 #address-cells = <1>; 272 #size-cells = <0>; 273 status = "disabled"; 274 }; 275 276 spi0: spi@880000 { 277 compatible = "qcom,geni-spi"; 278 reg = <0x880000 0x4000>; 279 clock-names = "se"; 280 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 281 pinctrl-names = "default"; 282 pinctrl-0 = <&qup_spi0_default>; 283 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 284 #address-cells = <1>; 285 #size-cells = <0>; 286 status = "disabled"; 287 }; 288 289 i2c1: i2c@884000 { 290 compatible = "qcom,geni-i2c"; 291 reg = <0x884000 0x4000>; 292 clock-names = "se"; 293 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 294 pinctrl-names = "default"; 295 pinctrl-0 = <&qup_i2c1_default>; 296 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 297 #address-cells = <1>; 298 #size-cells = <0>; 299 status = "disabled"; 300 }; 301 302 spi1: spi@884000 { 303 compatible = "qcom,geni-spi"; 304 reg = <0x884000 0x4000>; 305 clock-names = "se"; 306 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 307 pinctrl-names = "default"; 308 pinctrl-0 = <&qup_spi1_default>; 309 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 310 #address-cells = <1>; 311 #size-cells = <0>; 312 status = "disabled"; 313 }; 314 315 i2c2: i2c@888000 { 316 compatible = "qcom,geni-i2c"; 317 reg = <0x888000 0x4000>; 318 clock-names = "se"; 319 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&qup_i2c2_default>; 322 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 status = "disabled"; 326 }; 327 328 spi2: spi@888000 { 329 compatible = "qcom,geni-spi"; 330 reg = <0x888000 0x4000>; 331 clock-names = "se"; 332 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 333 pinctrl-names = "default"; 334 pinctrl-0 = <&qup_spi2_default>; 335 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 336 #address-cells = <1>; 337 #size-cells = <0>; 338 status = "disabled"; 339 }; 340 341 i2c3: i2c@88c000 { 342 compatible = "qcom,geni-i2c"; 343 reg = <0x88c000 0x4000>; 344 clock-names = "se"; 345 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 346 pinctrl-names = "default"; 347 pinctrl-0 = <&qup_i2c3_default>; 348 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 349 #address-cells = <1>; 350 #size-cells = <0>; 351 status = "disabled"; 352 }; 353 354 spi3: spi@88c000 { 355 compatible = "qcom,geni-spi"; 356 reg = <0x88c000 0x4000>; 357 clock-names = "se"; 358 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 359 pinctrl-names = "default"; 360 pinctrl-0 = <&qup_spi3_default>; 361 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 362 #address-cells = <1>; 363 #size-cells = <0>; 364 status = "disabled"; 365 }; 366 367 i2c4: i2c@890000 { 368 compatible = "qcom,geni-i2c"; 369 reg = <0x890000 0x4000>; 370 clock-names = "se"; 371 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 372 pinctrl-names = "default"; 373 pinctrl-0 = <&qup_i2c4_default>; 374 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 status = "disabled"; 378 }; 379 380 spi4: spi@890000 { 381 compatible = "qcom,geni-spi"; 382 reg = <0x890000 0x4000>; 383 clock-names = "se"; 384 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&qup_spi4_default>; 387 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 status = "disabled"; 391 }; 392 393 i2c5: i2c@894000 { 394 compatible = "qcom,geni-i2c"; 395 reg = <0x894000 0x4000>; 396 clock-names = "se"; 397 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 398 pinctrl-names = "default"; 399 pinctrl-0 = <&qup_i2c5_default>; 400 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 401 #address-cells = <1>; 402 #size-cells = <0>; 403 status = "disabled"; 404 }; 405 406 spi5: spi@894000 { 407 compatible = "qcom,geni-spi"; 408 reg = <0x894000 0x4000>; 409 clock-names = "se"; 410 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 411 pinctrl-names = "default"; 412 pinctrl-0 = <&qup_spi5_default>; 413 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 414 #address-cells = <1>; 415 #size-cells = <0>; 416 status = "disabled"; 417 }; 418 419 i2c6: i2c@898000 { 420 compatible = "qcom,geni-i2c"; 421 reg = <0x898000 0x4000>; 422 clock-names = "se"; 423 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 424 pinctrl-names = "default"; 425 pinctrl-0 = <&qup_i2c6_default>; 426 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 427 #address-cells = <1>; 428 #size-cells = <0>; 429 status = "disabled"; 430 }; 431 432 spi6: spi@898000 { 433 compatible = "qcom,geni-spi"; 434 reg = <0x898000 0x4000>; 435 clock-names = "se"; 436 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 437 pinctrl-names = "default"; 438 pinctrl-0 = <&qup_spi6_default>; 439 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 440 #address-cells = <1>; 441 #size-cells = <0>; 442 status = "disabled"; 443 }; 444 445 i2c7: i2c@89c000 { 446 compatible = "qcom,geni-i2c"; 447 reg = <0x89c000 0x4000>; 448 clock-names = "se"; 449 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 450 pinctrl-names = "default"; 451 pinctrl-0 = <&qup_i2c7_default>; 452 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 453 #address-cells = <1>; 454 #size-cells = <0>; 455 status = "disabled"; 456 }; 457 458 spi7: spi@89c000 { 459 compatible = "qcom,geni-spi"; 460 reg = <0x89c000 0x4000>; 461 clock-names = "se"; 462 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&qup_spi7_default>; 465 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 466 #address-cells = <1>; 467 #size-cells = <0>; 468 status = "disabled"; 469 }; 470 }; 471 472 qupv3_id_1: geniqup@ac0000 { 473 compatible = "qcom,geni-se-qup"; 474 reg = <0xac0000 0x6000>; 475 clock-names = "m-ahb", "s-ahb"; 476 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 477 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 478 #address-cells = <1>; 479 #size-cells = <1>; 480 ranges; 481 status = "disabled"; 482 483 i2c8: i2c@a80000 { 484 compatible = "qcom,geni-i2c"; 485 reg = <0xa80000 0x4000>; 486 clock-names = "se"; 487 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 488 pinctrl-names = "default"; 489 pinctrl-0 = <&qup_i2c8_default>; 490 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 491 #address-cells = <1>; 492 #size-cells = <0>; 493 status = "disabled"; 494 }; 495 496 spi8: spi@a80000 { 497 compatible = "qcom,geni-spi"; 498 reg = <0xa80000 0x4000>; 499 clock-names = "se"; 500 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 501 pinctrl-names = "default"; 502 pinctrl-0 = <&qup_spi8_default>; 503 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 504 #address-cells = <1>; 505 #size-cells = <0>; 506 status = "disabled"; 507 }; 508 509 i2c9: i2c@a84000 { 510 compatible = "qcom,geni-i2c"; 511 reg = <0xa84000 0x4000>; 512 clock-names = "se"; 513 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 514 pinctrl-names = "default"; 515 pinctrl-0 = <&qup_i2c9_default>; 516 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 517 #address-cells = <1>; 518 #size-cells = <0>; 519 status = "disabled"; 520 }; 521 522 spi9: spi@a84000 { 523 compatible = "qcom,geni-spi"; 524 reg = <0xa84000 0x4000>; 525 clock-names = "se"; 526 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 527 pinctrl-names = "default"; 528 pinctrl-0 = <&qup_spi9_default>; 529 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 530 #address-cells = <1>; 531 #size-cells = <0>; 532 status = "disabled"; 533 }; 534 535 uart9: serial@a84000 { 536 compatible = "qcom,geni-debug-uart"; 537 reg = <0xa84000 0x4000>; 538 clock-names = "se"; 539 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 540 pinctrl-names = "default"; 541 pinctrl-0 = <&qup_uart9_default>; 542 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 543 status = "disabled"; 544 }; 545 546 i2c10: i2c@a88000 { 547 compatible = "qcom,geni-i2c"; 548 reg = <0xa88000 0x4000>; 549 clock-names = "se"; 550 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 551 pinctrl-names = "default"; 552 pinctrl-0 = <&qup_i2c10_default>; 553 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 status = "disabled"; 557 }; 558 559 spi10: spi@a88000 { 560 compatible = "qcom,geni-spi"; 561 reg = <0xa88000 0x4000>; 562 clock-names = "se"; 563 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 564 pinctrl-names = "default"; 565 pinctrl-0 = <&qup_spi10_default>; 566 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 status = "disabled"; 570 }; 571 572 i2c11: i2c@a8c000 { 573 compatible = "qcom,geni-i2c"; 574 reg = <0xa8c000 0x4000>; 575 clock-names = "se"; 576 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 577 pinctrl-names = "default"; 578 pinctrl-0 = <&qup_i2c11_default>; 579 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 580 #address-cells = <1>; 581 #size-cells = <0>; 582 status = "disabled"; 583 }; 584 585 spi11: spi@a8c000 { 586 compatible = "qcom,geni-spi"; 587 reg = <0xa8c000 0x4000>; 588 clock-names = "se"; 589 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 590 pinctrl-names = "default"; 591 pinctrl-0 = <&qup_spi11_default>; 592 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 593 #address-cells = <1>; 594 #size-cells = <0>; 595 status = "disabled"; 596 }; 597 598 i2c12: i2c@a90000 { 599 compatible = "qcom,geni-i2c"; 600 reg = <0xa90000 0x4000>; 601 clock-names = "se"; 602 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 603 pinctrl-names = "default"; 604 pinctrl-0 = <&qup_i2c12_default>; 605 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 606 #address-cells = <1>; 607 #size-cells = <0>; 608 status = "disabled"; 609 }; 610 611 spi12: spi@a90000 { 612 compatible = "qcom,geni-spi"; 613 reg = <0xa90000 0x4000>; 614 clock-names = "se"; 615 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 616 pinctrl-names = "default"; 617 pinctrl-0 = <&qup_spi12_default>; 618 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 619 #address-cells = <1>; 620 #size-cells = <0>; 621 status = "disabled"; 622 }; 623 624 i2c13: i2c@a94000 { 625 compatible = "qcom,geni-i2c"; 626 reg = <0xa94000 0x4000>; 627 clock-names = "se"; 628 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 629 pinctrl-names = "default"; 630 pinctrl-0 = <&qup_i2c13_default>; 631 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 632 #address-cells = <1>; 633 #size-cells = <0>; 634 status = "disabled"; 635 }; 636 637 spi13: spi@a94000 { 638 compatible = "qcom,geni-spi"; 639 reg = <0xa94000 0x4000>; 640 clock-names = "se"; 641 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 642 pinctrl-names = "default"; 643 pinctrl-0 = <&qup_spi13_default>; 644 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 645 #address-cells = <1>; 646 #size-cells = <0>; 647 status = "disabled"; 648 }; 649 650 i2c14: i2c@a98000 { 651 compatible = "qcom,geni-i2c"; 652 reg = <0xa98000 0x4000>; 653 clock-names = "se"; 654 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 655 pinctrl-names = "default"; 656 pinctrl-0 = <&qup_i2c14_default>; 657 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 658 #address-cells = <1>; 659 #size-cells = <0>; 660 status = "disabled"; 661 }; 662 663 spi14: spi@a98000 { 664 compatible = "qcom,geni-spi"; 665 reg = <0xa98000 0x4000>; 666 clock-names = "se"; 667 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 668 pinctrl-names = "default"; 669 pinctrl-0 = <&qup_spi14_default>; 670 interrupts = <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>; 671 #address-cells = <1>; 672 #size-cells = <0>; 673 status = "disabled"; 674 }; 675 676 i2c15: i2c@a9c000 { 677 compatible = "qcom,geni-i2c"; 678 reg = <0xa9c000 0x4000>; 679 clock-names = "se"; 680 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&qup_i2c15_default>; 683 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 684 #address-cells = <1>; 685 #size-cells = <0>; 686 status = "disabled"; 687 }; 688 689 spi15: spi@a9c000 { 690 compatible = "qcom,geni-spi"; 691 reg = <0xa9c000 0x4000>; 692 clock-names = "se"; 693 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 694 pinctrl-names = "default"; 695 pinctrl-0 = <&qup_spi15_default>; 696 interrupts = <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>; 697 #address-cells = <1>; 698 #size-cells = <0>; 699 status = "disabled"; 700 }; 701 }; 702 703 tcsr_mutex_regs: syscon@1f40000 { 704 compatible = "syscon"; 705 reg = <0x1f40000 0x40000>; 706 }; 707 708 tlmm: pinctrl@3400000 { 709 compatible = "qcom,sdm845-pinctrl"; 710 reg = <0x03400000 0xc00000>; 711 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 712 gpio-controller; 713 #gpio-cells = <2>; 714 interrupt-controller; 715 #interrupt-cells = <2>; 716 717 qup_i2c0_default: qup-i2c0-default { 718 pinmux { 719 pins = "gpio0", "gpio1"; 720 function = "qup0"; 721 }; 722 }; 723 724 qup_i2c1_default: qup-i2c1-default { 725 pinmux { 726 pins = "gpio17", "gpio18"; 727 function = "qup1"; 728 }; 729 }; 730 731 qup_i2c2_default: qup-i2c2-default { 732 pinmux { 733 pins = "gpio27", "gpio28"; 734 function = "qup2"; 735 }; 736 }; 737 738 qup_i2c3_default: qup-i2c3-default { 739 pinmux { 740 pins = "gpio41", "gpio42"; 741 function = "qup3"; 742 }; 743 }; 744 745 qup_i2c4_default: qup-i2c4-default { 746 pinmux { 747 pins = "gpio89", "gpio90"; 748 function = "qup4"; 749 }; 750 }; 751 752 qup_i2c5_default: qup-i2c5-default { 753 pinmux { 754 pins = "gpio85", "gpio86"; 755 function = "qup5"; 756 }; 757 }; 758 759 qup_i2c6_default: qup-i2c6-default { 760 pinmux { 761 pins = "gpio45", "gpio46"; 762 function = "qup6"; 763 }; 764 }; 765 766 qup_i2c7_default: qup-i2c7-default { 767 pinmux { 768 pins = "gpio93", "gpio94"; 769 function = "qup7"; 770 }; 771 }; 772 773 qup_i2c8_default: qup-i2c8-default { 774 pinmux { 775 pins = "gpio65", "gpio66"; 776 function = "qup8"; 777 }; 778 }; 779 780 qup_i2c9_default: qup-i2c9-default { 781 pinmux { 782 pins = "gpio6", "gpio7"; 783 function = "qup9"; 784 }; 785 }; 786 787 qup_i2c10_default: qup-i2c10-default { 788 pinmux { 789 pins = "gpio55", "gpio56"; 790 function = "qup10"; 791 }; 792 }; 793 794 qup_i2c11_default: qup-i2c11-default { 795 pinmux { 796 pins = "gpio31", "gpio32"; 797 function = "qup11"; 798 }; 799 }; 800 801 qup_i2c12_default: qup-i2c12-default { 802 pinmux { 803 pins = "gpio49", "gpio50"; 804 function = "qup12"; 805 }; 806 }; 807 808 qup_i2c13_default: qup-i2c13-default { 809 pinmux { 810 pins = "gpio105", "gpio106"; 811 function = "qup13"; 812 }; 813 }; 814 815 qup_i2c14_default: qup-i2c14-default { 816 pinmux { 817 pins = "gpio33", "gpio34"; 818 function = "qup14"; 819 }; 820 }; 821 822 qup_i2c15_default: qup-i2c15-default { 823 pinmux { 824 pins = "gpio81", "gpio82"; 825 function = "qup15"; 826 }; 827 }; 828 829 qup_spi0_default: qup-spi0-default { 830 pinmux { 831 pins = "gpio0", "gpio1", 832 "gpio2", "gpio3"; 833 function = "qup0"; 834 }; 835 }; 836 837 qup_spi1_default: qup-spi1-default { 838 pinmux { 839 pins = "gpio17", "gpio18", 840 "gpio19", "gpio20"; 841 function = "qup1"; 842 }; 843 }; 844 845 qup_spi2_default: qup-spi2-default { 846 pinmux { 847 pins = "gpio27", "gpio28", 848 "gpio29", "gpio30"; 849 function = "qup2"; 850 }; 851 }; 852 853 qup_spi3_default: qup-spi3-default { 854 pinmux { 855 pins = "gpio41", "gpio42", 856 "gpio43", "gpio44"; 857 function = "qup3"; 858 }; 859 }; 860 861 qup_spi4_default: qup-spi4-default { 862 pinmux { 863 pins = "gpio89", "gpio90", 864 "gpio91", "gpio92"; 865 function = "qup4"; 866 }; 867 }; 868 869 qup_spi5_default: qup-spi5-default { 870 pinmux { 871 pins = "gpio85", "gpio86", 872 "gpio87", "gpio88"; 873 function = "qup5"; 874 }; 875 }; 876 877 qup_spi6_default: qup-spi6-default { 878 pinmux { 879 pins = "gpio45", "gpio46", 880 "gpio47", "gpio48"; 881 function = "qup6"; 882 }; 883 }; 884 885 qup_spi7_default: qup-spi7-default { 886 pinmux { 887 pins = "gpio93", "gpio94", 888 "gpio95", "gpio96"; 889 function = "qup7"; 890 }; 891 }; 892 893 qup_spi8_default: qup-spi8-default { 894 pinmux { 895 pins = "gpio65", "gpio66", 896 "gpio67", "gpio68"; 897 function = "qup8"; 898 }; 899 }; 900 901 qup_spi9_default: qup-spi9-default { 902 pinmux { 903 pins = "gpio6", "gpio7", 904 "gpio4", "gpio5"; 905 function = "qup9"; 906 }; 907 }; 908 909 qup_spi10_default: qup-spi10-default { 910 pinmux { 911 pins = "gpio55", "gpio56", 912 "gpio53", "gpio54"; 913 function = "qup10"; 914 }; 915 }; 916 917 qup_spi11_default: qup-spi11-default { 918 pinmux { 919 pins = "gpio31", "gpio32", 920 "gpio33", "gpio34"; 921 function = "qup11"; 922 }; 923 }; 924 925 qup_spi12_default: qup-spi12-default { 926 pinmux { 927 pins = "gpio49", "gpio50", 928 "gpio51", "gpio52"; 929 function = "qup12"; 930 }; 931 }; 932 933 qup_spi13_default: qup-spi13-default { 934 pinmux { 935 pins = "gpio105", "gpio106", 936 "gpio107", "gpio108"; 937 function = "qup13"; 938 }; 939 }; 940 941 qup_spi14_default: qup-spi14-default { 942 pinmux { 943 pins = "gpio33", "gpio34", 944 "gpio31", "gpio32"; 945 function = "qup14"; 946 }; 947 }; 948 949 qup_spi15_default: qup-spi15-default { 950 pinmux { 951 pins = "gpio81", "gpio82", 952 "gpio83", "gpio84"; 953 function = "qup15"; 954 }; 955 }; 956 957 qup_uart9_default: qup-uart9-default { 958 pinmux { 959 pins = "gpio4", "gpio5"; 960 function = "qup9"; 961 }; 962 }; 963 }; 964 965 tsens0: thermal-sensor@c263000 { 966 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 967 reg = <0xc263000 0x1ff>, /* TM */ 968 <0xc222000 0x1ff>; /* SROT */ 969 #qcom,sensors = <13>; 970 #thermal-sensor-cells = <1>; 971 }; 972 973 tsens1: thermal-sensor@c265000 { 974 compatible = "qcom,sdm845-tsens", "qcom,tsens-v2"; 975 reg = <0xc265000 0x1ff>, /* TM */ 976 <0xc223000 0x1ff>; /* SROT */ 977 #qcom,sensors = <8>; 978 #thermal-sensor-cells = <1>; 979 }; 980 981 spmi_bus: spmi@c440000 { 982 compatible = "qcom,spmi-pmic-arb"; 983 reg = <0xc440000 0x1100>, 984 <0xc600000 0x2000000>, 985 <0xe600000 0x100000>, 986 <0xe700000 0xa0000>, 987 <0xc40a000 0x26000>; 988 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 989 interrupt-names = "periph_irq"; 990 interrupts = <GIC_SPI 481 IRQ_TYPE_LEVEL_HIGH>; 991 qcom,ee = <0>; 992 qcom,channel = <0>; 993 #address-cells = <2>; 994 #size-cells = <0>; 995 interrupt-controller; 996 #interrupt-cells = <4>; 997 cell-index = <0>; 998 }; 999 1000 apss_shared: mailbox@17990000 { 1001 compatible = "qcom,sdm845-apss-shared"; 1002 reg = <0x17990000 0x1000>; 1003 #mbox-cells = <1>; 1004 }; 1005 1006 apps_rsc: rsc@179c0000 { 1007 label = "apps_rsc"; 1008 compatible = "qcom,rpmh-rsc"; 1009 reg = <0x179c0000 0x10000>, 1010 <0x179d0000 0x10000>, 1011 <0x179e0000 0x10000>; 1012 reg-names = "drv-0", "drv-1", "drv-2"; 1013 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1014 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1015 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1016 qcom,tcs-offset = <0xd00>; 1017 qcom,drv-id = <2>; 1018 qcom,tcs-config = <ACTIVE_TCS 2>, 1019 <SLEEP_TCS 3>, 1020 <WAKE_TCS 3>, 1021 <CONTROL_TCS 1>; 1022 1023 rpmhcc: clock-controller { 1024 compatible = "qcom,sdm845-rpmh-clk"; 1025 #clock-cells = <1>; 1026 }; 1027 }; 1028 1029 intc: interrupt-controller@17a00000 { 1030 compatible = "arm,gic-v3"; 1031 #address-cells = <1>; 1032 #size-cells = <1>; 1033 ranges; 1034 #interrupt-cells = <3>; 1035 interrupt-controller; 1036 reg = <0x17a00000 0x10000>, /* GICD */ 1037 <0x17a60000 0x100000>; /* GICR * 8 */ 1038 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1039 1040 gic-its@17a40000 { 1041 compatible = "arm,gic-v3-its"; 1042 msi-controller; 1043 #msi-cells = <1>; 1044 reg = <0x17a40000 0x20000>; 1045 status = "disabled"; 1046 }; 1047 }; 1048 1049 timer@17c90000 { 1050 #address-cells = <1>; 1051 #size-cells = <1>; 1052 ranges; 1053 compatible = "arm,armv7-timer-mem"; 1054 reg = <0x17c90000 0x1000>; 1055 1056 frame@17ca0000 { 1057 frame-number = <0>; 1058 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1060 reg = <0x17ca0000 0x1000>, 1061 <0x17cb0000 0x1000>; 1062 }; 1063 1064 frame@17cc0000 { 1065 frame-number = <1>; 1066 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1067 reg = <0x17cc0000 0x1000>; 1068 status = "disabled"; 1069 }; 1070 1071 frame@17cd0000 { 1072 frame-number = <2>; 1073 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 1074 reg = <0x17cd0000 0x1000>; 1075 status = "disabled"; 1076 }; 1077 1078 frame@17ce0000 { 1079 frame-number = <3>; 1080 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 1081 reg = <0x17ce0000 0x1000>; 1082 status = "disabled"; 1083 }; 1084 1085 frame@17cf0000 { 1086 frame-number = <4>; 1087 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1088 reg = <0x17cf0000 0x1000>; 1089 status = "disabled"; 1090 }; 1091 1092 frame@17d00000 { 1093 frame-number = <5>; 1094 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1095 reg = <0x17d00000 0x1000>; 1096 status = "disabled"; 1097 }; 1098 1099 frame@17d10000 { 1100 frame-number = <6>; 1101 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1102 reg = <0x17d10000 0x1000>; 1103 status = "disabled"; 1104 }; 1105 }; 1106 }; 1107}; 1108