1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the Condor board 4 * 5 * Copyright (C) 2018 Renesas Electronics Corp. 6 * Copyright (C) 2018 Cogent Embedded, Inc. 7 */ 8 9/dts-v1/; 10#include "r8a77980.dtsi" 11 12/ { 13 model = "Renesas Condor board based on r8a77980"; 14 compatible = "renesas,condor", "renesas,r8a77980"; 15 16 aliases { 17 serial0 = &scif0; 18 ethernet0 = &gether; 19 }; 20 21 chosen { 22 stdout-path = "serial0:115200n8"; 23 }; 24 25 memory@48000000 { 26 device_type = "memory"; 27 /* first 128MB is reserved for secure area. */ 28 reg = <0 0x48000000 0 0x78000000>; 29 }; 30 31 d3_3v: regulator-0 { 32 compatible = "regulator-fixed"; 33 regulator-name = "D3.3V"; 34 regulator-min-microvolt = <3300000>; 35 regulator-max-microvolt = <3300000>; 36 regulator-boot-on; 37 regulator-always-on; 38 }; 39 40 vddq_vin01: regulator-1 { 41 compatible = "regulator-fixed"; 42 regulator-name = "VDDQ_VIN01"; 43 regulator-min-microvolt = <1800000>; 44 regulator-max-microvolt = <1800000>; 45 regulator-boot-on; 46 regulator-always-on; 47 }; 48}; 49 50&canfd { 51 pinctrl-0 = <&canfd0_pins>; 52 pinctrl-names = "default"; 53 status = "okay"; 54 55 channel0 { 56 status = "okay"; 57 }; 58}; 59 60&extal_clk { 61 clock-frequency = <16666666>; 62}; 63 64&extalr_clk { 65 clock-frequency = <32768>; 66}; 67 68&gether { 69 pinctrl-0 = <&gether_pins>; 70 pinctrl-names = "default"; 71 72 phy-mode = "rgmii-id"; 73 phy-handle = <&phy0>; 74 renesas,no-ether-link; 75 status = "okay"; 76 77 phy0: ethernet-phy@0 { 78 rxc-skew-ps = <1500>; 79 reg = <0>; 80 interrupt-parent = <&gpio4>; 81 interrupts = <23 IRQ_TYPE_LEVEL_LOW>; 82 }; 83}; 84 85&i2c0 { 86 pinctrl-0 = <&i2c0_pins>; 87 pinctrl-names = "default"; 88 89 status = "okay"; 90 clock-frequency = <400000>; 91 92 io_expander0: gpio@20 { 93 compatible = "onnn,pca9654"; 94 reg = <0x20>; 95 gpio-controller; 96 #gpio-cells = <2>; 97 }; 98 99 io_expander1: gpio@21 { 100 compatible = "onnn,pca9654"; 101 reg = <0x21>; 102 gpio-controller; 103 #gpio-cells = <2>; 104 }; 105}; 106 107&mmc0 { 108 pinctrl-0 = <&mmc_pins>; 109 pinctrl-1 = <&mmc_pins_uhs>; 110 pinctrl-names = "default", "state_uhs"; 111 112 vmmc-supply = <&d3_3v>; 113 vqmmc-supply = <&vddq_vin01>; 114 mmc-hs200-1_8v; 115 bus-width = <8>; 116 non-removable; 117 status = "okay"; 118}; 119 120&pfc { 121 canfd0_pins: canfd0 { 122 groups = "canfd0_data_a"; 123 function = "canfd0"; 124 }; 125 126 gether_pins: gether { 127 groups = "gether_mdio_a", "gether_rgmii", 128 "gether_txcrefclk", "gether_txcrefclk_mega"; 129 function = "gether"; 130 }; 131 132 i2c0_pins: i2c0 { 133 groups = "i2c0"; 134 function = "i2c0"; 135 }; 136 137 mmc_pins: mmc { 138 groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; 139 function = "mmc"; 140 power-source = <3300>; 141 }; 142 143 mmc_pins_uhs: mmc_uhs { 144 groups = "mmc_data8", "mmc_ctrl", "mmc_ds"; 145 function = "mmc"; 146 power-source = <1800>; 147 }; 148 149 scif0_pins: scif0 { 150 groups = "scif0_data"; 151 function = "scif0"; 152 }; 153 154 scif_clk_pins: scif_clk { 155 groups = "scif_clk_b"; 156 function = "scif_clk"; 157 }; 158}; 159 160&scif0 { 161 pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>; 162 pinctrl-names = "default"; 163 164 status = "okay"; 165}; 166 167&scif_clk { 168 clock-frequency = <14745600>; 169}; 170